blob: 65c1833244f728f6ff5cadf87cad6f9030a73181 [file] [log] [blame]
Auke Kok9d5c8242008-01-24 02:22:38 -08001/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
Alexander Duyck86d5d382009-02-06 23:23:12 +00004 Copyright(c) 2007-2009 Intel Corporation.
Auke Kok9d5c8242008-01-24 02:22:38 -08005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
32#include <linux/types.h>
Alexander Duyck2d064c02008-07-08 15:10:12 -070033#include <linux/if_ether.h>
Auke Kok9d5c8242008-01-24 02:22:38 -080034
35#include "e1000_mac.h"
36#include "e1000_82575.h"
37
38static s32 igb_get_invariants_82575(struct e1000_hw *);
39static s32 igb_acquire_phy_82575(struct e1000_hw *);
40static void igb_release_phy_82575(struct e1000_hw *);
41static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42static void igb_release_nvm_82575(struct e1000_hw *);
43static s32 igb_check_for_link_82575(struct e1000_hw *);
44static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45static s32 igb_init_hw_82575(struct e1000_hw *);
46static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
Alexander Duyckbb2ac472009-11-19 12:42:01 +000048static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
Auke Kok9d5c8242008-01-24 02:22:38 -080050static s32 igb_reset_hw_82575(struct e1000_hw *);
Alexander Duyckbb2ac472009-11-19 12:42:01 +000051static s32 igb_reset_hw_82580(struct e1000_hw *);
Auke Kok9d5c8242008-01-24 02:22:38 -080052static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53static s32 igb_setup_copper_link_82575(struct e1000_hw *);
Alexander Duyck2fb02a22009-09-14 08:22:54 +000054static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
Auke Kok9d5c8242008-01-24 02:22:38 -080055static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
56static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
57static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
Auke Kok9d5c8242008-01-24 02:22:38 -080058static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
59 u16 *);
60static s32 igb_get_phy_id_82575(struct e1000_hw *);
61static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
62static bool igb_sgmii_active_82575(struct e1000_hw *);
63static s32 igb_reset_init_script_82575(struct e1000_hw *);
64static s32 igb_read_mac_addr_82575(struct e1000_hw *);
Alexander Duyck009bc062009-07-23 18:08:35 +000065static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
Alexander Duyck99870a72010-08-03 11:50:08 +000066static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
Auke Kok9d5c8242008-01-24 02:22:38 -080067
Alexander Duyckbb2ac472009-11-19 12:42:01 +000068static const u16 e1000_82580_rxpbs_table[] =
69 { 36, 72, 144, 1, 2, 4, 8, 16,
70 35, 70, 140 };
71#define E1000_82580_RXPBS_TABLE_SIZE \
72 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
73
Nick Nunley4085f742010-07-26 13:15:06 +000074/**
75 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
76 * @hw: pointer to the HW structure
77 *
78 * Called to determine if the I2C pins are being used for I2C or as an
79 * external MDIO interface since the two options are mutually exclusive.
80 **/
81static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
82{
83 u32 reg = 0;
84 bool ext_mdio = false;
85
86 switch (hw->mac.type) {
87 case e1000_82575:
88 case e1000_82576:
89 reg = rd32(E1000_MDIC);
90 ext_mdio = !!(reg & E1000_MDIC_DEST);
91 break;
92 case e1000_82580:
93 case e1000_i350:
94 reg = rd32(E1000_MDICNFG);
95 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
96 break;
97 default:
98 break;
99 }
100 return ext_mdio;
101}
102
Auke Kok9d5c8242008-01-24 02:22:38 -0800103static s32 igb_get_invariants_82575(struct e1000_hw *hw)
104{
105 struct e1000_phy_info *phy = &hw->phy;
106 struct e1000_nvm_info *nvm = &hw->nvm;
107 struct e1000_mac_info *mac = &hw->mac;
Alexander Duyckc1889bf2009-02-06 23:16:45 +0000108 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
Auke Kok9d5c8242008-01-24 02:22:38 -0800109 u32 eecd;
110 s32 ret_val;
111 u16 size;
112 u32 ctrl_ext = 0;
113
114 switch (hw->device_id) {
115 case E1000_DEV_ID_82575EB_COPPER:
116 case E1000_DEV_ID_82575EB_FIBER_SERDES:
117 case E1000_DEV_ID_82575GB_QUAD_COPPER:
118 mac->type = e1000_82575;
119 break;
Alexander Duyck2d064c02008-07-08 15:10:12 -0700120 case E1000_DEV_ID_82576:
Alexander Duyck9eb23412009-03-13 20:42:15 +0000121 case E1000_DEV_ID_82576_NS:
Alexander Duyck747d49b2009-10-05 06:33:27 +0000122 case E1000_DEV_ID_82576_NS_SERDES:
Alexander Duyck2d064c02008-07-08 15:10:12 -0700123 case E1000_DEV_ID_82576_FIBER:
124 case E1000_DEV_ID_82576_SERDES:
Alexander Duyckc8ea5ea2009-03-13 20:42:35 +0000125 case E1000_DEV_ID_82576_QUAD_COPPER:
Carolyn Wybornyb894fa22010-03-19 06:07:48 +0000126 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
Alexander Duyck4703bf72009-07-23 18:09:48 +0000127 case E1000_DEV_ID_82576_SERDES_QUAD:
Alexander Duyck2d064c02008-07-08 15:10:12 -0700128 mac->type = e1000_82576;
129 break;
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000130 case E1000_DEV_ID_82580_COPPER:
131 case E1000_DEV_ID_82580_FIBER:
Carolyn Wyborny6493d242011-01-14 05:33:46 +0000132 case E1000_DEV_ID_82580_QUAD_FIBER:
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000133 case E1000_DEV_ID_82580_SERDES:
134 case E1000_DEV_ID_82580_SGMII:
135 case E1000_DEV_ID_82580_COPPER_DUAL:
Joseph Gasparakis308fb392010-09-22 17:56:44 +0000136 case E1000_DEV_ID_DH89XXCC_SGMII:
137 case E1000_DEV_ID_DH89XXCC_SERDES:
Gasparakis, Joseph1b5dda32010-12-09 01:41:01 +0000138 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
139 case E1000_DEV_ID_DH89XXCC_SFP:
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000140 mac->type = e1000_82580;
141 break;
Alexander Duyckd2ba2ed2010-03-22 14:08:06 +0000142 case E1000_DEV_ID_I350_COPPER:
143 case E1000_DEV_ID_I350_FIBER:
144 case E1000_DEV_ID_I350_SERDES:
145 case E1000_DEV_ID_I350_SGMII:
146 mac->type = e1000_i350;
147 break;
Auke Kok9d5c8242008-01-24 02:22:38 -0800148 default:
149 return -E1000_ERR_MAC_INIT;
150 break;
151 }
152
Auke Kok9d5c8242008-01-24 02:22:38 -0800153 /* Set media type */
154 /*
155 * The 82575 uses bits 22:23 for link mode. The mode can be changed
156 * based on the EEPROM. We cannot rely upon device ID. There
157 * is no distinguishable difference between fiber and internal
158 * SerDes mode on the 82575. There can be an external PHY attached
159 * on the SGMII interface. For this, we'll set sgmii_active to true.
160 */
161 phy->media_type = e1000_media_type_copper;
162 dev_spec->sgmii_active = false;
163
164 ctrl_ext = rd32(E1000_CTRL_EXT);
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000165 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
166 case E1000_CTRL_EXT_LINK_MODE_SGMII:
Auke Kok9d5c8242008-01-24 02:22:38 -0800167 dev_spec->sgmii_active = true;
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000168 break;
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000169 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000170 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
171 hw->phy.media_type = e1000_media_type_internal_serdes;
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000172 break;
173 default:
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000174 break;
Auke Kok9d5c8242008-01-24 02:22:38 -0800175 }
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000176
Auke Kok9d5c8242008-01-24 02:22:38 -0800177 /* Set mta register count */
178 mac->mta_reg_count = 128;
179 /* Set rar entry count */
180 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
Alexander Duyck2d064c02008-07-08 15:10:12 -0700181 if (mac->type == e1000_82576)
182 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000183 if (mac->type == e1000_82580)
184 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
Alexander Duyckd2ba2ed2010-03-22 14:08:06 +0000185 if (mac->type == e1000_i350)
186 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000187 /* reset */
Alexander Duyckd2ba2ed2010-03-22 14:08:06 +0000188 if (mac->type >= e1000_82580)
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000189 mac->ops.reset_hw = igb_reset_hw_82580;
190 else
191 mac->ops.reset_hw = igb_reset_hw_82575;
Auke Kok9d5c8242008-01-24 02:22:38 -0800192 /* Set if part includes ASF firmware */
193 mac->asf_firmware_present = true;
194 /* Set if manageability features are enabled. */
195 mac->arc_subsystem_valid =
196 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
197 ? true : false;
198
199 /* physical interface link setup */
200 mac->ops.setup_physical_interface =
201 (hw->phy.media_type == e1000_media_type_copper)
202 ? igb_setup_copper_link_82575
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000203 : igb_setup_serdes_link_82575;
Auke Kok9d5c8242008-01-24 02:22:38 -0800204
205 /* NVM initialization */
206 eecd = rd32(E1000_EECD);
207
208 nvm->opcode_bits = 8;
209 nvm->delay_usec = 1;
210 switch (nvm->override) {
211 case e1000_nvm_override_spi_large:
212 nvm->page_size = 32;
213 nvm->address_bits = 16;
214 break;
215 case e1000_nvm_override_spi_small:
216 nvm->page_size = 8;
217 nvm->address_bits = 8;
218 break;
219 default:
220 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
221 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
222 break;
223 }
224
225 nvm->type = e1000_nvm_eeprom_spi;
226
227 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
228 E1000_EECD_SIZE_EX_SHIFT);
229
230 /*
231 * Added to a constant, "size" becomes the left-shift value
232 * for setting word_size.
233 */
234 size += NVM_WORD_SIZE_BASE_SHIFT;
Jeff Kirsher5c3cad72008-06-27 10:59:33 -0700235
236 /* EEPROM access above 16k is unsupported */
237 if (size > 14)
238 size = 14;
Auke Kok9d5c8242008-01-24 02:22:38 -0800239 nvm->word_size = 1 << size;
240
Carolyn Wyborny6b78bb12011-01-20 06:40:45 +0000241 /* if part supports SR-IOV then initialize mailbox parameters */
242 switch (mac->type) {
243 case e1000_82576:
244 case e1000_i350:
Alexander Duycka0c98602009-07-23 18:10:43 +0000245 igb_init_mbx_params_pf(hw);
Carolyn Wyborny6b78bb12011-01-20 06:40:45 +0000246 break;
247 default:
248 break;
249 }
Alexander Duycka0c98602009-07-23 18:10:43 +0000250
Auke Kok9d5c8242008-01-24 02:22:38 -0800251 /* setup PHY parameters */
252 if (phy->media_type != e1000_media_type_copper) {
253 phy->type = e1000_phy_none;
254 return 0;
255 }
256
257 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
258 phy->reset_delay_us = 100;
259
Alexander Duyck99870a72010-08-03 11:50:08 +0000260 ctrl_ext = rd32(E1000_CTRL_EXT);
261
Auke Kok9d5c8242008-01-24 02:22:38 -0800262 /* PHY function pointers */
Alexander Duyck99870a72010-08-03 11:50:08 +0000263 if (igb_sgmii_active_82575(hw)) {
Nick Nunley4085f742010-07-26 13:15:06 +0000264 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
Alexander Duyck99870a72010-08-03 11:50:08 +0000265 ctrl_ext |= E1000_CTRL_I2C_ENA;
266 } else {
Nick Nunley4085f742010-07-26 13:15:06 +0000267 phy->ops.reset = igb_phy_hw_reset;
Alexander Duyck99870a72010-08-03 11:50:08 +0000268 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
269 }
270
271 wr32(E1000_CTRL_EXT, ctrl_ext);
272 igb_reset_mdicnfg_82580(hw);
Nick Nunley4085f742010-07-26 13:15:06 +0000273
274 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
275 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
276 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
Alexander Duyckd2ba2ed2010-03-22 14:08:06 +0000277 } else if (hw->mac.type >= e1000_82580) {
Nick Nunley4085f742010-07-26 13:15:06 +0000278 phy->ops.read_reg = igb_read_phy_reg_82580;
279 phy->ops.write_reg = igb_write_phy_reg_82580;
Auke Kok9d5c8242008-01-24 02:22:38 -0800280 } else {
Nick Nunley4085f742010-07-26 13:15:06 +0000281 phy->ops.read_reg = igb_read_phy_reg_igp;
282 phy->ops.write_reg = igb_write_phy_reg_igp;
Auke Kok9d5c8242008-01-24 02:22:38 -0800283 }
284
Alexander Duyck19e588e2009-07-07 13:01:55 +0000285 /* set lan id */
286 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
287 E1000_STATUS_FUNC_SHIFT;
288
Auke Kok9d5c8242008-01-24 02:22:38 -0800289 /* Set phy->phy_addr and phy->id. */
290 ret_val = igb_get_phy_id_82575(hw);
291 if (ret_val)
292 return ret_val;
293
294 /* Verify phy id and set remaining function pointers */
295 switch (phy->id) {
Joseph Gasparakis308fb392010-09-22 17:56:44 +0000296 case I347AT4_E_PHY_ID:
297 case M88E1112_E_PHY_ID:
Auke Kok9d5c8242008-01-24 02:22:38 -0800298 case M88E1111_I_PHY_ID:
299 phy->type = e1000_phy_m88;
300 phy->ops.get_phy_info = igb_get_phy_info_m88;
Joseph Gasparakis308fb392010-09-22 17:56:44 +0000301
302 if (phy->id == I347AT4_E_PHY_ID ||
303 phy->id == M88E1112_E_PHY_ID)
304 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
305 else
306 phy->ops.get_cable_length = igb_get_cable_length_m88;
307
Auke Kok9d5c8242008-01-24 02:22:38 -0800308 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
309 break;
310 case IGP03E1000_E_PHY_ID:
311 phy->type = e1000_phy_igp_3;
312 phy->ops.get_phy_info = igb_get_phy_info_igp;
313 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
314 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
315 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
316 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
317 break;
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000318 case I82580_I_PHY_ID:
Alexander Duyckd2ba2ed2010-03-22 14:08:06 +0000319 case I350_I_PHY_ID:
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000320 phy->type = e1000_phy_82580;
321 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
322 phy->ops.get_cable_length = igb_get_cable_length_82580;
323 phy->ops.get_phy_info = igb_get_phy_info_82580;
324 break;
Auke Kok9d5c8242008-01-24 02:22:38 -0800325 default:
326 return -E1000_ERR_PHY;
327 }
328
329 return 0;
330}
331
332/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700333 * igb_acquire_phy_82575 - Acquire rights to access PHY
Auke Kok9d5c8242008-01-24 02:22:38 -0800334 * @hw: pointer to the HW structure
335 *
336 * Acquire access rights to the correct PHY. This is a
337 * function pointer entry point called by the api module.
338 **/
339static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
340{
Alexander Duyck008c3422009-10-05 06:32:07 +0000341 u16 mask = E1000_SWFW_PHY0_SM;
Auke Kok9d5c8242008-01-24 02:22:38 -0800342
Alexander Duyck008c3422009-10-05 06:32:07 +0000343 if (hw->bus.func == E1000_FUNC_1)
344 mask = E1000_SWFW_PHY1_SM;
Nick Nunleyede3ef02010-07-01 13:37:54 +0000345 else if (hw->bus.func == E1000_FUNC_2)
346 mask = E1000_SWFW_PHY2_SM;
347 else if (hw->bus.func == E1000_FUNC_3)
348 mask = E1000_SWFW_PHY3_SM;
Auke Kok9d5c8242008-01-24 02:22:38 -0800349
350 return igb_acquire_swfw_sync_82575(hw, mask);
351}
352
353/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700354 * igb_release_phy_82575 - Release rights to access PHY
Auke Kok9d5c8242008-01-24 02:22:38 -0800355 * @hw: pointer to the HW structure
356 *
357 * A wrapper to release access rights to the correct PHY. This is a
358 * function pointer entry point called by the api module.
359 **/
360static void igb_release_phy_82575(struct e1000_hw *hw)
361{
Alexander Duyck008c3422009-10-05 06:32:07 +0000362 u16 mask = E1000_SWFW_PHY0_SM;
Auke Kok9d5c8242008-01-24 02:22:38 -0800363
Alexander Duyck008c3422009-10-05 06:32:07 +0000364 if (hw->bus.func == E1000_FUNC_1)
365 mask = E1000_SWFW_PHY1_SM;
Nick Nunleyede3ef02010-07-01 13:37:54 +0000366 else if (hw->bus.func == E1000_FUNC_2)
367 mask = E1000_SWFW_PHY2_SM;
368 else if (hw->bus.func == E1000_FUNC_3)
369 mask = E1000_SWFW_PHY3_SM;
Alexander Duyck008c3422009-10-05 06:32:07 +0000370
Auke Kok9d5c8242008-01-24 02:22:38 -0800371 igb_release_swfw_sync_82575(hw, mask);
372}
373
374/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700375 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
Auke Kok9d5c8242008-01-24 02:22:38 -0800376 * @hw: pointer to the HW structure
377 * @offset: register offset to be read
378 * @data: pointer to the read data
379 *
380 * Reads the PHY register at offset using the serial gigabit media independent
381 * interface and stores the retrieved information in data.
382 **/
383static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
384 u16 *data)
385{
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000386 s32 ret_val = -E1000_ERR_PARAM;
Auke Kok9d5c8242008-01-24 02:22:38 -0800387
388 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
Auke Kok652fff32008-06-27 11:00:18 -0700389 hw_dbg("PHY Address %u is out of range\n", offset);
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000390 goto out;
Auke Kok9d5c8242008-01-24 02:22:38 -0800391 }
392
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000393 ret_val = hw->phy.ops.acquire(hw);
394 if (ret_val)
395 goto out;
Auke Kok9d5c8242008-01-24 02:22:38 -0800396
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000397 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800398
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000399 hw->phy.ops.release(hw);
Auke Kok9d5c8242008-01-24 02:22:38 -0800400
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000401out:
402 return ret_val;
Auke Kok9d5c8242008-01-24 02:22:38 -0800403}
404
405/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700406 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
Auke Kok9d5c8242008-01-24 02:22:38 -0800407 * @hw: pointer to the HW structure
408 * @offset: register offset to write to
409 * @data: data to write at register offset
410 *
411 * Writes the data to PHY register at the offset using the serial gigabit
412 * media independent interface.
413 **/
414static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
415 u16 data)
416{
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000417 s32 ret_val = -E1000_ERR_PARAM;
418
Auke Kok9d5c8242008-01-24 02:22:38 -0800419
420 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
Auke Kok652fff32008-06-27 11:00:18 -0700421 hw_dbg("PHY Address %d is out of range\n", offset);
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000422 goto out;
Auke Kok9d5c8242008-01-24 02:22:38 -0800423 }
424
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000425 ret_val = hw->phy.ops.acquire(hw);
426 if (ret_val)
427 goto out;
Auke Kok9d5c8242008-01-24 02:22:38 -0800428
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000429 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800430
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000431 hw->phy.ops.release(hw);
Auke Kok9d5c8242008-01-24 02:22:38 -0800432
Alexander Duyckbf6f7a92009-10-05 06:32:27 +0000433out:
434 return ret_val;
Auke Kok9d5c8242008-01-24 02:22:38 -0800435}
436
437/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700438 * igb_get_phy_id_82575 - Retrieve PHY addr and id
Auke Kok9d5c8242008-01-24 02:22:38 -0800439 * @hw: pointer to the HW structure
440 *
Auke Kok652fff32008-06-27 11:00:18 -0700441 * Retrieves the PHY address and ID for both PHY's which do and do not use
Auke Kok9d5c8242008-01-24 02:22:38 -0800442 * sgmi interface.
443 **/
444static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
445{
446 struct e1000_phy_info *phy = &hw->phy;
447 s32 ret_val = 0;
448 u16 phy_id;
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000449 u32 ctrl_ext;
Nick Nunley4085f742010-07-26 13:15:06 +0000450 u32 mdic;
Auke Kok9d5c8242008-01-24 02:22:38 -0800451
452 /*
453 * For SGMII PHYs, we try the list of possible addresses until
454 * we find one that works. For non-SGMII PHYs
455 * (e.g. integrated copper PHYs), an address of 1 should
456 * work. The result of this function should mean phy->phy_addr
457 * and phy->id are set correctly.
458 */
459 if (!(igb_sgmii_active_82575(hw))) {
460 phy->addr = 1;
461 ret_val = igb_get_phy_id(hw);
462 goto out;
463 }
464
Nick Nunley4085f742010-07-26 13:15:06 +0000465 if (igb_sgmii_uses_mdio_82575(hw)) {
466 switch (hw->mac.type) {
467 case e1000_82575:
468 case e1000_82576:
469 mdic = rd32(E1000_MDIC);
470 mdic &= E1000_MDIC_PHY_MASK;
471 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
472 break;
473 case e1000_82580:
474 case e1000_i350:
475 mdic = rd32(E1000_MDICNFG);
476 mdic &= E1000_MDICNFG_PHY_MASK;
477 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
478 break;
479 default:
480 ret_val = -E1000_ERR_PHY;
481 goto out;
482 break;
483 }
484 ret_val = igb_get_phy_id(hw);
485 goto out;
486 }
487
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000488 /* Power on sgmii phy if it is disabled */
489 ctrl_ext = rd32(E1000_CTRL_EXT);
490 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
491 wrfl();
492 msleep(300);
493
Auke Kok9d5c8242008-01-24 02:22:38 -0800494 /*
495 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
496 * Therefore, we need to test 1-7
497 */
498 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
499 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
500 if (ret_val == 0) {
Auke Kok652fff32008-06-27 11:00:18 -0700501 hw_dbg("Vendor ID 0x%08X read at address %u\n",
502 phy_id, phy->addr);
Auke Kok9d5c8242008-01-24 02:22:38 -0800503 /*
504 * At the time of this writing, The M88 part is
505 * the only supported SGMII PHY product.
506 */
507 if (phy_id == M88_VENDOR)
508 break;
509 } else {
Auke Kok652fff32008-06-27 11:00:18 -0700510 hw_dbg("PHY address %u was unreadable\n", phy->addr);
Auke Kok9d5c8242008-01-24 02:22:38 -0800511 }
512 }
513
514 /* A valid PHY type couldn't be found. */
515 if (phy->addr == 8) {
516 phy->addr = 0;
517 ret_val = -E1000_ERR_PHY;
518 goto out;
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000519 } else {
520 ret_val = igb_get_phy_id(hw);
Auke Kok9d5c8242008-01-24 02:22:38 -0800521 }
522
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000523 /* restore previous sfp cage power state */
524 wr32(E1000_CTRL_EXT, ctrl_ext);
Auke Kok9d5c8242008-01-24 02:22:38 -0800525
526out:
527 return ret_val;
528}
529
530/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700531 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
Auke Kok9d5c8242008-01-24 02:22:38 -0800532 * @hw: pointer to the HW structure
533 *
534 * Resets the PHY using the serial gigabit media independent interface.
535 **/
536static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
537{
538 s32 ret_val;
539
540 /*
541 * This isn't a true "hard" reset, but is the only reset
542 * available to us at this time.
543 */
544
Auke Kok652fff32008-06-27 11:00:18 -0700545 hw_dbg("Soft resetting SGMII attached PHY...\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800546
547 /*
548 * SFP documentation requires the following to configure the SPF module
549 * to work on SGMII. No further documentation is given.
550 */
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000551 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
Auke Kok9d5c8242008-01-24 02:22:38 -0800552 if (ret_val)
553 goto out;
554
555 ret_val = igb_phy_sw_reset(hw);
556
557out:
558 return ret_val;
559}
560
561/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700562 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
Auke Kok9d5c8242008-01-24 02:22:38 -0800563 * @hw: pointer to the HW structure
564 * @active: true to enable LPLU, false to disable
565 *
566 * Sets the LPLU D0 state according to the active flag. When
567 * activating LPLU this function also disables smart speed
568 * and vice versa. LPLU will not be activated unless the
569 * device autonegotiation advertisement meets standards of
570 * either 10 or 10/100 or 10/100/1000 at all duplexes.
571 * This is a function pointer entry point only called by
572 * PHY setup routines.
573 **/
574static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
575{
576 struct e1000_phy_info *phy = &hw->phy;
577 s32 ret_val;
578 u16 data;
579
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000580 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800581 if (ret_val)
582 goto out;
583
584 if (active) {
585 data |= IGP02E1000_PM_D0_LPLU;
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000586 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
Auke Kok652fff32008-06-27 11:00:18 -0700587 data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800588 if (ret_val)
589 goto out;
590
591 /* When LPLU is enabled, we should disable SmartSpeed */
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000592 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
Auke Kok652fff32008-06-27 11:00:18 -0700593 &data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800594 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000595 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
Auke Kok652fff32008-06-27 11:00:18 -0700596 data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800597 if (ret_val)
598 goto out;
599 } else {
600 data &= ~IGP02E1000_PM_D0_LPLU;
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000601 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
Auke Kok652fff32008-06-27 11:00:18 -0700602 data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800603 /*
604 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
605 * during Dx states where the power conservation is most
606 * important. During driver activity we should enable
607 * SmartSpeed, so performance is maintained.
608 */
609 if (phy->smart_speed == e1000_smart_speed_on) {
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000610 ret_val = phy->ops.read_reg(hw,
Auke Kok652fff32008-06-27 11:00:18 -0700611 IGP01E1000_PHY_PORT_CONFIG, &data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800612 if (ret_val)
613 goto out;
614
615 data |= IGP01E1000_PSCFR_SMART_SPEED;
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000616 ret_val = phy->ops.write_reg(hw,
Auke Kok652fff32008-06-27 11:00:18 -0700617 IGP01E1000_PHY_PORT_CONFIG, data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800618 if (ret_val)
619 goto out;
620 } else if (phy->smart_speed == e1000_smart_speed_off) {
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000621 ret_val = phy->ops.read_reg(hw,
Auke Kok652fff32008-06-27 11:00:18 -0700622 IGP01E1000_PHY_PORT_CONFIG, &data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800623 if (ret_val)
624 goto out;
625
626 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000627 ret_val = phy->ops.write_reg(hw,
Auke Kok652fff32008-06-27 11:00:18 -0700628 IGP01E1000_PHY_PORT_CONFIG, data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800629 if (ret_val)
630 goto out;
631 }
632 }
633
634out:
635 return ret_val;
636}
637
638/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700639 * igb_acquire_nvm_82575 - Request for access to EEPROM
Auke Kok9d5c8242008-01-24 02:22:38 -0800640 * @hw: pointer to the HW structure
641 *
Auke Kok652fff32008-06-27 11:00:18 -0700642 * Acquire the necessary semaphores for exclusive access to the EEPROM.
Auke Kok9d5c8242008-01-24 02:22:38 -0800643 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
644 * Return successful if access grant bit set, else clear the request for
645 * EEPROM access and return -E1000_ERR_NVM (-1).
646 **/
647static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
648{
649 s32 ret_val;
650
651 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
652 if (ret_val)
653 goto out;
654
655 ret_val = igb_acquire_nvm(hw);
656
657 if (ret_val)
658 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
659
660out:
661 return ret_val;
662}
663
664/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700665 * igb_release_nvm_82575 - Release exclusive access to EEPROM
Auke Kok9d5c8242008-01-24 02:22:38 -0800666 * @hw: pointer to the HW structure
667 *
668 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
669 * then release the semaphores acquired.
670 **/
671static void igb_release_nvm_82575(struct e1000_hw *hw)
672{
673 igb_release_nvm(hw);
674 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
675}
676
677/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700678 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
Auke Kok9d5c8242008-01-24 02:22:38 -0800679 * @hw: pointer to the HW structure
680 * @mask: specifies which semaphore to acquire
681 *
682 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
683 * will also specify which port we're acquiring the lock for.
684 **/
685static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
686{
687 u32 swfw_sync;
688 u32 swmask = mask;
689 u32 fwmask = mask << 16;
690 s32 ret_val = 0;
691 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
692
693 while (i < timeout) {
694 if (igb_get_hw_semaphore(hw)) {
695 ret_val = -E1000_ERR_SWFW_SYNC;
696 goto out;
697 }
698
699 swfw_sync = rd32(E1000_SW_FW_SYNC);
700 if (!(swfw_sync & (fwmask | swmask)))
701 break;
702
703 /*
704 * Firmware currently using resource (fwmask)
705 * or other software thread using resource (swmask)
706 */
707 igb_put_hw_semaphore(hw);
708 mdelay(5);
709 i++;
710 }
711
712 if (i == timeout) {
Auke Kok652fff32008-06-27 11:00:18 -0700713 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800714 ret_val = -E1000_ERR_SWFW_SYNC;
715 goto out;
716 }
717
718 swfw_sync |= swmask;
719 wr32(E1000_SW_FW_SYNC, swfw_sync);
720
721 igb_put_hw_semaphore(hw);
722
723out:
724 return ret_val;
725}
726
727/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700728 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
Auke Kok9d5c8242008-01-24 02:22:38 -0800729 * @hw: pointer to the HW structure
730 * @mask: specifies which semaphore to acquire
731 *
732 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
733 * will also specify which port we're releasing the lock for.
734 **/
735static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
736{
737 u32 swfw_sync;
738
739 while (igb_get_hw_semaphore(hw) != 0);
740 /* Empty */
741
742 swfw_sync = rd32(E1000_SW_FW_SYNC);
743 swfw_sync &= ~mask;
744 wr32(E1000_SW_FW_SYNC, swfw_sync);
745
746 igb_put_hw_semaphore(hw);
747}
748
749/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700750 * igb_get_cfg_done_82575 - Read config done bit
Auke Kok9d5c8242008-01-24 02:22:38 -0800751 * @hw: pointer to the HW structure
752 *
753 * Read the management control register for the config done bit for
754 * completion status. NOTE: silicon which is EEPROM-less will fail trying
755 * to read the config done bit, so an error is *ONLY* logged and returns
756 * 0. If we were to return with error, EEPROM-less silicon
757 * would not be able to be reset or change link.
758 **/
759static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
760{
761 s32 timeout = PHY_CFG_TIMEOUT;
762 s32 ret_val = 0;
763 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
764
765 if (hw->bus.func == 1)
766 mask = E1000_NVM_CFG_DONE_PORT_1;
Alexander Duyckbb2ac472009-11-19 12:42:01 +0000767 else if (hw->bus.func == E1000_FUNC_2)
768 mask = E1000_NVM_CFG_DONE_PORT_2;
769 else if (hw->bus.func == E1000_FUNC_3)
770 mask = E1000_NVM_CFG_DONE_PORT_3;
Auke Kok9d5c8242008-01-24 02:22:38 -0800771
772 while (timeout) {
773 if (rd32(E1000_EEMNGCTL) & mask)
774 break;
775 msleep(1);
776 timeout--;
777 }
778 if (!timeout)
Auke Kok652fff32008-06-27 11:00:18 -0700779 hw_dbg("MNG configuration cycle has not completed.\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800780
781 /* If EEPROM is not marked present, init the PHY manually */
782 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
783 (hw->phy.type == e1000_phy_igp_3))
784 igb_phy_init_script_igp3(hw);
785
786 return ret_val;
787}
788
789/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700790 * igb_check_for_link_82575 - Check for link
Auke Kok9d5c8242008-01-24 02:22:38 -0800791 * @hw: pointer to the HW structure
792 *
793 * If sgmii is enabled, then use the pcs register to determine link, otherwise
794 * use the generic interface for determining link.
795 **/
796static s32 igb_check_for_link_82575(struct e1000_hw *hw)
797{
798 s32 ret_val;
799 u16 speed, duplex;
800
Alexander Duyck70d92f82009-10-05 06:31:47 +0000801 if (hw->phy.media_type != e1000_media_type_copper) {
Auke Kok9d5c8242008-01-24 02:22:38 -0800802 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
Alexander Duyck2d064c02008-07-08 15:10:12 -0700803 &duplex);
Alexander Duyck5d0932a2009-01-31 00:53:18 -0800804 /*
805 * Use this flag to determine if link needs to be checked or
806 * not. If we have link clear the flag so that we do not
807 * continue to check for link.
808 */
809 hw->mac.get_link_status = !hw->mac.serdes_has_link;
810 } else {
Auke Kok9d5c8242008-01-24 02:22:38 -0800811 ret_val = igb_check_for_copper_link(hw);
Alexander Duyck5d0932a2009-01-31 00:53:18 -0800812 }
Auke Kok9d5c8242008-01-24 02:22:38 -0800813
814 return ret_val;
815}
Alexander Duyck70d92f82009-10-05 06:31:47 +0000816
Auke Kok9d5c8242008-01-24 02:22:38 -0800817/**
Nick Nunley88a268c2010-02-17 01:01:59 +0000818 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
819 * @hw: pointer to the HW structure
820 **/
821void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
822{
823 u32 reg;
824
825
826 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
827 !igb_sgmii_active_82575(hw))
828 return;
829
830 /* Enable PCS to turn on link */
831 reg = rd32(E1000_PCS_CFG0);
832 reg |= E1000_PCS_CFG_PCS_EN;
833 wr32(E1000_PCS_CFG0, reg);
834
835 /* Power up the laser */
836 reg = rd32(E1000_CTRL_EXT);
837 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
838 wr32(E1000_CTRL_EXT, reg);
839
840 /* flush the write to verify completion */
841 wrfl();
842 msleep(1);
843}
844
845/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700846 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
Auke Kok9d5c8242008-01-24 02:22:38 -0800847 * @hw: pointer to the HW structure
848 * @speed: stores the current speed
849 * @duplex: stores the current duplex
850 *
Auke Kok652fff32008-06-27 11:00:18 -0700851 * Using the physical coding sub-layer (PCS), retrieve the current speed and
Auke Kok9d5c8242008-01-24 02:22:38 -0800852 * duplex, then store the values in the pointers provided.
853 **/
854static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
855 u16 *duplex)
856{
857 struct e1000_mac_info *mac = &hw->mac;
858 u32 pcs;
859
860 /* Set up defaults for the return values of this function */
861 mac->serdes_has_link = false;
862 *speed = 0;
863 *duplex = 0;
864
865 /*
866 * Read the PCS Status register for link state. For non-copper mode,
867 * the status register is not accurate. The PCS status register is
868 * used instead.
869 */
870 pcs = rd32(E1000_PCS_LSTAT);
871
872 /*
873 * The link up bit determines when link is up on autoneg. The sync ok
874 * gets set once both sides sync up and agree upon link. Stable link
875 * can be determined by checking for both link up and link sync ok
876 */
877 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
878 mac->serdes_has_link = true;
879
880 /* Detect and store PCS speed */
881 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
882 *speed = SPEED_1000;
883 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
884 *speed = SPEED_100;
885 } else {
886 *speed = SPEED_10;
887 }
888
889 /* Detect and store PCS duplex */
890 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
891 *duplex = FULL_DUPLEX;
892 } else {
893 *duplex = HALF_DUPLEX;
894 }
895 }
896
897 return 0;
898}
899
900/**
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000901 * igb_shutdown_serdes_link_82575 - Remove link during power down
Alexander Duyck2d064c02008-07-08 15:10:12 -0700902 * @hw: pointer to the HW structure
903 *
904 * In the case of fiber serdes, shut down optics and PCS on driver unload
905 * when management pass thru is not enabled.
906 **/
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000907void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
Alexander Duyck2d064c02008-07-08 15:10:12 -0700908{
909 u32 reg;
910
Nick Nunley53c992f2010-02-17 01:01:40 +0000911 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000912 igb_sgmii_active_82575(hw))
Alexander Duyck2d064c02008-07-08 15:10:12 -0700913 return;
914
Nick Nunley53c992f2010-02-17 01:01:40 +0000915 if (!igb_enable_mng_pass_thru(hw)) {
Alexander Duyck2d064c02008-07-08 15:10:12 -0700916 /* Disable PCS to turn off link */
917 reg = rd32(E1000_PCS_CFG0);
918 reg &= ~E1000_PCS_CFG_PCS_EN;
919 wr32(E1000_PCS_CFG0, reg);
920
921 /* shutdown the laser */
922 reg = rd32(E1000_CTRL_EXT);
Alexander Duyck2fb02a22009-09-14 08:22:54 +0000923 reg |= E1000_CTRL_EXT_SDP3_DATA;
Alexander Duyck2d064c02008-07-08 15:10:12 -0700924 wr32(E1000_CTRL_EXT, reg);
925
926 /* flush the write to verify completion */
927 wrfl();
928 msleep(1);
929 }
Auke Kok9d5c8242008-01-24 02:22:38 -0800930}
931
932/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700933 * igb_reset_hw_82575 - Reset hardware
Auke Kok9d5c8242008-01-24 02:22:38 -0800934 * @hw: pointer to the HW structure
935 *
936 * This resets the hardware into a known state. This is a
937 * function pointer entry point called by the api module.
938 **/
939static s32 igb_reset_hw_82575(struct e1000_hw *hw)
940{
941 u32 ctrl, icr;
942 s32 ret_val;
943
944 /*
945 * Prevent the PCI-E bus from sticking if there is no TLP connection
946 * on the last TLP read/write transaction when MAC is reset.
947 */
948 ret_val = igb_disable_pcie_master(hw);
949 if (ret_val)
Auke Kok652fff32008-06-27 11:00:18 -0700950 hw_dbg("PCI-E Master disable polling has failed.\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800951
Alexander Duyck009bc062009-07-23 18:08:35 +0000952 /* set the completion timeout for interface */
953 ret_val = igb_set_pcie_completion_timeout(hw);
954 if (ret_val) {
955 hw_dbg("PCI-E Set completion timeout has failed.\n");
956 }
957
Auke Kok652fff32008-06-27 11:00:18 -0700958 hw_dbg("Masking off all interrupts\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800959 wr32(E1000_IMC, 0xffffffff);
960
961 wr32(E1000_RCTL, 0);
962 wr32(E1000_TCTL, E1000_TCTL_PSP);
963 wrfl();
964
965 msleep(10);
966
967 ctrl = rd32(E1000_CTRL);
968
Auke Kok652fff32008-06-27 11:00:18 -0700969 hw_dbg("Issuing a global reset to MAC\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800970 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
971
972 ret_val = igb_get_auto_rd_done(hw);
973 if (ret_val) {
974 /*
975 * When auto config read does not complete, do not
976 * return with an error. This can happen in situations
977 * where there is no eeprom and prevents getting link.
978 */
Auke Kok652fff32008-06-27 11:00:18 -0700979 hw_dbg("Auto Read Done did not complete\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800980 }
981
982 /* If EEPROM is not present, run manual init scripts */
983 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
984 igb_reset_init_script_82575(hw);
985
986 /* Clear any pending interrupt events. */
987 wr32(E1000_IMC, 0xffffffff);
988 icr = rd32(E1000_ICR);
989
Alexander Duyck5ac16652009-07-23 18:09:12 +0000990 /* Install any alternate MAC address into RAR0 */
991 ret_val = igb_check_alt_mac_addr(hw);
Auke Kok9d5c8242008-01-24 02:22:38 -0800992
993 return ret_val;
994}
995
996/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700997 * igb_init_hw_82575 - Initialize hardware
Auke Kok9d5c8242008-01-24 02:22:38 -0800998 * @hw: pointer to the HW structure
999 *
1000 * This inits the hardware readying it for operation.
1001 **/
1002static s32 igb_init_hw_82575(struct e1000_hw *hw)
1003{
1004 struct e1000_mac_info *mac = &hw->mac;
1005 s32 ret_val;
1006 u16 i, rar_count = mac->rar_entry_count;
1007
1008 /* Initialize identification LED */
1009 ret_val = igb_id_led_init(hw);
1010 if (ret_val) {
Auke Kok652fff32008-06-27 11:00:18 -07001011 hw_dbg("Error initializing identification LED\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001012 /* This is not fatal and we should not stop init due to this */
1013 }
1014
1015 /* Disabling VLAN filtering */
Auke Kok652fff32008-06-27 11:00:18 -07001016 hw_dbg("Initializing the IEEE VLAN\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001017 igb_clear_vfta(hw);
1018
1019 /* Setup the receive address */
Alexander Duyck5ac16652009-07-23 18:09:12 +00001020 igb_init_rx_addrs(hw, rar_count);
1021
Auke Kok9d5c8242008-01-24 02:22:38 -08001022 /* Zero out the Multicast HASH table */
Auke Kok652fff32008-06-27 11:00:18 -07001023 hw_dbg("Zeroing the MTA\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001024 for (i = 0; i < mac->mta_reg_count; i++)
1025 array_wr32(E1000_MTA, i, 0);
1026
Alexander Duyck68d480c42009-10-05 06:33:08 +00001027 /* Zero out the Unicast HASH table */
1028 hw_dbg("Zeroing the UTA\n");
1029 for (i = 0; i < mac->uta_reg_count; i++)
1030 array_wr32(E1000_UTA, i, 0);
1031
Auke Kok9d5c8242008-01-24 02:22:38 -08001032 /* Setup link and flow control */
1033 ret_val = igb_setup_link(hw);
1034
1035 /*
1036 * Clear all of the statistics registers (clear on read). It is
1037 * important that we do this after we have tried to establish link
1038 * because the symbol error count will increment wildly if there
1039 * is no link.
1040 */
1041 igb_clear_hw_cntrs_82575(hw);
1042
1043 return ret_val;
1044}
1045
1046/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001047 * igb_setup_copper_link_82575 - Configure copper link settings
Auke Kok9d5c8242008-01-24 02:22:38 -08001048 * @hw: pointer to the HW structure
1049 *
1050 * Configures the link for auto-neg or forced speed and duplex. Then we check
1051 * for link, once link is established calls to configure collision distance
1052 * and flow control are called.
1053 **/
1054static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1055{
Alexander Duyck12645a12009-07-23 18:08:16 +00001056 u32 ctrl;
Auke Kok9d5c8242008-01-24 02:22:38 -08001057 s32 ret_val;
Auke Kok9d5c8242008-01-24 02:22:38 -08001058
1059 ctrl = rd32(E1000_CTRL);
1060 ctrl |= E1000_CTRL_SLU;
1061 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1062 wr32(E1000_CTRL, ctrl);
1063
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001064 ret_val = igb_setup_serdes_link_82575(hw);
1065 if (ret_val)
1066 goto out;
1067
1068 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001069 /* allow time for SFP cage time to power up phy */
1070 msleep(300);
1071
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001072 ret_val = hw->phy.ops.reset(hw);
1073 if (ret_val) {
1074 hw_dbg("Error resetting the PHY.\n");
1075 goto out;
1076 }
1077 }
Auke Kok9d5c8242008-01-24 02:22:38 -08001078 switch (hw->phy.type) {
1079 case e1000_phy_m88:
Joseph Gasparakis308fb392010-09-22 17:56:44 +00001080 if (hw->phy.id == I347AT4_E_PHY_ID ||
1081 hw->phy.id == M88E1112_E_PHY_ID)
1082 ret_val = igb_copper_link_setup_m88_gen2(hw);
1083 else
1084 ret_val = igb_copper_link_setup_m88(hw);
Auke Kok9d5c8242008-01-24 02:22:38 -08001085 break;
1086 case e1000_phy_igp_3:
1087 ret_val = igb_copper_link_setup_igp(hw);
Auke Kok9d5c8242008-01-24 02:22:38 -08001088 break;
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001089 case e1000_phy_82580:
1090 ret_val = igb_copper_link_setup_82580(hw);
1091 break;
Auke Kok9d5c8242008-01-24 02:22:38 -08001092 default:
1093 ret_val = -E1000_ERR_PHY;
1094 break;
1095 }
1096
1097 if (ret_val)
1098 goto out;
1099
Alexander Duyck81fadd82009-10-05 06:35:03 +00001100 ret_val = igb_setup_copper_link(hw);
Auke Kok9d5c8242008-01-24 02:22:38 -08001101out:
1102 return ret_val;
1103}
1104
1105/**
Alexander Duyck70d92f82009-10-05 06:31:47 +00001106 * igb_setup_serdes_link_82575 - Setup link for serdes
Auke Kok9d5c8242008-01-24 02:22:38 -08001107 * @hw: pointer to the HW structure
1108 *
Alexander Duyck70d92f82009-10-05 06:31:47 +00001109 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1110 * used on copper connections where the serialized gigabit media independent
1111 * interface (sgmii), or serdes fiber is being used. Configures the link
1112 * for auto-negotiation or forces speed/duplex.
Auke Kok9d5c8242008-01-24 02:22:38 -08001113 **/
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001114static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
Auke Kok9d5c8242008-01-24 02:22:38 -08001115{
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001116 u32 ctrl_ext, ctrl_reg, reg;
1117 bool pcs_autoneg;
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001118
1119 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1120 !igb_sgmii_active_82575(hw))
1121 return 0;
Auke Kok9d5c8242008-01-24 02:22:38 -08001122
1123 /*
1124 * On the 82575, SerDes loopback mode persists until it is
1125 * explicitly turned off or a power cycle is performed. A read to
1126 * the register does not indicate its status. Therefore, we ensure
1127 * loopback mode is disabled during initialization.
1128 */
1129 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1130
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001131 /* power on the sfp cage if present */
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001132 ctrl_ext = rd32(E1000_CTRL_EXT);
1133 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1134 wr32(E1000_CTRL_EXT, ctrl_ext);
Auke Kok9d5c8242008-01-24 02:22:38 -08001135
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001136 ctrl_reg = rd32(E1000_CTRL);
1137 ctrl_reg |= E1000_CTRL_SLU;
1138
1139 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1140 /* set both sw defined pins */
1141 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1142
1143 /* Set switch control to serdes energy detect */
1144 reg = rd32(E1000_CONNSW);
1145 reg |= E1000_CONNSW_ENRGSRC;
1146 wr32(E1000_CONNSW, reg);
Alexander Duyck921aa742009-01-21 14:42:28 -08001147 }
1148
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001149 reg = rd32(E1000_PCS_LCTL);
1150
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001151 /* default pcs_autoneg to the same setting as mac autoneg */
1152 pcs_autoneg = hw->mac.autoneg;
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001153
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001154 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1155 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1156 /* sgmii mode lets the phy handle forcing speed/duplex */
1157 pcs_autoneg = true;
1158 /* autoneg time out should be disabled for SGMII mode */
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001159 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001160 break;
1161 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1162 /* disable PCS autoneg and support parallel detect only */
1163 pcs_autoneg = false;
1164 default:
1165 /*
1166 * non-SGMII modes only supports a speed of 1000/Full for the
1167 * link so it is best to just force the MAC and let the pcs
1168 * link either autoneg or be forced to 1000/Full
1169 */
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001170 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1171 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001172
1173 /* set speed of 1000/Full if speed/duplex is forced */
1174 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1175 break;
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001176 }
1177
1178 wr32(E1000_CTRL, ctrl_reg);
Auke Kok9d5c8242008-01-24 02:22:38 -08001179
1180 /*
1181 * New SerDes mode allows for forcing speed or autonegotiating speed
1182 * at 1gb. Autoneg should be default set by most drivers. This is the
1183 * mode that will be compatible with older link partners and switches.
1184 * However, both are supported by the hardware and some drivers/tools.
1185 */
Auke Kok9d5c8242008-01-24 02:22:38 -08001186 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1187 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1188
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001189 /*
1190 * We force flow control to prevent the CTRL register values from being
1191 * overwritten by the autonegotiated flow control values
1192 */
1193 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1194
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001195 if (pcs_autoneg) {
Auke Kok9d5c8242008-01-24 02:22:38 -08001196 /* Set PCS register for autoneg */
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001197 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
Alexander Duyck70d92f82009-10-05 06:31:47 +00001198 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001199 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
Auke Kok9d5c8242008-01-24 02:22:38 -08001200 } else {
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001201 /* Set PCS register for forced link */
Alexander Duyckd68caec2009-12-23 13:20:47 +00001202 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
Alexander Duyck70d92f82009-10-05 06:31:47 +00001203
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001204 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
Auke Kok9d5c8242008-01-24 02:22:38 -08001205 }
Alexander Duyck726c09e2008-08-04 14:59:56 -07001206
Auke Kok9d5c8242008-01-24 02:22:38 -08001207 wr32(E1000_PCS_LCTL, reg);
1208
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001209 if (!igb_sgmii_active_82575(hw))
1210 igb_force_mac_fc(hw);
1211
Auke Kok9d5c8242008-01-24 02:22:38 -08001212 return 0;
1213}
1214
1215/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001216 * igb_sgmii_active_82575 - Return sgmii state
Auke Kok9d5c8242008-01-24 02:22:38 -08001217 * @hw: pointer to the HW structure
1218 *
1219 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1220 * which can be enabled for use in the embedded applications. Simply
1221 * return the current state of the sgmii interface.
1222 **/
1223static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1224{
Alexander Duyckc1889bf2009-02-06 23:16:45 +00001225 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
Alexander Duyckc1889bf2009-02-06 23:16:45 +00001226 return dev_spec->sgmii_active;
Auke Kok9d5c8242008-01-24 02:22:38 -08001227}
1228
1229/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001230 * igb_reset_init_script_82575 - Inits HW defaults after reset
Auke Kok9d5c8242008-01-24 02:22:38 -08001231 * @hw: pointer to the HW structure
1232 *
1233 * Inits recommended HW defaults after a reset when there is no EEPROM
1234 * detected. This is only for the 82575.
1235 **/
1236static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1237{
1238 if (hw->mac.type == e1000_82575) {
Auke Kok652fff32008-06-27 11:00:18 -07001239 hw_dbg("Running reset init script for 82575\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001240 /* SerDes configuration via SERDESCTRL */
1241 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1242 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1243 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1244 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1245
1246 /* CCM configuration via CCMCTL register */
1247 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1248 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1249
1250 /* PCIe lanes configuration */
1251 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1252 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1253 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1254 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1255
1256 /* PCIe PLL Configuration */
1257 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1258 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1259 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1260 }
1261
1262 return 0;
1263}
1264
1265/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001266 * igb_read_mac_addr_82575 - Read device MAC address
Auke Kok9d5c8242008-01-24 02:22:38 -08001267 * @hw: pointer to the HW structure
1268 **/
1269static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1270{
1271 s32 ret_val = 0;
1272
Alexander Duyck22896632009-10-05 06:34:25 +00001273 /*
1274 * If there's an alternate MAC address place it in RAR0
1275 * so that it will override the Si installed default perm
1276 * address.
1277 */
1278 ret_val = igb_check_alt_mac_addr(hw);
1279 if (ret_val)
1280 goto out;
Auke Kok9d5c8242008-01-24 02:22:38 -08001281
Alexander Duyck22896632009-10-05 06:34:25 +00001282 ret_val = igb_read_mac_addr(hw);
1283
1284out:
Auke Kok9d5c8242008-01-24 02:22:38 -08001285 return ret_val;
1286}
1287
1288/**
Nick Nunley88a268c2010-02-17 01:01:59 +00001289 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1290 * @hw: pointer to the HW structure
1291 *
1292 * In the case of a PHY power down to save power, or to turn off link during a
1293 * driver unload, or wake on lan is not enabled, remove the link.
1294 **/
1295void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1296{
1297 /* If the management interface is not enabled, then power down */
1298 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1299 igb_power_down_phy_copper(hw);
Nick Nunley88a268c2010-02-17 01:01:59 +00001300}
1301
1302/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001303 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
Auke Kok9d5c8242008-01-24 02:22:38 -08001304 * @hw: pointer to the HW structure
1305 *
1306 * Clears the hardware counters by reading the counter registers.
1307 **/
1308static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1309{
Auke Kok9d5c8242008-01-24 02:22:38 -08001310 igb_clear_hw_cntrs_base(hw);
1311
Alexander Duyckcc9073b2009-10-05 06:31:25 +00001312 rd32(E1000_PRC64);
1313 rd32(E1000_PRC127);
1314 rd32(E1000_PRC255);
1315 rd32(E1000_PRC511);
1316 rd32(E1000_PRC1023);
1317 rd32(E1000_PRC1522);
1318 rd32(E1000_PTC64);
1319 rd32(E1000_PTC127);
1320 rd32(E1000_PTC255);
1321 rd32(E1000_PTC511);
1322 rd32(E1000_PTC1023);
1323 rd32(E1000_PTC1522);
Auke Kok9d5c8242008-01-24 02:22:38 -08001324
Alexander Duyckcc9073b2009-10-05 06:31:25 +00001325 rd32(E1000_ALGNERRC);
1326 rd32(E1000_RXERRC);
1327 rd32(E1000_TNCRS);
1328 rd32(E1000_CEXTERR);
1329 rd32(E1000_TSCTC);
1330 rd32(E1000_TSCTFC);
Auke Kok9d5c8242008-01-24 02:22:38 -08001331
Alexander Duyckcc9073b2009-10-05 06:31:25 +00001332 rd32(E1000_MGTPRC);
1333 rd32(E1000_MGTPDC);
1334 rd32(E1000_MGTPTC);
Auke Kok9d5c8242008-01-24 02:22:38 -08001335
Alexander Duyckcc9073b2009-10-05 06:31:25 +00001336 rd32(E1000_IAC);
1337 rd32(E1000_ICRXOC);
Auke Kok9d5c8242008-01-24 02:22:38 -08001338
Alexander Duyckcc9073b2009-10-05 06:31:25 +00001339 rd32(E1000_ICRXPTC);
1340 rd32(E1000_ICRXATC);
1341 rd32(E1000_ICTXPTC);
1342 rd32(E1000_ICTXATC);
1343 rd32(E1000_ICTXQEC);
1344 rd32(E1000_ICTXQMTC);
1345 rd32(E1000_ICRXDMTC);
Auke Kok9d5c8242008-01-24 02:22:38 -08001346
Alexander Duyckcc9073b2009-10-05 06:31:25 +00001347 rd32(E1000_CBTMPC);
1348 rd32(E1000_HTDPMC);
1349 rd32(E1000_CBRMPC);
1350 rd32(E1000_RPTHC);
1351 rd32(E1000_HGPTC);
1352 rd32(E1000_HTCBDPC);
1353 rd32(E1000_HGORCL);
1354 rd32(E1000_HGORCH);
1355 rd32(E1000_HGOTCL);
1356 rd32(E1000_HGOTCH);
1357 rd32(E1000_LENERRS);
Auke Kok9d5c8242008-01-24 02:22:38 -08001358
1359 /* This register should not be read in copper configurations */
Alexander Duyck2fb02a22009-09-14 08:22:54 +00001360 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1361 igb_sgmii_active_82575(hw))
Alexander Duyckcc9073b2009-10-05 06:31:25 +00001362 rd32(E1000_SCVPC);
Auke Kok9d5c8242008-01-24 02:22:38 -08001363}
1364
Alexander Duyck662d7202008-06-27 11:00:29 -07001365/**
1366 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1367 * @hw: pointer to the HW structure
1368 *
1369 * After rx enable if managability is enabled then there is likely some
1370 * bad data at the start of the fifo and possibly in the DMA fifo. This
1371 * function clears the fifos and flushes any packets that came in as rx was
1372 * being enabled.
1373 **/
1374void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1375{
1376 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1377 int i, ms_wait;
1378
1379 if (hw->mac.type != e1000_82575 ||
1380 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1381 return;
1382
1383 /* Disable all RX queues */
1384 for (i = 0; i < 4; i++) {
1385 rxdctl[i] = rd32(E1000_RXDCTL(i));
1386 wr32(E1000_RXDCTL(i),
1387 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1388 }
1389 /* Poll all queues to verify they have shut down */
1390 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1391 msleep(1);
1392 rx_enabled = 0;
1393 for (i = 0; i < 4; i++)
1394 rx_enabled |= rd32(E1000_RXDCTL(i));
1395 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1396 break;
1397 }
1398
1399 if (ms_wait == 10)
1400 hw_dbg("Queue disable timed out after 10ms\n");
1401
1402 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1403 * incoming packets are rejected. Set enable and wait 2ms so that
1404 * any packet that was coming in as RCTL.EN was set is flushed
1405 */
1406 rfctl = rd32(E1000_RFCTL);
1407 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1408
1409 rlpml = rd32(E1000_RLPML);
1410 wr32(E1000_RLPML, 0);
1411
1412 rctl = rd32(E1000_RCTL);
1413 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1414 temp_rctl |= E1000_RCTL_LPE;
1415
1416 wr32(E1000_RCTL, temp_rctl);
1417 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1418 wrfl();
1419 msleep(2);
1420
1421 /* Enable RX queues that were previously enabled and restore our
1422 * previous state
1423 */
1424 for (i = 0; i < 4; i++)
1425 wr32(E1000_RXDCTL(i), rxdctl[i]);
1426 wr32(E1000_RCTL, rctl);
1427 wrfl();
1428
1429 wr32(E1000_RLPML, rlpml);
1430 wr32(E1000_RFCTL, rfctl);
1431
1432 /* Flush receive errors generated by workaround */
1433 rd32(E1000_ROC);
1434 rd32(E1000_RNBC);
1435 rd32(E1000_MPC);
1436}
1437
Alexander Duyck4ae196d2009-02-19 20:40:07 -08001438/**
Alexander Duyck009bc062009-07-23 18:08:35 +00001439 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1440 * @hw: pointer to the HW structure
1441 *
1442 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1443 * however the hardware default for these parts is 500us to 1ms which is less
1444 * than the 10ms recommended by the pci-e spec. To address this we need to
1445 * increase the value to either 10ms to 200ms for capability version 1 config,
1446 * or 16ms to 55ms for version 2.
1447 **/
1448static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1449{
1450 u32 gcr = rd32(E1000_GCR);
1451 s32 ret_val = 0;
1452 u16 pcie_devctl2;
1453
1454 /* only take action if timeout value is defaulted to 0 */
1455 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1456 goto out;
1457
1458 /*
1459 * if capababilities version is type 1 we can write the
1460 * timeout of 10ms to 200ms through the GCR register
1461 */
1462 if (!(gcr & E1000_GCR_CAP_VER2)) {
1463 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1464 goto out;
1465 }
1466
1467 /*
1468 * for version 2 capabilities we need to write the config space
1469 * directly in order to set the completion timeout value for
1470 * 16ms to 55ms
1471 */
1472 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1473 &pcie_devctl2);
1474 if (ret_val)
1475 goto out;
1476
1477 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1478
1479 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1480 &pcie_devctl2);
1481out:
1482 /* disable completion timeout resend */
1483 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1484
1485 wr32(E1000_GCR, gcr);
1486 return ret_val;
1487}
1488
1489/**
Greg Rose13800462010-11-06 02:08:26 +00001490 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1491 * @hw: pointer to the hardware struct
1492 * @enable: state to enter, either enabled or disabled
1493 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1494 *
1495 * enables/disables L2 switch anti-spoofing functionality.
1496 **/
1497void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1498{
1499 u32 dtxswc;
1500
1501 switch (hw->mac.type) {
1502 case e1000_82576:
1503 case e1000_i350:
1504 dtxswc = rd32(E1000_DTXSWC);
1505 if (enable) {
1506 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1507 E1000_DTXSWC_VLAN_SPOOF_MASK);
1508 /* The PF can spoof - it has to in order to
1509 * support emulation mode NICs */
1510 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1511 } else {
1512 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1513 E1000_DTXSWC_VLAN_SPOOF_MASK);
1514 }
1515 wr32(E1000_DTXSWC, dtxswc);
1516 break;
1517 default:
1518 break;
1519 }
1520}
1521
1522/**
Alexander Duyck4ae196d2009-02-19 20:40:07 -08001523 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1524 * @hw: pointer to the hardware struct
1525 * @enable: state to enter, either enabled or disabled
1526 *
1527 * enables/disables L2 switch loopback functionality.
1528 **/
1529void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1530{
1531 u32 dtxswc = rd32(E1000_DTXSWC);
1532
1533 if (enable)
1534 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1535 else
1536 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1537
1538 wr32(E1000_DTXSWC, dtxswc);
1539}
1540
1541/**
1542 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1543 * @hw: pointer to the hardware struct
1544 * @enable: state to enter, either enabled or disabled
1545 *
1546 * enables/disables replication of packets across multiple pools.
1547 **/
1548void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1549{
1550 u32 vt_ctl = rd32(E1000_VT_CTL);
1551
1552 if (enable)
1553 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1554 else
1555 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1556
1557 wr32(E1000_VT_CTL, vt_ctl);
1558}
1559
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001560/**
1561 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1562 * @hw: pointer to the HW structure
1563 * @offset: register offset to be read
1564 * @data: pointer to the read data
1565 *
1566 * Reads the MDI control register in the PHY at offset and stores the
1567 * information read to data.
1568 **/
1569static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1570{
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001571 s32 ret_val;
1572
1573
1574 ret_val = hw->phy.ops.acquire(hw);
1575 if (ret_val)
1576 goto out;
1577
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001578 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1579
1580 hw->phy.ops.release(hw);
1581
1582out:
1583 return ret_val;
1584}
1585
1586/**
1587 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1588 * @hw: pointer to the HW structure
1589 * @offset: register offset to write to
1590 * @data: data to write to register at offset
1591 *
1592 * Writes data to MDI control register in the PHY at offset.
1593 **/
1594static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1595{
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001596 s32 ret_val;
1597
1598
1599 ret_val = hw->phy.ops.acquire(hw);
1600 if (ret_val)
1601 goto out;
1602
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001603 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1604
1605 hw->phy.ops.release(hw);
1606
1607out:
1608 return ret_val;
1609}
1610
1611/**
Nick Nunley08451e22010-07-26 13:15:29 +00001612 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1613 * @hw: pointer to the HW structure
1614 *
1615 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1616 * the values found in the EEPROM. This addresses an issue in which these
1617 * bits are not restored from EEPROM after reset.
1618 **/
1619static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1620{
1621 s32 ret_val = 0;
1622 u32 mdicnfg;
Gasparakis, Joseph1b5dda32010-12-09 01:41:01 +00001623 u16 nvm_data = 0;
Nick Nunley08451e22010-07-26 13:15:29 +00001624
1625 if (hw->mac.type != e1000_82580)
1626 goto out;
1627 if (!igb_sgmii_active_82575(hw))
1628 goto out;
1629
1630 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1631 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1632 &nvm_data);
1633 if (ret_val) {
1634 hw_dbg("NVM Read Error\n");
1635 goto out;
1636 }
1637
1638 mdicnfg = rd32(E1000_MDICNFG);
1639 if (nvm_data & NVM_WORD24_EXT_MDIO)
1640 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1641 if (nvm_data & NVM_WORD24_COM_MDIO)
1642 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1643 wr32(E1000_MDICNFG, mdicnfg);
1644out:
1645 return ret_val;
1646}
1647
1648/**
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001649 * igb_reset_hw_82580 - Reset hardware
1650 * @hw: pointer to the HW structure
1651 *
1652 * This resets function or entire device (all ports, etc.)
1653 * to a known state.
1654 **/
1655static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1656{
1657 s32 ret_val = 0;
1658 /* BH SW mailbox bit in SW_FW_SYNC */
1659 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1660 u32 ctrl, icr;
1661 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1662
1663
1664 hw->dev_spec._82575.global_device_reset = false;
1665
1666 /* Get current control state. */
1667 ctrl = rd32(E1000_CTRL);
1668
1669 /*
1670 * Prevent the PCI-E bus from sticking if there is no TLP connection
1671 * on the last TLP read/write transaction when MAC is reset.
1672 */
1673 ret_val = igb_disable_pcie_master(hw);
1674 if (ret_val)
1675 hw_dbg("PCI-E Master disable polling has failed.\n");
1676
1677 hw_dbg("Masking off all interrupts\n");
1678 wr32(E1000_IMC, 0xffffffff);
1679 wr32(E1000_RCTL, 0);
1680 wr32(E1000_TCTL, E1000_TCTL_PSP);
1681 wrfl();
1682
1683 msleep(10);
1684
1685 /* Determine whether or not a global dev reset is requested */
1686 if (global_device_reset &&
1687 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1688 global_device_reset = false;
1689
1690 if (global_device_reset &&
1691 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1692 ctrl |= E1000_CTRL_DEV_RST;
1693 else
1694 ctrl |= E1000_CTRL_RST;
1695
1696 wr32(E1000_CTRL, ctrl);
1697
1698 /* Add delay to insure DEV_RST has time to complete */
1699 if (global_device_reset)
1700 msleep(5);
1701
1702 ret_val = igb_get_auto_rd_done(hw);
1703 if (ret_val) {
1704 /*
1705 * When auto config read does not complete, do not
1706 * return with an error. This can happen in situations
1707 * where there is no eeprom and prevents getting link.
1708 */
1709 hw_dbg("Auto Read Done did not complete\n");
1710 }
1711
1712 /* If EEPROM is not present, run manual init scripts */
1713 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1714 igb_reset_init_script_82575(hw);
1715
1716 /* clear global device reset status bit */
1717 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1718
1719 /* Clear any pending interrupt events. */
1720 wr32(E1000_IMC, 0xffffffff);
1721 icr = rd32(E1000_ICR);
1722
Nick Nunley08451e22010-07-26 13:15:29 +00001723 ret_val = igb_reset_mdicnfg_82580(hw);
1724 if (ret_val)
1725 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
1726
Alexander Duyckbb2ac472009-11-19 12:42:01 +00001727 /* Install any alternate MAC address into RAR0 */
1728 ret_val = igb_check_alt_mac_addr(hw);
1729
1730 /* Release semaphore */
1731 if (global_device_reset)
1732 igb_release_swfw_sync_82575(hw, swmbsw_mask);
1733
1734 return ret_val;
1735}
1736
1737/**
1738 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1739 * @data: data received by reading RXPBS register
1740 *
1741 * The 82580 uses a table based approach for packet buffer allocation sizes.
1742 * This function converts the retrieved value into the correct table value
1743 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1744 * 0x0 36 72 144 1 2 4 8 16
1745 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1746 */
1747u16 igb_rxpbs_adjust_82580(u32 data)
1748{
1749 u16 ret_val = 0;
1750
1751 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1752 ret_val = e1000_82580_rxpbs_table[data];
1753
1754 return ret_val;
1755}
1756
Auke Kok9d5c8242008-01-24 02:22:38 -08001757static struct e1000_mac_operations e1000_mac_ops_82575 = {
Auke Kok9d5c8242008-01-24 02:22:38 -08001758 .init_hw = igb_init_hw_82575,
1759 .check_for_link = igb_check_for_link_82575,
Alexander Duyck2d064c02008-07-08 15:10:12 -07001760 .rar_set = igb_rar_set,
Auke Kok9d5c8242008-01-24 02:22:38 -08001761 .read_mac_addr = igb_read_mac_addr_82575,
1762 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1763};
1764
1765static struct e1000_phy_operations e1000_phy_ops_82575 = {
Alexander Duycka8d2a0c2009-02-06 23:17:26 +00001766 .acquire = igb_acquire_phy_82575,
Auke Kok9d5c8242008-01-24 02:22:38 -08001767 .get_cfg_done = igb_get_cfg_done_82575,
Alexander Duycka8d2a0c2009-02-06 23:17:26 +00001768 .release = igb_release_phy_82575,
Auke Kok9d5c8242008-01-24 02:22:38 -08001769};
1770
1771static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
Alexander Duyck312c75a2009-02-06 23:17:47 +00001772 .acquire = igb_acquire_nvm_82575,
1773 .read = igb_read_nvm_eerd,
1774 .release = igb_release_nvm_82575,
1775 .write = igb_write_nvm_spi,
Auke Kok9d5c8242008-01-24 02:22:38 -08001776};
1777
1778const struct e1000_info e1000_82575_info = {
1779 .get_invariants = igb_get_invariants_82575,
1780 .mac_ops = &e1000_mac_ops_82575,
1781 .phy_ops = &e1000_phy_ops_82575,
1782 .nvm_ops = &e1000_nvm_ops_82575,
1783};
1784