blob: 767d1eb87c9477538c661e1742af66f6f30d1ca3 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
Ayaz Abdulla87046e52006-12-19 23:33:32 -05006 * and Andrew de Quincey.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
Manfred Spraul18360982005-12-24 14:19:24 +010012 * Copyright (C) 2003,4,5 Manfred Spraul
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
Ayaz Abdullaf1405d322009-01-09 11:03:54 +000016 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
Ayaz Abdulla3e1a3ce2009-03-05 08:02:38 +000042#define FORCEDETH_VERSION "0.64"
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#define DRV_NAME "forcedeth"
44
45#include <linux/module.h>
46#include <linux/types.h>
47#include <linux/pci.h>
48#include <linux/interrupt.h>
49#include <linux/netdevice.h>
50#include <linux/etherdevice.h>
51#include <linux/delay.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040052#include <linux/sched.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#include <linux/spinlock.h>
54#include <linux/ethtool.h>
55#include <linux/timer.h>
56#include <linux/skbuff.h>
57#include <linux/mii.h>
58#include <linux/random.h>
59#include <linux/init.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +020060#include <linux/if_vlan.h>
Matthias Gehre910638a2006-03-28 01:56:48 -080061#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090062#include <linux/slab.h>
Szymon Janc5504e132010-11-27 08:39:45 +000063#include <linux/uaccess.h>
64#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
66#include <asm/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070067#include <asm/system.h>
68
69#if 0
70#define dprintk printk
71#else
72#define dprintk(x...) do { } while (0)
73#endif
74
Stephen Hemmingerbea33482007-10-03 16:41:36 -070075#define TX_WORK_PER_LOOP 64
76#define RX_WORK_PER_LOOP 64
Linus Torvalds1da177e2005-04-16 15:20:36 -070077
78/*
79 * Hardware access:
80 */
81
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +000082#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
83#define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
84#define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
85#define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
86#define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
87#define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
88#define DEV_HAS_MSI 0x0000040 /* device supports MSI */
89#define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
90#define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
91#define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
Mike Ditto7b5e0782010-07-25 21:54:28 -070092#define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
93#define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
94#define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
95#define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +000096#define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
97#define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
98#define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
99#define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
100#define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
101#define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
102#define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
103#define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
104#define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
105#define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
106#define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
107#define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
108#define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
110enum {
111 NvRegIrqStatus = 0x000,
112#define NVREG_IRQSTAT_MIIEVENT 0x040
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800113#define NVREG_IRQSTAT_MASK 0x83ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 NvRegIrqMask = 0x004,
115#define NVREG_IRQ_RX_ERROR 0x0001
116#define NVREG_IRQ_RX 0x0002
117#define NVREG_IRQ_RX_NOBUF 0x0004
118#define NVREG_IRQ_TX_ERR 0x0008
Manfred Spraulc2dba062005-07-31 18:29:47 +0200119#define NVREG_IRQ_TX_OK 0x0010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120#define NVREG_IRQ_TIMER 0x0020
121#define NVREG_IRQ_LINK 0x0040
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500122#define NVREG_IRQ_RX_FORCED 0x0080
123#define NVREG_IRQ_TX_FORCED 0x0100
Ayaz Abdulladaa91a92009-02-07 00:25:00 -0800124#define NVREG_IRQ_RECOVER_ERROR 0x8200
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500125#define NVREG_IRQMASK_THROUGHPUT 0x00df
Ayaz Abdulla096a4582007-05-21 20:23:11 -0400126#define NVREG_IRQMASK_CPU 0x0060
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500127#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
128#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500129#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200130
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 NvRegUnknownSetupReg6 = 0x008,
132#define NVREG_UNKSETUP6_VAL 3
133
134/*
135 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
136 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
137 */
138 NvRegPollingInterval = 0x00c,
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000139#define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500140#define NVREG_POLL_DEFAULT_CPU 13
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500141 NvRegMSIMap0 = 0x020,
142 NvRegMSIMap1 = 0x024,
143 NvRegMSIIrqMask = 0x030,
144#define NVREG_MSI_VECTOR_0_ENABLED 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145 NvRegMisc1 = 0x080,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400146#define NVREG_MISC1_PAUSE_TX 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147#define NVREG_MISC1_HD 0x02
148#define NVREG_MISC1_FORCE 0x3b0f3c
149
Ayaz Abdulla0a626772008-01-13 16:02:42 -0500150 NvRegMacReset = 0x34,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400151#define NVREG_MAC_RESET_ASSERT 0x0F3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 NvRegTransmitterControl = 0x084,
153#define NVREG_XMITCTL_START 0x01
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500154#define NVREG_XMITCTL_MGMT_ST 0x40000000
155#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
156#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
157#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
158#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
159#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
160#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
161#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
162#define NVREG_XMITCTL_HOST_LOADED 0x00004000
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500163#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800164#define NVREG_XMITCTL_DATA_START 0x00100000
165#define NVREG_XMITCTL_DATA_READY 0x00010000
166#define NVREG_XMITCTL_DATA_ERROR 0x00020000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 NvRegTransmitterStatus = 0x088,
168#define NVREG_XMITSTAT_BUSY 0x01
169
170 NvRegPacketFilterFlags = 0x8c,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400171#define NVREG_PFF_PAUSE_RX 0x08
172#define NVREG_PFF_ALWAYS 0x7F0000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173#define NVREG_PFF_PROMISC 0x80
174#define NVREG_PFF_MYADDR 0x20
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400175#define NVREG_PFF_LOOPBACK 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176
177 NvRegOffloadConfig = 0x90,
178#define NVREG_OFFLOAD_HOMEPHY 0x601
179#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
180 NvRegReceiverControl = 0x094,
181#define NVREG_RCVCTL_START 0x01
Ayaz Abdullaf35723e2003-02-20 03:03:54 -0500182#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 NvRegReceiverStatus = 0x98,
184#define NVREG_RCVSTAT_BUSY 0x01
185
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700186 NvRegSlotTime = 0x9c,
187#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
188#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
Szymon Janc78aea4f2010-11-27 08:39:43 +0000189#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700190#define NVREG_SLOTTIME_HALF 0x0000ff00
Szymon Janc78aea4f2010-11-27 08:39:43 +0000191#define NVREG_SLOTTIME_DEFAULT 0x00007f00
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700192#define NVREG_SLOTTIME_MASK 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400194 NvRegTxDeferral = 0xA0,
Ayaz Abdullafd9b5582008-02-05 12:29:49 -0500195#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
196#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
197#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
198#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
199#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
200#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
Ayaz Abdulla9744e212006-07-06 16:45:58 -0400201 NvRegRxDeferral = 0xA4,
202#define NVREG_RX_DEFERRAL_DEFAULT 0x16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 NvRegMacAddrA = 0xA8,
204 NvRegMacAddrB = 0xAC,
205 NvRegMulticastAddrA = 0xB0,
206#define NVREG_MCASTADDRA_FORCE 0x01
207 NvRegMulticastAddrB = 0xB4,
208 NvRegMulticastMaskA = 0xB8,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500209#define NVREG_MCASTMASKA_NONE 0xffffffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 NvRegMulticastMaskB = 0xBC,
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -0500211#define NVREG_MCASTMASKB_NONE 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212
213 NvRegPhyInterface = 0xC0,
214#define PHY_RGMII 0x10000000
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700215 NvRegBackOffControl = 0xC4,
216#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
217#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
218#define NVREG_BKOFFCTRL_SELECT 24
219#define NVREG_BKOFFCTRL_GEAR 12
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220
221 NvRegTxRingPhysAddr = 0x100,
222 NvRegRxRingPhysAddr = 0x104,
223 NvRegRingSizes = 0x108,
224#define NVREG_RINGSZ_TXSHIFT 0
225#define NVREG_RINGSZ_RXSHIFT 16
Ayaz Abdulla5070d342006-07-31 12:05:01 -0400226 NvRegTransmitPoll = 0x10c,
227#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228 NvRegLinkSpeed = 0x110,
229#define NVREG_LINKSPEED_FORCE 0x10000
230#define NVREG_LINKSPEED_10 1000
231#define NVREG_LINKSPEED_100 100
232#define NVREG_LINKSPEED_1000 50
233#define NVREG_LINKSPEED_MASK (0xFFF)
234 NvRegUnknownSetupReg5 = 0x130,
235#define NVREG_UNKSETUP5_BIT31 (1<<31)
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400236 NvRegTxWatermark = 0x13c,
237#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
238#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
239#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 NvRegTxRxControl = 0x144,
241#define NVREG_TXRXCTL_KICK 0x0001
242#define NVREG_TXRXCTL_BIT1 0x0002
243#define NVREG_TXRXCTL_BIT2 0x0004
244#define NVREG_TXRXCTL_IDLE 0x0008
245#define NVREG_TXRXCTL_RESET 0x0010
246#define NVREG_TXRXCTL_RXCHECK 0x0400
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400247#define NVREG_TXRXCTL_DESC_1 0
Ayaz Abdullad2f78412007-01-09 13:30:02 -0500248#define NVREG_TXRXCTL_DESC_2 0x002100
249#define NVREG_TXRXCTL_DESC_3 0xc02200
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500250#define NVREG_TXRXCTL_VLANSTRIP 0x00040
251#define NVREG_TXRXCTL_VLANINS 0x00080
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500252 NvRegTxRingPhysAddrHigh = 0x148,
253 NvRegRxRingPhysAddrHigh = 0x14C,
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400254 NvRegTxPauseFrame = 0x170,
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -0500255#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
256#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
257#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
258#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
Ayaz Abdulla9a33e882008-08-06 12:12:34 -0400259 NvRegTxPauseFrameLimit = 0x174,
260#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 NvRegMIIStatus = 0x180,
262#define NVREG_MIISTAT_ERROR 0x0001
263#define NVREG_MIISTAT_LINKCHANGE 0x0008
Ayaz Abdullaeb798422008-02-04 15:14:04 -0500264#define NVREG_MIISTAT_MASK_RW 0x0007
265#define NVREG_MIISTAT_MASK_ALL 0x000f
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500266 NvRegMIIMask = 0x184,
267#define NVREG_MII_LINKCHANGE 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268
269 NvRegAdapterControl = 0x188,
270#define NVREG_ADAPTCTL_START 0x02
271#define NVREG_ADAPTCTL_LINKUP 0x04
272#define NVREG_ADAPTCTL_PHYVALID 0x40000
273#define NVREG_ADAPTCTL_RUNNING 0x100000
274#define NVREG_ADAPTCTL_PHYSHIFT 24
275 NvRegMIISpeed = 0x18c,
276#define NVREG_MIISPEED_BIT8 (1<<8)
277#define NVREG_MIIDELAY 5
278 NvRegMIIControl = 0x190,
279#define NVREG_MIICTL_INUSE 0x08000
280#define NVREG_MIICTL_WRITE 0x00400
281#define NVREG_MIICTL_ADDRSHIFT 5
282 NvRegMIIData = 0x194,
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400283 NvRegTxUnicast = 0x1a0,
284 NvRegTxMulticast = 0x1a4,
285 NvRegTxBroadcast = 0x1a8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286 NvRegWakeUpFlags = 0x200,
287#define NVREG_WAKEUPFLAGS_VAL 0x7770
288#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
289#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
290#define NVREG_WAKEUPFLAGS_D3SHIFT 12
291#define NVREG_WAKEUPFLAGS_D2SHIFT 8
292#define NVREG_WAKEUPFLAGS_D1SHIFT 4
293#define NVREG_WAKEUPFLAGS_D0SHIFT 0
294#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
295#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
296#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
297#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
298
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800299 NvRegMgmtUnitGetVersion = 0x204,
Szymon Janc78aea4f2010-11-27 08:39:43 +0000300#define NVREG_MGMTUNITGETVERSION 0x01
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800301 NvRegMgmtUnitVersion = 0x208,
302#define NVREG_MGMTUNITVERSION 0x08
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 NvRegPowerCap = 0x268,
304#define NVREG_POWERCAP_D3SUPP (1<<30)
305#define NVREG_POWERCAP_D2SUPP (1<<26)
306#define NVREG_POWERCAP_D1SUPP (1<<25)
307 NvRegPowerState = 0x26c,
308#define NVREG_POWERSTATE_POWEREDUP 0x8000
309#define NVREG_POWERSTATE_VALID 0x0100
310#define NVREG_POWERSTATE_MASK 0x0003
311#define NVREG_POWERSTATE_D0 0x0000
312#define NVREG_POWERSTATE_D1 0x0001
313#define NVREG_POWERSTATE_D2 0x0002
314#define NVREG_POWERSTATE_D3 0x0003
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800315 NvRegMgmtUnitControl = 0x278,
316#define NVREG_MGMTUNITCONTROL_INUSE 0x20000
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400317 NvRegTxCnt = 0x280,
318 NvRegTxZeroReXmt = 0x284,
319 NvRegTxOneReXmt = 0x288,
320 NvRegTxManyReXmt = 0x28c,
321 NvRegTxLateCol = 0x290,
322 NvRegTxUnderflow = 0x294,
323 NvRegTxLossCarrier = 0x298,
324 NvRegTxExcessDef = 0x29c,
325 NvRegTxRetryErr = 0x2a0,
326 NvRegRxFrameErr = 0x2a4,
327 NvRegRxExtraByte = 0x2a8,
328 NvRegRxLateCol = 0x2ac,
329 NvRegRxRunt = 0x2b0,
330 NvRegRxFrameTooLong = 0x2b4,
331 NvRegRxOverflow = 0x2b8,
332 NvRegRxFCSErr = 0x2bc,
333 NvRegRxFrameAlignErr = 0x2c0,
334 NvRegRxLenErr = 0x2c4,
335 NvRegRxUnicast = 0x2c8,
336 NvRegRxMulticast = 0x2cc,
337 NvRegRxBroadcast = 0x2d0,
338 NvRegTxDef = 0x2d4,
339 NvRegTxFrame = 0x2d8,
340 NvRegRxCnt = 0x2dc,
341 NvRegTxPause = 0x2e0,
342 NvRegRxPause = 0x2e4,
343 NvRegRxDropFrame = 0x2e8,
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500344 NvRegVlanControl = 0x300,
345#define NVREG_VLANCONTROL_ENABLE 0x2000
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500346 NvRegMSIXMap0 = 0x3e0,
347 NvRegMSIXMap1 = 0x3e4,
348 NvRegMSIXIrqStatus = 0x3f0,
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400349
350 NvRegPowerState2 = 0x600,
Ayaz Abdulla1545e202008-09-22 09:55:35 -0400351#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400352#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400353#define NVREG_POWERSTATE2_PHY_RESET 0x0004
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +0000354#define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355};
356
357/* Big endian: should work, but is untested */
358struct ring_desc {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700359 __le32 buf;
360 __le32 flaglen;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361};
362
Manfred Spraulee733622005-07-31 18:32:26 +0200363struct ring_desc_ex {
Stephen Hemmingera8bed492006-07-27 18:50:09 -0700364 __le32 bufhigh;
365 __le32 buflow;
366 __le32 txvlan;
367 __le32 flaglen;
Manfred Spraulee733622005-07-31 18:32:26 +0200368};
369
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700370union ring_type {
Szymon Janc78aea4f2010-11-27 08:39:43 +0000371 struct ring_desc *orig;
372 struct ring_desc_ex *ex;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700373};
Manfred Spraulee733622005-07-31 18:32:26 +0200374
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375#define FLAG_MASK_V1 0xffff0000
376#define FLAG_MASK_V2 0xffffc000
377#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
378#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
379
380#define NV_TX_LASTPACKET (1<<16)
381#define NV_TX_RETRYERROR (1<<19)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700382#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200383#define NV_TX_FORCED_INTERRUPT (1<<24)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384#define NV_TX_DEFERRED (1<<26)
385#define NV_TX_CARRIERLOST (1<<27)
386#define NV_TX_LATECOLLISION (1<<28)
387#define NV_TX_UNDERFLOW (1<<29)
388#define NV_TX_ERROR (1<<30)
389#define NV_TX_VALID (1<<31)
390
391#define NV_TX2_LASTPACKET (1<<29)
392#define NV_TX2_RETRYERROR (1<<18)
Ayaz Abdullaa4336862008-04-18 13:50:43 -0700393#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
Manfred Spraulc2dba062005-07-31 18:29:47 +0200394#define NV_TX2_FORCED_INTERRUPT (1<<30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395#define NV_TX2_DEFERRED (1<<25)
396#define NV_TX2_CARRIERLOST (1<<26)
397#define NV_TX2_LATECOLLISION (1<<27)
398#define NV_TX2_UNDERFLOW (1<<28)
399/* error and valid are the same for both */
400#define NV_TX2_ERROR (1<<30)
401#define NV_TX2_VALID (1<<31)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400402#define NV_TX2_TSO (1<<28)
403#define NV_TX2_TSO_SHIFT 14
Ayaz Abdullafa454592006-01-05 22:45:45 -0800404#define NV_TX2_TSO_MAX_SHIFT 14
405#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400406#define NV_TX2_CHECKSUM_L3 (1<<27)
407#define NV_TX2_CHECKSUM_L4 (1<<26)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500409#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
410
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411#define NV_RX_DESCRIPTORVALID (1<<16)
412#define NV_RX_MISSEDFRAME (1<<17)
413#define NV_RX_SUBSTRACT1 (1<<18)
414#define NV_RX_ERROR1 (1<<23)
415#define NV_RX_ERROR2 (1<<24)
416#define NV_RX_ERROR3 (1<<25)
417#define NV_RX_ERROR4 (1<<26)
418#define NV_RX_CRCERR (1<<27)
419#define NV_RX_OVERFLOW (1<<28)
420#define NV_RX_FRAMINGERR (1<<29)
421#define NV_RX_ERROR (1<<30)
422#define NV_RX_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400423#define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424
425#define NV_RX2_CHECKSUMMASK (0x1C000000)
Ayaz Abdullabfaffe82008-01-13 16:02:55 -0500426#define NV_RX2_CHECKSUM_IP (0x10000000)
427#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
428#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429#define NV_RX2_DESCRIPTORVALID (1<<29)
430#define NV_RX2_SUBSTRACT1 (1<<25)
431#define NV_RX2_ERROR1 (1<<18)
432#define NV_RX2_ERROR2 (1<<19)
433#define NV_RX2_ERROR3 (1<<20)
434#define NV_RX2_ERROR4 (1<<21)
435#define NV_RX2_CRCERR (1<<22)
436#define NV_RX2_OVERFLOW (1<<23)
437#define NV_RX2_FRAMINGERR (1<<24)
438/* error and avail are the same for both */
439#define NV_RX2_ERROR (1<<30)
440#define NV_RX2_AVAIL (1<<31)
Ayaz Abdulla1ef68412008-08-06 12:11:03 -0400441#define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500443#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
444#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
445
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446/* Miscelaneous hardware related defines: */
Szymon Janc78aea4f2010-11-27 08:39:43 +0000447#define NV_PCI_REGSZ_VER1 0x270
448#define NV_PCI_REGSZ_VER2 0x2d4
449#define NV_PCI_REGSZ_VER3 0x604
450#define NV_PCI_REGSZ_MAX 0x604
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451
452/* various timeout delays: all in usec */
453#define NV_TXRX_RESET_DELAY 4
454#define NV_TXSTOP_DELAY1 10
455#define NV_TXSTOP_DELAY1MAX 500000
456#define NV_TXSTOP_DELAY2 100
457#define NV_RXSTOP_DELAY1 10
458#define NV_RXSTOP_DELAY1MAX 500000
459#define NV_RXSTOP_DELAY2 100
460#define NV_SETUP5_DELAY 5
461#define NV_SETUP5_DELAYMAX 50000
462#define NV_POWERUP_DELAY 5
463#define NV_POWERUP_DELAYMAX 5000
464#define NV_MIIBUSY_DELAY 50
465#define NV_MIIPHY_DELAY 10
466#define NV_MIIPHY_DELAYMAX 10000
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400467#define NV_MAC_RESET_DELAY 64
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468
469#define NV_WAKEUPPATTERNS 5
470#define NV_WAKEUPMASKENTRIES 4
471
472/* General driver defaults */
473#define NV_WATCHDOG_TIMEO (5*HZ)
474
Ayaz Abdulla6cef67a2009-03-05 08:02:30 +0000475#define RX_RING_DEFAULT 512
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400476#define TX_RING_DEFAULT 256
477#define RX_RING_MIN 128
478#define TX_RING_MIN 64
479#define RING_MAX_DESC_VER_1 1024
480#define RING_MAX_DESC_VER_2_3 16384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481
482/* rx/tx mac addr + type + vlan + align + slack*/
Manfred Sprauld81c0982005-07-31 18:20:30 +0200483#define NV_RX_HEADERS (64)
484/* even more slack. */
485#define NV_RX_ALLOC_PAD (64)
486
487/* maximum mtu size */
488#define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
489#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490
491#define OOM_REFILL (1+HZ/20)
492#define POLL_WAIT (1+HZ/100)
493#define LINK_TIMEOUT (3*HZ)
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400494#define STATS_INTERVAL (10*HZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400496/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 * desc_ver values:
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400498 * The nic supports three different descriptor types:
499 * - DESC_VER_1: Original
500 * - DESC_VER_2: support for jumbo frames.
501 * - DESC_VER_3: 64-bit format.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 */
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400503#define DESC_VER_1 1
504#define DESC_VER_2 2
505#define DESC_VER_3 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506
507/* PHY defines */
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400508#define PHY_OUI_MARVELL 0x5043
509#define PHY_OUI_CICADA 0x03f1
510#define PHY_OUI_VITESSE 0x01c1
511#define PHY_OUI_REALTEK 0x0732
512#define PHY_OUI_REALTEK2 0x0020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513#define PHYID1_OUI_MASK 0x03ff
514#define PHYID1_OUI_SHFT 6
515#define PHYID2_OUI_MASK 0xfc00
516#define PHYID2_OUI_SHFT 10
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400517#define PHYID2_MODEL_MASK 0x03f0
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400518#define PHY_MODEL_REALTEK_8211 0x0110
519#define PHY_REV_MASK 0x0001
520#define PHY_REV_REALTEK_8211B 0x0000
521#define PHY_REV_REALTEK_8211C 0x0001
522#define PHY_MODEL_REALTEK_8201 0x0200
523#define PHY_MODEL_MARVELL_E3016 0x0220
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400524#define PHY_MARVELL_E3016_INITMASK 0x0300
Ayaz Abdulla14a67f32007-07-15 06:50:28 -0400525#define PHY_CICADA_INIT1 0x0f000
526#define PHY_CICADA_INIT2 0x0e00
527#define PHY_CICADA_INIT3 0x01000
528#define PHY_CICADA_INIT4 0x0200
529#define PHY_CICADA_INIT5 0x0004
530#define PHY_CICADA_INIT6 0x02000
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400531#define PHY_VITESSE_INIT_REG1 0x1f
532#define PHY_VITESSE_INIT_REG2 0x10
533#define PHY_VITESSE_INIT_REG3 0x11
534#define PHY_VITESSE_INIT_REG4 0x12
535#define PHY_VITESSE_INIT_MSK1 0xc
536#define PHY_VITESSE_INIT_MSK2 0x0180
537#define PHY_VITESSE_INIT1 0x52b5
538#define PHY_VITESSE_INIT2 0xaf8a
539#define PHY_VITESSE_INIT3 0x8
540#define PHY_VITESSE_INIT4 0x8f8a
541#define PHY_VITESSE_INIT5 0xaf86
542#define PHY_VITESSE_INIT6 0x8f86
543#define PHY_VITESSE_INIT7 0xaf82
544#define PHY_VITESSE_INIT8 0x0100
545#define PHY_VITESSE_INIT9 0x8f82
546#define PHY_VITESSE_INIT10 0x0
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400547#define PHY_REALTEK_INIT_REG1 0x1f
548#define PHY_REALTEK_INIT_REG2 0x19
549#define PHY_REALTEK_INIT_REG3 0x13
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400550#define PHY_REALTEK_INIT_REG4 0x14
551#define PHY_REALTEK_INIT_REG5 0x18
552#define PHY_REALTEK_INIT_REG6 0x11
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400553#define PHY_REALTEK_INIT_REG7 0x01
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -0400554#define PHY_REALTEK_INIT1 0x0000
555#define PHY_REALTEK_INIT2 0x8e00
556#define PHY_REALTEK_INIT3 0x0001
557#define PHY_REALTEK_INIT4 0xad17
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400558#define PHY_REALTEK_INIT5 0xfb54
559#define PHY_REALTEK_INIT6 0xf5c7
560#define PHY_REALTEK_INIT7 0x1000
561#define PHY_REALTEK_INIT8 0x0003
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -0400562#define PHY_REALTEK_INIT9 0x0008
563#define PHY_REALTEK_INIT10 0x0005
564#define PHY_REALTEK_INIT11 0x0200
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400565#define PHY_REALTEK_INIT_MSK1 0x0003
Ayaz Abdullad215d8a2007-07-15 06:50:53 -0400566
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567#define PHY_GIGABIT 0x0100
568
569#define PHY_TIMEOUT 0x1
570#define PHY_ERROR 0x2
571
572#define PHY_100 0x1
573#define PHY_1000 0x2
574#define PHY_HALF 0x100
575
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400576#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
577#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
578#define NV_PAUSEFRAME_RX_ENABLE 0x0004
579#define NV_PAUSEFRAME_TX_ENABLE 0x0008
Ayaz Abdullab6d07732006-06-10 22:47:42 -0400580#define NV_PAUSEFRAME_RX_REQ 0x0010
581#define NV_PAUSEFRAME_TX_REQ 0x0020
582#define NV_PAUSEFRAME_AUTONEG 0x0040
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500584/* MSI/MSI-X defines */
585#define NV_MSI_X_MAX_VECTORS 8
586#define NV_MSI_X_VECTORS_MASK 0x000f
587#define NV_MSI_CAPABLE 0x0010
588#define NV_MSI_X_CAPABLE 0x0020
589#define NV_MSI_ENABLED 0x0040
590#define NV_MSI_X_ENABLED 0x0080
591
592#define NV_MSI_X_VECTOR_ALL 0x0
593#define NV_MSI_X_VECTOR_RX 0x0
594#define NV_MSI_X_VECTOR_TX 0x1
595#define NV_MSI_X_VECTOR_OTHER 0x2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596
Ayaz Abdullab6e44052009-02-07 00:24:15 -0800597#define NV_MSI_PRIV_OFFSET 0x68
598#define NV_MSI_PRIV_VALUE 0xffffffff
599
Ayaz Abdullab2976d22008-02-04 15:13:59 -0500600#define NV_RESTART_TX 0x1
601#define NV_RESTART_RX 0x2
602
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500603#define NV_TX_LIMIT_COUNT 16
604
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000605#define NV_DYNAMIC_THRESHOLD 4
606#define NV_DYNAMIC_MAX_QUIET_COUNT 2048
607
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400608/* statistics */
609struct nv_ethtool_str {
610 char name[ETH_GSTRING_LEN];
611};
612
613static const struct nv_ethtool_str nv_estats_str[] = {
614 { "tx_bytes" },
615 { "tx_zero_rexmt" },
616 { "tx_one_rexmt" },
617 { "tx_many_rexmt" },
618 { "tx_late_collision" },
619 { "tx_fifo_errors" },
620 { "tx_carrier_errors" },
621 { "tx_excess_deferral" },
622 { "tx_retry_error" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400623 { "rx_frame_error" },
624 { "rx_extra_byte" },
625 { "rx_late_collision" },
626 { "rx_runt" },
627 { "rx_frame_too_long" },
628 { "rx_over_errors" },
629 { "rx_crc_errors" },
630 { "rx_frame_align_error" },
631 { "rx_length_error" },
632 { "rx_unicast" },
633 { "rx_multicast" },
634 { "rx_broadcast" },
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400635 { "rx_packets" },
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500636 { "rx_errors_total" },
637 { "tx_errors_total" },
638
639 /* version 2 stats */
640 { "tx_deferral" },
641 { "tx_packets" },
642 { "rx_bytes" },
643 { "tx_pause" },
644 { "rx_pause" },
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400645 { "rx_drop_frame" },
646
647 /* version 3 stats */
648 { "tx_unicast" },
649 { "tx_multicast" },
650 { "tx_broadcast" }
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400651};
652
653struct nv_ethtool_stats {
654 u64 tx_bytes;
655 u64 tx_zero_rexmt;
656 u64 tx_one_rexmt;
657 u64 tx_many_rexmt;
658 u64 tx_late_collision;
659 u64 tx_fifo_errors;
660 u64 tx_carrier_errors;
661 u64 tx_excess_deferral;
662 u64 tx_retry_error;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400663 u64 rx_frame_error;
664 u64 rx_extra_byte;
665 u64 rx_late_collision;
666 u64 rx_runt;
667 u64 rx_frame_too_long;
668 u64 rx_over_errors;
669 u64 rx_crc_errors;
670 u64 rx_frame_align_error;
671 u64 rx_length_error;
672 u64 rx_unicast;
673 u64 rx_multicast;
674 u64 rx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400675 u64 rx_packets;
676 u64 rx_errors_total;
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500677 u64 tx_errors_total;
678
679 /* version 2 stats */
680 u64 tx_deferral;
681 u64 tx_packets;
682 u64 rx_bytes;
683 u64 tx_pause;
684 u64 rx_pause;
685 u64 rx_drop_frame;
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400686
687 /* version 3 stats */
688 u64 tx_unicast;
689 u64 tx_multicast;
690 u64 tx_broadcast;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400691};
692
Ayaz Abdulla9c662432008-08-06 12:11:42 -0400693#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
694#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
Ayaz Abdulla57fff692007-01-23 12:27:00 -0500695#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
696
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400697/* diagnostics */
698#define NV_TEST_COUNT_BASE 3
699#define NV_TEST_COUNT_EXTENDED 4
700
701static const struct nv_ethtool_str nv_etests_str[] = {
702 { "link (online/offline)" },
703 { "register (offline) " },
704 { "interrupt (offline) " },
705 { "loopback (offline) " }
706};
707
708struct register_test {
Al Viro5bb7ea22007-12-09 16:06:41 +0000709 __u32 reg;
710 __u32 mask;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400711};
712
713static const struct register_test nv_registers_test[] = {
714 { NvRegUnknownSetupReg6, 0x01 },
715 { NvRegMisc1, 0x03c },
716 { NvRegOffloadConfig, 0x03ff },
717 { NvRegMulticastAddrA, 0xffffffff },
Ayaz Abdulla95d161c2006-07-06 16:46:25 -0400718 { NvRegTxWatermark, 0x0ff },
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400719 { NvRegWakeUpFlags, 0x07777 },
Szymon Janc78aea4f2010-11-27 08:39:43 +0000720 { 0, 0 }
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400721};
722
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500723struct nv_skb_map {
724 struct sk_buff *skb;
725 dma_addr_t dma;
Eric Dumazet73a37072009-06-17 21:17:59 +0000726 unsigned int dma_len:31;
727 unsigned int dma_single:1;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500728 struct ring_desc_ex *first_tx_desc;
729 struct nv_skb_map *next_tx_ctx;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500730};
731
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732/*
733 * SMP locking:
Wang Chenb74ca3a2008-12-08 01:14:16 -0800734 * All hardware access under netdev_priv(dev)->lock, except the performance
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735 * critical parts:
736 * - rx is (pseudo-) lockless: it relies on the single-threading provided
737 * by the arch code for interrupts.
Herbert Xu932ff272006-06-09 12:20:56 -0700738 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
Wang Chenb74ca3a2008-12-08 01:14:16 -0800739 * needs netdev_priv(dev)->lock :-(
Herbert Xu932ff272006-06-09 12:20:56 -0700740 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 */
742
743/* in dev: base, irq */
744struct fe_priv {
745 spinlock_t lock;
746
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700747 struct net_device *dev;
748 struct napi_struct napi;
749
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750 /* General data:
751 * Locking: spin_lock(&np->lock); */
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400752 struct nv_ethtool_stats estats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753 int in_shutdown;
754 u32 linkspeed;
755 int duplex;
756 int autoneg;
757 int fixed_mode;
758 int phyaddr;
759 int wolenabled;
760 unsigned int phy_oui;
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -0400761 unsigned int phy_model;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400762 unsigned int phy_rev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763 u16 gigabit;
Ayaz Abdulla9589c772006-06-10 22:48:13 -0400764 int intr_test;
Ayaz Abdullac5cf9102006-10-30 17:32:01 -0500765 int recover_error;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000766 int quiet_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767
768 /* General data: RO fields */
769 dma_addr_t ring_addr;
770 struct pci_dev *pci_dev;
771 u32 orig_mac[2];
Ayaz Abdulla582806b2009-03-05 08:02:03 +0000772 u32 events;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773 u32 irqmask;
774 u32 desc_ver;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -0400775 u32 txrxctl_bits;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500776 u32 vlanctl_bits;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400777 u32 driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400778 u32 device_id;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -0400779 u32 register_size;
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -0400780 int rx_csum;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -0500781 u32 mac_in_use;
Ayaz Abdullacac1c522009-02-07 00:23:57 -0800782 int mgmt_version;
783 int mgmt_sema;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784
785 void __iomem *base;
786
787 /* rx specific fields.
788 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
789 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500790 union ring_type get_rx, put_rx, first_rx, last_rx;
791 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
792 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
793 struct nv_skb_map *rx_skb;
794
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700795 union ring_type rx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796 unsigned int rx_buf_sz;
Manfred Sprauld81c0982005-07-31 18:20:30 +0200797 unsigned int pkt_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 struct timer_list oom_kick;
799 struct timer_list nic_poll;
Ayaz Abdulla52da3572006-06-10 22:48:04 -0400800 struct timer_list stats_poll;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500801 u32 nic_poll_irq;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400802 int rx_ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803
804 /* media detection workaround.
805 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
806 */
807 int need_linktimer;
808 unsigned long link_timeout;
809 /*
810 * tx specific fields.
811 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -0500812 union ring_type get_tx, put_tx, first_tx, last_tx;
813 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
814 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
815 struct nv_skb_map *tx_skb;
816
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700817 union ring_type tx_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 u32 tx_flags;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -0400819 int tx_ring_size;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -0500820 int tx_limit;
821 u32 tx_pkts_in_progress;
822 struct nv_skb_map *tx_change_owner;
823 struct nv_skb_map *tx_end_flip;
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -0500824 int tx_stop;
Ayaz Abdullaee407b02006-02-04 13:13:17 -0500825
826 /* vlan fields */
827 struct vlan_group *vlangrp;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500828
829 /* msi/msi-x fields */
830 u32 msi_flags;
831 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
Ayaz Abdullaeb91f612006-05-24 18:13:19 -0400832
833 /* flow control */
834 u32 pause_flags;
Tobias Diedrich1a1ca862008-05-18 15:03:44 +0200835
836 /* power saved state */
837 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
Yinghai Luddb213f2009-02-06 01:29:23 -0800838
839 /* for different msi-x irq type */
840 char name_rx[IFNAMSIZ + 3]; /* -rx */
841 char name_tx[IFNAMSIZ + 3]; /* -tx */
842 char name_other[IFNAMSIZ + 6]; /* -other */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843};
844
845/*
846 * Maximum number of loops until we assume that a bit in the irq mask
847 * is stuck. Overridable with module param.
848 */
Ayaz Abdulla4145ade2009-03-05 08:02:26 +0000849static int max_interrupt_work = 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500851/*
852 * Optimization can be either throuput mode or cpu mode
Jeff Garzikf3b197a2006-05-26 21:39:03 -0400853 *
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500854 * Throughput Mode: Every tx and rx packet will generate an interrupt.
855 * CPU Mode: Interrupts are controlled by a timer.
856 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400857enum {
858 NV_OPTIMIZATION_MODE_THROUGHPUT,
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000859 NV_OPTIMIZATION_MODE_CPU,
860 NV_OPTIMIZATION_MODE_DYNAMIC
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400861};
Ayaz Abdulla9e184762009-03-05 08:02:18 +0000862static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
Ayaz Abdullaa971c322005-11-11 08:30:38 -0500863
864/*
865 * Poll interval for timer irq
866 *
867 * This interval determines how frequent an interrupt is generated.
868 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
869 * Min = 0, and Max = 65535
870 */
871static int poll_interval = -1;
872
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500873/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400874 * MSI interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500875 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400876enum {
877 NV_MSI_INT_DISABLED,
878 NV_MSI_INT_ENABLED
879};
880static int msi = NV_MSI_INT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500881
882/*
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400883 * MSIX interrupts
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500884 */
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400885enum {
886 NV_MSIX_INT_DISABLED,
887 NV_MSIX_INT_ENABLED
888};
Yinghai Lu39482792009-02-06 01:31:12 -0800889static int msix = NV_MSIX_INT_ENABLED;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -0400890
891/*
892 * DMA 64bit
893 */
894enum {
895 NV_DMA_64BIT_DISABLED,
896 NV_DMA_64BIT_ENABLED
897};
898static int dma_64bit = NV_DMA_64BIT_ENABLED;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -0500899
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -0400900/*
901 * Crossover Detection
902 * Realtek 8201 phy + some OEM boards do not work properly.
903 */
904enum {
905 NV_CROSSOVER_DETECTION_DISABLED,
906 NV_CROSSOVER_DETECTION_ENABLED
907};
908static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
909
Ed Swierk5a9a8e32009-06-02 00:19:52 -0700910/*
911 * Power down phy when interface is down (persists through reboot;
912 * older Linux and other OSes may not power it up again)
913 */
Szymon Janc78aea4f2010-11-27 08:39:43 +0000914static int phy_power_down;
Ed Swierk5a9a8e32009-06-02 00:19:52 -0700915
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916static inline struct fe_priv *get_nvpriv(struct net_device *dev)
917{
918 return netdev_priv(dev);
919}
920
921static inline u8 __iomem *get_hwbase(struct net_device *dev)
922{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -0400923 return ((struct fe_priv *)netdev_priv(dev))->base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924}
925
926static inline void pci_push(u8 __iomem *base)
927{
928 /* force out pending posted writes */
929 readl(base);
930}
931
932static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
933{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700934 return le32_to_cpu(prd->flaglen)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
936}
937
Manfred Spraulee733622005-07-31 18:32:26 +0200938static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
939{
Stephen Hemmingerf82a9352006-07-27 18:50:08 -0700940 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
Manfred Spraulee733622005-07-31 18:32:26 +0200941}
942
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400943static bool nv_optimized(struct fe_priv *np)
944{
945 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
946 return false;
947 return true;
948}
949
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
Joe Perches344d0dc2010-11-29 07:41:52 +0000951 int delay, int delaymax)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952{
953 u8 __iomem *base = get_hwbase(dev);
954
955 pci_push(base);
956 do {
957 udelay(delay);
958 delaymax -= delay;
Joe Perches344d0dc2010-11-29 07:41:52 +0000959 if (delaymax < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 } while ((readl(base + offset) & mask) != target);
962 return 0;
963}
964
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500965#define NV_SETUP_RX_RING 0x01
966#define NV_SETUP_TX_RING 0x02
967
Al Viro5bb7ea22007-12-09 16:06:41 +0000968static inline u32 dma_low(dma_addr_t addr)
969{
970 return addr;
971}
972
973static inline u32 dma_high(dma_addr_t addr)
974{
975 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
976}
977
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500978static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
979{
980 struct fe_priv *np = get_nvpriv(dev);
981 u8 __iomem *base = get_hwbase(dev);
982
Jeff Garzik36b30ea2007-10-16 01:40:30 -0400983 if (!nv_optimized(np)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +0000984 if (rxtx_flags & NV_SETUP_RX_RING)
Al Viro5bb7ea22007-12-09 16:06:41 +0000985 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
Szymon Janc78aea4f2010-11-27 08:39:43 +0000986 if (rxtx_flags & NV_SETUP_TX_RING)
Al Viro5bb7ea22007-12-09 16:06:41 +0000987 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500988 } else {
989 if (rxtx_flags & NV_SETUP_RX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000990 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
991 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500992 }
993 if (rxtx_flags & NV_SETUP_TX_RING) {
Al Viro5bb7ea22007-12-09 16:06:41 +0000994 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
995 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
Ayaz Abdulla0832b252006-02-04 13:13:26 -0500996 }
997 }
998}
999
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001000static void free_rings(struct net_device *dev)
1001{
1002 struct fe_priv *np = get_nvpriv(dev);
1003
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001004 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001005 if (np->rx_ring.orig)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001006 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1007 np->rx_ring.orig, np->ring_addr);
1008 } else {
1009 if (np->rx_ring.ex)
1010 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1011 np->rx_ring.ex, np->ring_addr);
1012 }
Szymon Janc9b03b062010-11-27 08:39:44 +00001013 kfree(np->rx_skb);
1014 kfree(np->tx_skb);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001015}
1016
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001017static int using_multi_irqs(struct net_device *dev)
1018{
1019 struct fe_priv *np = get_nvpriv(dev);
1020
1021 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1022 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1023 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1024 return 0;
1025 else
1026 return 1;
1027}
1028
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00001029static void nv_txrx_gate(struct net_device *dev, bool gate)
1030{
1031 struct fe_priv *np = get_nvpriv(dev);
1032 u8 __iomem *base = get_hwbase(dev);
1033 u32 powerstate;
1034
1035 if (!np->mac_in_use &&
1036 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1037 powerstate = readl(base + NvRegPowerState2);
1038 if (gate)
1039 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1040 else
1041 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1042 writel(powerstate, base + NvRegPowerState2);
1043 }
1044}
1045
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001046static void nv_enable_irq(struct net_device *dev)
1047{
1048 struct fe_priv *np = get_nvpriv(dev);
1049
1050 if (!using_multi_irqs(dev)) {
1051 if (np->msi_flags & NV_MSI_X_ENABLED)
1052 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1053 else
Manfred Spraula7475902007-10-17 21:52:33 +02001054 enable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001055 } else {
1056 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1057 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1058 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1059 }
1060}
1061
1062static void nv_disable_irq(struct net_device *dev)
1063{
1064 struct fe_priv *np = get_nvpriv(dev);
1065
1066 if (!using_multi_irqs(dev)) {
1067 if (np->msi_flags & NV_MSI_X_ENABLED)
1068 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1069 else
Manfred Spraula7475902007-10-17 21:52:33 +02001070 disable_irq(np->pci_dev->irq);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07001071 } else {
1072 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1073 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1074 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1075 }
1076}
1077
1078/* In MSIX mode, a write to irqmask behaves as XOR */
1079static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1080{
1081 u8 __iomem *base = get_hwbase(dev);
1082
1083 writel(mask, base + NvRegIrqMask);
1084}
1085
1086static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1087{
1088 struct fe_priv *np = get_nvpriv(dev);
1089 u8 __iomem *base = get_hwbase(dev);
1090
1091 if (np->msi_flags & NV_MSI_X_ENABLED) {
1092 writel(mask, base + NvRegIrqMask);
1093 } else {
1094 if (np->msi_flags & NV_MSI_ENABLED)
1095 writel(0, base + NvRegMSIIrqMask);
1096 writel(0, base + NvRegIrqMask);
1097 }
1098}
1099
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001100static void nv_napi_enable(struct net_device *dev)
1101{
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001102 struct fe_priv *np = get_nvpriv(dev);
1103
1104 napi_enable(&np->napi);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001105}
1106
1107static void nv_napi_disable(struct net_device *dev)
1108{
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001109 struct fe_priv *np = get_nvpriv(dev);
1110
1111 napi_disable(&np->napi);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00001112}
1113
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114#define MII_READ (-1)
1115/* mii_rw: read/write a register on the PHY.
1116 *
1117 * Caller must guarantee serialization
1118 */
1119static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1120{
1121 u8 __iomem *base = get_hwbase(dev);
1122 u32 reg;
1123 int retval;
1124
Ayaz Abdullaeb798422008-02-04 15:14:04 -05001125 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126
1127 reg = readl(base + NvRegMIIControl);
1128 if (reg & NVREG_MIICTL_INUSE) {
1129 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1130 udelay(NV_MIIBUSY_DELAY);
1131 }
1132
1133 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1134 if (value != MII_READ) {
1135 writel(value, base + NvRegMIIData);
1136 reg |= NVREG_MIICTL_WRITE;
1137 }
1138 writel(reg, base + NvRegMIIControl);
1139
1140 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
Joe Perches344d0dc2010-11-29 07:41:52 +00001141 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
Joe Perches6b808582010-11-29 07:41:53 +00001142 netdev_dbg(dev, "mii_rw of reg %d at PHY %d timed out\n",
1143 miireg, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001144 retval = -1;
1145 } else if (value != MII_READ) {
1146 /* it was a write operation - fewer failures are detectable */
Joe Perches6b808582010-11-29 07:41:53 +00001147 netdev_dbg(dev, "mii_rw wrote 0x%x to reg %d at PHY %d\n",
1148 value, miireg, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149 retval = 0;
1150 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
Joe Perches6b808582010-11-29 07:41:53 +00001151 netdev_dbg(dev, "mii_rw of reg %d at PHY %d failed\n",
1152 miireg, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153 retval = -1;
1154 } else {
1155 retval = readl(base + NvRegMIIData);
Joe Perches6b808582010-11-29 07:41:53 +00001156 netdev_dbg(dev, "mii_rw read from reg %d at PHY %d: 0x%x\n",
1157 miireg, addr, retval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158 }
1159
1160 return retval;
1161}
1162
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001163static int phy_reset(struct net_device *dev, u32 bmcr_setup)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001165 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166 u32 miicontrol;
1167 unsigned int tries = 0;
1168
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001169 miicontrol = BMCR_RESET | bmcr_setup;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001170 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001172
1173 /* wait for 500ms */
1174 msleep(500);
1175
1176 /* must wait till reset is deasserted */
1177 while (miicontrol & BMCR_RESET) {
Szymon Jancde855b92010-11-27 08:39:48 +00001178 usleep_range(10000, 20000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1180 /* FIXME: 100 tries seem excessive */
1181 if (tries++ > 100)
1182 return -1;
1183 }
1184 return 0;
1185}
1186
1187static int phy_init(struct net_device *dev)
1188{
1189 struct fe_priv *np = get_nvpriv(dev);
1190 u8 __iomem *base = get_hwbase(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001191 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001192
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001193 /* phy errata for E3016 phy */
1194 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1195 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1196 reg &= ~PHY_MARVELL_E3016_INITMASK;
1197 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1198 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1199 return PHY_ERROR;
1200 }
1201 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001202 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001203 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1204 np->phy_rev == PHY_REV_REALTEK_8211B) {
1205 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1206 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1207 return PHY_ERROR;
1208 }
1209 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1210 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1211 return PHY_ERROR;
1212 }
1213 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1214 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1215 return PHY_ERROR;
1216 }
1217 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1218 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1219 return PHY_ERROR;
1220 }
1221 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1222 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1223 return PHY_ERROR;
1224 }
1225 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1226 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1227 return PHY_ERROR;
1228 }
1229 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1230 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1231 return PHY_ERROR;
1232 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001233 }
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001234 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1235 np->phy_rev == PHY_REV_REALTEK_8211C) {
1236 u32 powerstate = readl(base + NvRegPowerState2);
1237
1238 /* need to perform hw phy reset */
1239 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1240 writel(powerstate, base + NvRegPowerState2);
1241 msleep(25);
1242
1243 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1244 writel(powerstate, base + NvRegPowerState2);
1245 msleep(25);
1246
1247 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1248 reg |= PHY_REALTEK_INIT9;
1249 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1250 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1251 return PHY_ERROR;
1252 }
1253 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1254 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1255 return PHY_ERROR;
1256 }
1257 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1258 if (!(reg & PHY_REALTEK_INIT11)) {
1259 reg |= PHY_REALTEK_INIT11;
1260 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1261 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1262 return PHY_ERROR;
1263 }
1264 }
1265 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1266 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1267 return PHY_ERROR;
1268 }
1269 }
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001270 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00001271 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001272 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1273 phy_reserved |= PHY_REALTEK_INIT7;
1274 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1275 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1276 return PHY_ERROR;
1277 }
1278 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001279 }
1280 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001281
Linus Torvalds1da177e2005-04-16 15:20:36 -07001282 /* set advertise register */
1283 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001284 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1286 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1287 return PHY_ERROR;
1288 }
1289
1290 /* get phy interface type */
1291 phyinterface = readl(base + NvRegPhyInterface);
1292
1293 /* see if gigabit phy */
1294 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1295 if (mii_status & PHY_GIGABIT) {
1296 np->gigabit = PHY_GIGABIT;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001297 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298 mii_control_1000 &= ~ADVERTISE_1000HALF;
1299 if (phyinterface & PHY_RGMII)
1300 mii_control_1000 |= ADVERTISE_1000FULL;
1301 else
1302 mii_control_1000 &= ~ADVERTISE_1000FULL;
1303
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001304 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1306 return PHY_ERROR;
1307 }
Szymon Janc78aea4f2010-11-27 08:39:43 +00001308 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309 np->gigabit = 0;
1310
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04001311 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1312 mii_control |= BMCR_ANENABLE;
1313
Ayaz Abdulla22ae03a2008-07-25 15:31:29 -04001314 if (np->phy_oui == PHY_OUI_REALTEK &&
1315 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1316 np->phy_rev == PHY_REV_REALTEK_8211C) {
1317 /* start autoneg since we already performed hw reset above */
1318 mii_control |= BMCR_ANRESTART;
1319 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1320 printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1321 return PHY_ERROR;
1322 }
1323 } else {
1324 /* reset the phy
1325 * (certain phys need bmcr to be setup with reset)
1326 */
1327 if (phy_reset(dev, mii_control)) {
1328 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1329 return PHY_ERROR;
1330 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001331 }
1332
1333 /* phy vendor specific configuration */
Szymon Janc78aea4f2010-11-27 08:39:43 +00001334 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001335 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001336 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1337 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1339 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1340 return PHY_ERROR;
1341 }
1342 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001343 phy_reserved |= PHY_CICADA_INIT5;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001344 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1345 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1346 return PHY_ERROR;
1347 }
1348 }
1349 if (np->phy_oui == PHY_OUI_CICADA) {
1350 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
Ayaz Abdulla14a67f32007-07-15 06:50:28 -04001351 phy_reserved |= PHY_CICADA_INIT6;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1353 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1354 return PHY_ERROR;
1355 }
1356 }
Ayaz Abdullad215d8a2007-07-15 06:50:53 -04001357 if (np->phy_oui == PHY_OUI_VITESSE) {
1358 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1359 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1360 return PHY_ERROR;
1361 }
1362 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1363 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1364 return PHY_ERROR;
1365 }
1366 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1367 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1368 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369 return PHY_ERROR;
1370 }
1371 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1372 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1373 phy_reserved |= PHY_VITESSE_INIT3;
1374 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1375 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1376 return PHY_ERROR;
1377 }
1378 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1379 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1380 return PHY_ERROR;
1381 }
1382 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1383 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1384 return PHY_ERROR;
1385 }
1386 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1387 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1388 phy_reserved |= PHY_VITESSE_INIT3;
1389 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1390 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1391 return PHY_ERROR;
1392 }
1393 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1394 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1395 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1396 return PHY_ERROR;
1397 }
1398 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1399 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1400 return PHY_ERROR;
1401 }
1402 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1403 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1404 return PHY_ERROR;
1405 }
1406 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1407 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1408 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1409 return PHY_ERROR;
1410 }
1411 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1412 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1413 phy_reserved |= PHY_VITESSE_INIT8;
1414 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1415 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1416 return PHY_ERROR;
1417 }
1418 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1419 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1420 return PHY_ERROR;
1421 }
1422 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1423 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1424 return PHY_ERROR;
1425 }
1426 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001427 if (np->phy_oui == PHY_OUI_REALTEK) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001428 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1429 np->phy_rev == PHY_REV_REALTEK_8211B) {
1430 /* reset could have cleared these out, set them back */
1431 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1432 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1433 return PHY_ERROR;
1434 }
1435 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1436 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1437 return PHY_ERROR;
1438 }
1439 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1440 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1441 return PHY_ERROR;
1442 }
1443 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1444 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1445 return PHY_ERROR;
1446 }
1447 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1448 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1449 return PHY_ERROR;
1450 }
1451 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1452 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1453 return PHY_ERROR;
1454 }
1455 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1456 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1457 return PHY_ERROR;
1458 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001459 }
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001460 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00001461 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04001462 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1463 phy_reserved |= PHY_REALTEK_INIT7;
1464 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1465 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1466 return PHY_ERROR;
1467 }
1468 }
1469 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1470 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1471 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1472 return PHY_ERROR;
1473 }
1474 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1475 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1476 phy_reserved |= PHY_REALTEK_INIT3;
1477 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1478 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1479 return PHY_ERROR;
1480 }
1481 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1482 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1483 return PHY_ERROR;
1484 }
1485 }
Ayaz Abdullac5e3ae82007-07-15 06:51:03 -04001486 }
1487 }
1488
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04001489 /* some phys clear out pause advertisment on reset, set it back */
1490 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491
Ed Swierkcb52deb2008-12-01 12:24:43 +00001492 /* restart auto negotiation, power down phy */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001493 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ed Swierk5a9a8e32009-06-02 00:19:52 -07001494 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001495 if (phy_power_down)
Ed Swierk5a9a8e32009-06-02 00:19:52 -07001496 mii_control |= BMCR_PDOWN;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001497 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498 return PHY_ERROR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499
1500 return 0;
1501}
1502
1503static void nv_start_rx(struct net_device *dev)
1504{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001505 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001507 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001508
Joe Perches6b808582010-11-29 07:41:53 +00001509 netdev_dbg(dev, "%s\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001510 /* Already running? Stop it. */
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001511 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1512 rx_ctrl &= ~NVREG_RCVCTL_START;
1513 writel(rx_ctrl, base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001514 pci_push(base);
1515 }
1516 writel(np->linkspeed, base + NvRegLinkSpeed);
1517 pci_push(base);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001518 rx_ctrl |= NVREG_RCVCTL_START;
1519 if (np->mac_in_use)
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001520 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1521 writel(rx_ctrl, base + NvRegReceiverControl);
Joe Perches6b808582010-11-29 07:41:53 +00001522 netdev_dbg(dev, "%s: duplex %d, speed 0x%08x\n",
1523 __func__, np->duplex, np->linkspeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524 pci_push(base);
1525}
1526
1527static void nv_stop_rx(struct net_device *dev)
1528{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001529 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001531 u32 rx_ctrl = readl(base + NvRegReceiverControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532
Joe Perches6b808582010-11-29 07:41:53 +00001533 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001534 if (!np->mac_in_use)
1535 rx_ctrl &= ~NVREG_RCVCTL_START;
1536 else
1537 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1538 writel(rx_ctrl, base + NvRegReceiverControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00001539 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1540 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1541 printk(KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001542
1543 udelay(NV_RXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001544 if (!np->mac_in_use)
1545 writel(0, base + NvRegLinkSpeed);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001546}
1547
1548static void nv_start_tx(struct net_device *dev)
1549{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001550 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001552 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553
Joe Perches6b808582010-11-29 07:41:53 +00001554 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001555 tx_ctrl |= NVREG_XMITCTL_START;
1556 if (np->mac_in_use)
1557 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1558 writel(tx_ctrl, base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559 pci_push(base);
1560}
1561
1562static void nv_stop_tx(struct net_device *dev)
1563{
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001564 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001566 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001567
Joe Perches6b808582010-11-29 07:41:53 +00001568 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001569 if (!np->mac_in_use)
1570 tx_ctrl &= ~NVREG_XMITCTL_START;
1571 else
1572 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1573 writel(tx_ctrl, base + NvRegTransmitterControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00001574 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1575 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1576 printk(KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001577
1578 udelay(NV_TXSTOP_DELAY2);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05001579 if (!np->mac_in_use)
1580 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1581 base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582}
1583
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001584static void nv_start_rxtx(struct net_device *dev)
1585{
1586 nv_start_rx(dev);
1587 nv_start_tx(dev);
1588}
1589
1590static void nv_stop_rxtx(struct net_device *dev)
1591{
1592 nv_stop_rx(dev);
1593 nv_stop_tx(dev);
1594}
1595
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596static void nv_txrx_reset(struct net_device *dev)
1597{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001598 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599 u8 __iomem *base = get_hwbase(dev);
1600
Joe Perches6b808582010-11-29 07:41:53 +00001601 netdev_dbg(dev, "%s\n", __func__);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001602 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603 pci_push(base);
1604 udelay(NV_TXRX_RESET_DELAY);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04001605 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606 pci_push(base);
1607}
1608
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001609static void nv_mac_reset(struct net_device *dev)
1610{
1611 struct fe_priv *np = netdev_priv(dev);
1612 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001613 u32 temp1, temp2, temp3;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001614
Joe Perches6b808582010-11-29 07:41:53 +00001615 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001616
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001617 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1618 pci_push(base);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001619
1620 /* save registers since they will be cleared on reset */
1621 temp1 = readl(base + NvRegMacAddrA);
1622 temp2 = readl(base + NvRegMacAddrB);
1623 temp3 = readl(base + NvRegTransmitPoll);
1624
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001625 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1626 pci_push(base);
1627 udelay(NV_MAC_RESET_DELAY);
1628 writel(0, base + NvRegMacReset);
1629 pci_push(base);
1630 udelay(NV_MAC_RESET_DELAY);
Ayaz Abdulla4e84f9b2008-02-04 15:14:09 -05001631
1632 /* restore saved registers */
1633 writel(temp1, base + NvRegMacAddrA);
1634 writel(temp2, base + NvRegMacAddrB);
1635 writel(temp3, base + NvRegTransmitPoll);
1636
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04001637 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1638 pci_push(base);
1639}
1640
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001641static void nv_get_hw_stats(struct net_device *dev)
1642{
1643 struct fe_priv *np = netdev_priv(dev);
1644 u8 __iomem *base = get_hwbase(dev);
1645
1646 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1647 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1648 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1649 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1650 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1651 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1652 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1653 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1654 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1655 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1656 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1657 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1658 np->estats.rx_runt += readl(base + NvRegRxRunt);
1659 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1660 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1661 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1662 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1663 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1664 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1665 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1666 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1667 np->estats.rx_packets =
1668 np->estats.rx_unicast +
1669 np->estats.rx_multicast +
1670 np->estats.rx_broadcast;
1671 np->estats.rx_errors_total =
1672 np->estats.rx_crc_errors +
1673 np->estats.rx_over_errors +
1674 np->estats.rx_frame_error +
1675 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1676 np->estats.rx_late_collision +
1677 np->estats.rx_runt +
1678 np->estats.rx_frame_too_long;
1679 np->estats.tx_errors_total =
1680 np->estats.tx_late_collision +
1681 np->estats.tx_fifo_errors +
1682 np->estats.tx_carrier_errors +
1683 np->estats.tx_excess_deferral +
1684 np->estats.tx_retry_error;
1685
1686 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1687 np->estats.tx_deferral += readl(base + NvRegTxDef);
1688 np->estats.tx_packets += readl(base + NvRegTxFrame);
1689 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1690 np->estats.tx_pause += readl(base + NvRegTxPause);
1691 np->estats.rx_pause += readl(base + NvRegRxPause);
1692 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1693 }
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001694
1695 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1696 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1697 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1698 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1699 }
Ayaz Abdulla57fff692007-01-23 12:27:00 -05001700}
1701
Linus Torvalds1da177e2005-04-16 15:20:36 -07001702/*
1703 * nv_get_stats: dev->get_stats function
1704 * Get latest stats value from the nic.
1705 * Called with read_lock(&dev_base_lock) held for read -
1706 * only synchronized against unregister_netdevice.
1707 */
1708static struct net_device_stats *nv_get_stats(struct net_device *dev)
1709{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001710 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001711
Ayaz Abdulla21828162007-01-23 12:27:21 -05001712 /* If the nic supports hw counters then retrieve latest values */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04001713 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05001714 nv_get_hw_stats(dev);
1715
1716 /* copy to net_device stats */
Jeff Garzik8148ff42007-10-16 20:56:09 -04001717 dev->stats.tx_bytes = np->estats.tx_bytes;
1718 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1719 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1720 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1721 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1722 dev->stats.rx_errors = np->estats.rx_errors_total;
1723 dev->stats.tx_errors = np->estats.tx_errors_total;
Ayaz Abdulla21828162007-01-23 12:27:21 -05001724 }
Jeff Garzik8148ff42007-10-16 20:56:09 -04001725
1726 return &dev->stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001727}
1728
1729/*
1730 * nv_alloc_rx: fill rx ring entries.
1731 * Return 1 if the allocations for the skbs failed and the
1732 * rx engine is without Available descriptors
1733 */
1734static int nv_alloc_rx(struct net_device *dev)
1735{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001736 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001737 struct ring_desc *less_rx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001739 less_rx = np->get_rx.orig;
1740 if (less_rx-- == np->first_rx.orig)
1741 less_rx = np->last_rx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001742
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001743 while (np->put_rx.orig != less_rx) {
1744 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001745 if (skb) {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001746 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001747 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1748 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001749 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001750 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001751 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001752 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1753 wmb();
1754 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001755 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001756 np->put_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001757 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001758 np->put_rx_ctx = np->first_rx_ctx;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001759 } else
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001760 return 1;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001761 }
1762 return 0;
1763}
1764
1765static int nv_alloc_rx_optimized(struct net_device *dev)
1766{
1767 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00001768 struct ring_desc_ex *less_rx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001769
1770 less_rx = np->get_rx.ex;
1771 if (less_rx-- == np->first_rx.ex)
1772 less_rx = np->last_rx.ex;
1773
1774 while (np->put_rx.ex != less_rx) {
1775 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1776 if (skb) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001777 np->put_rx_ctx->skb = skb;
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001778 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1779 skb->data,
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001780 skb_tailroom(skb),
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001781 PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03001782 np->put_rx_ctx->dma_len = skb_tailroom(skb);
Al Viro5bb7ea22007-12-09 16:06:41 +00001783 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1784 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001785 wmb();
1786 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001787 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001788 np->put_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05001789 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001790 np->put_rx_ctx = np->first_rx_ctx;
Szymon Janc78aea4f2010-11-27 08:39:43 +00001791 } else
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05001792 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001793 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001794 return 0;
1795}
1796
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001797/* If rx bufs are exhausted called after 50ms to attempt to refresh */
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001798static void nv_do_rx_refill(unsigned long data)
1799{
1800 struct net_device *dev = (struct net_device *) data;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001801 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001802
1803 /* Just reschedule NAPI rx processing */
Ben Hutchings288379f2009-01-19 16:43:59 -08001804 napi_schedule(&np->napi);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07001805}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001806
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001807static void nv_init_rx(struct net_device *dev)
Manfred Sprauld81c0982005-07-31 18:20:30 +02001808{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001809 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02001810 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001811
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001812 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001813
1814 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001815 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1816 else
1817 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1818 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1819 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
Manfred Sprauld81c0982005-07-31 18:20:30 +02001820
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001821 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001822 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001823 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001824 np->rx_ring.orig[i].buf = 0;
1825 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001826 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001827 np->rx_ring.ex[i].txvlan = 0;
1828 np->rx_ring.ex[i].bufhigh = 0;
1829 np->rx_ring.ex[i].buflow = 0;
1830 }
1831 np->rx_skb[i].skb = NULL;
1832 np->rx_skb[i].dma = 0;
1833 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001834}
1835
1836static void nv_init_tx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001837{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001838 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001839 int i;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001840
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001841 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001842
1843 if (!nv_optimized(np))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001844 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1845 else
1846 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1847 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1848 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001849 np->tx_pkts_in_progress = 0;
1850 np->tx_change_owner = NULL;
1851 np->tx_end_flip = NULL;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00001852 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001853
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001854 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001855 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001856 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001857 np->tx_ring.orig[i].buf = 0;
1858 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001859 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001860 np->tx_ring.ex[i].txvlan = 0;
1861 np->tx_ring.ex[i].bufhigh = 0;
1862 np->tx_ring.ex[i].buflow = 0;
1863 }
1864 np->tx_skb[i].skb = NULL;
1865 np->tx_skb[i].dma = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001866 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00001867 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001868 np->tx_skb[i].first_tx_desc = NULL;
1869 np->tx_skb[i].next_tx_ctx = NULL;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001870 }
Manfred Sprauld81c0982005-07-31 18:20:30 +02001871}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001872
Manfred Sprauld81c0982005-07-31 18:20:30 +02001873static int nv_init_ring(struct net_device *dev)
1874{
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001875 struct fe_priv *np = netdev_priv(dev);
1876
Manfred Sprauld81c0982005-07-31 18:20:30 +02001877 nv_init_tx(dev);
1878 nv_init_rx(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001879
1880 if (!nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05001881 return nv_alloc_rx(dev);
1882 else
1883 return nv_alloc_rx_optimized(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884}
1885
Eric Dumazet73a37072009-06-17 21:17:59 +00001886static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001887{
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001888 if (tx_skb->dma) {
Eric Dumazet73a37072009-06-17 21:17:59 +00001889 if (tx_skb->dma_single)
1890 pci_unmap_single(np->pci_dev, tx_skb->dma,
1891 tx_skb->dma_len,
1892 PCI_DMA_TODEVICE);
1893 else
1894 pci_unmap_page(np->pci_dev, tx_skb->dma,
1895 tx_skb->dma_len,
1896 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001897 tx_skb->dma = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001898 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001899}
1900
1901static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1902{
1903 nv_unmap_txskb(np, tx_skb);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001904 if (tx_skb->skb) {
1905 dev_kfree_skb_any(tx_skb->skb);
1906 tx_skb->skb = NULL;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001907 return 1;
Ayaz Abdullafa454592006-01-05 22:45:45 -08001908 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001909 return 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001910}
1911
Linus Torvalds1da177e2005-04-16 15:20:36 -07001912static void nv_drain_tx(struct net_device *dev)
1913{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001914 struct fe_priv *np = netdev_priv(dev);
1915 unsigned int i;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04001916
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001917 for (i = 0; i < np->tx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001918 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001919 np->tx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001920 np->tx_ring.orig[i].buf = 0;
1921 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001922 np->tx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001923 np->tx_ring.ex[i].txvlan = 0;
1924 np->tx_ring.ex[i].bufhigh = 0;
1925 np->tx_ring.ex[i].buflow = 0;
1926 }
Eric Dumazet73a37072009-06-17 21:17:59 +00001927 if (nv_release_txskb(np, &np->tx_skb[i]))
Jeff Garzik8148ff42007-10-16 20:56:09 -04001928 dev->stats.tx_dropped++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001929 np->tx_skb[i].dma = 0;
1930 np->tx_skb[i].dma_len = 0;
Eric Dumazet73a37072009-06-17 21:17:59 +00001931 np->tx_skb[i].dma_single = 0;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001932 np->tx_skb[i].first_tx_desc = NULL;
1933 np->tx_skb[i].next_tx_ctx = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001934 }
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05001935 np->tx_pkts_in_progress = 0;
1936 np->tx_change_owner = NULL;
1937 np->tx_end_flip = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001938}
1939
1940static void nv_drain_rx(struct net_device *dev)
1941{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04001942 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001943 int i;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001944
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04001945 for (i = 0; i < np->rx_ring_size; i++) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001946 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001947 np->rx_ring.orig[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001948 np->rx_ring.orig[i].buf = 0;
1949 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07001950 np->rx_ring.ex[i].flaglen = 0;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001951 np->rx_ring.ex[i].txvlan = 0;
1952 np->rx_ring.ex[i].bufhigh = 0;
1953 np->rx_ring.ex[i].buflow = 0;
1954 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001955 wmb();
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001956 if (np->rx_skb[i].skb) {
1957 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07001958 (skb_end_pointer(np->rx_skb[i].skb) -
1959 np->rx_skb[i].skb->data),
1960 PCI_DMA_FROMDEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001961 dev_kfree_skb(np->rx_skb[i].skb);
1962 np->rx_skb[i].skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001963 }
1964 }
1965}
1966
Jeff Garzik36b30ea2007-10-16 01:40:30 -04001967static void nv_drain_rxtx(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001968{
1969 nv_drain_tx(dev);
1970 nv_drain_rx(dev);
1971}
1972
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05001973static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1974{
1975 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1976}
1977
Ayaz Abdullaa4336862008-04-18 13:50:43 -07001978static void nv_legacybackoff_reseed(struct net_device *dev)
1979{
1980 u8 __iomem *base = get_hwbase(dev);
1981 u32 reg;
1982 u32 low;
1983 int tx_status = 0;
1984
1985 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1986 get_random_bytes(&low, sizeof(low));
1987 reg |= low & NVREG_SLOTTIME_MASK;
1988
1989 /* Need to stop tx before change takes effect.
1990 * Caller has already gained np->lock.
1991 */
1992 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1993 if (tx_status)
1994 nv_stop_tx(dev);
1995 nv_stop_rx(dev);
1996 writel(reg, base + NvRegSlotTime);
1997 if (tx_status)
1998 nv_start_tx(dev);
1999 nv_start_rx(dev);
2000}
2001
2002/* Gear Backoff Seeds */
2003#define BACKOFF_SEEDSET_ROWS 8
2004#define BACKOFF_SEEDSET_LFSRS 15
2005
2006/* Known Good seed sets */
2007static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002008 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2009 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2010 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2011 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2012 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2013 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2014 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2015 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002016
2017static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002018 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2019 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2020 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2021 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2022 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2023 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2024 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2025 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002026
2027static void nv_gear_backoff_reseed(struct net_device *dev)
2028{
2029 u8 __iomem *base = get_hwbase(dev);
2030 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2031 u32 temp, seedset, combinedSeed;
2032 int i;
2033
2034 /* Setup seed for free running LFSR */
2035 /* We are going to read the time stamp counter 3 times
2036 and swizzle bits around to increase randomness */
2037 get_random_bytes(&miniseed1, sizeof(miniseed1));
2038 miniseed1 &= 0x0fff;
2039 if (miniseed1 == 0)
2040 miniseed1 = 0xabc;
2041
2042 get_random_bytes(&miniseed2, sizeof(miniseed2));
2043 miniseed2 &= 0x0fff;
2044 if (miniseed2 == 0)
2045 miniseed2 = 0xabc;
2046 miniseed2_reversed =
2047 ((miniseed2 & 0xF00) >> 8) |
2048 (miniseed2 & 0x0F0) |
2049 ((miniseed2 & 0x00F) << 8);
2050
2051 get_random_bytes(&miniseed3, sizeof(miniseed3));
2052 miniseed3 &= 0x0fff;
2053 if (miniseed3 == 0)
2054 miniseed3 = 0xabc;
2055 miniseed3_reversed =
2056 ((miniseed3 & 0xF00) >> 8) |
2057 (miniseed3 & 0x0F0) |
2058 ((miniseed3 & 0x00F) << 8);
2059
2060 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2061 (miniseed2 ^ miniseed3_reversed);
2062
2063 /* Seeds can not be zero */
2064 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2065 combinedSeed |= 0x08;
2066 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2067 combinedSeed |= 0x8000;
2068
2069 /* No need to disable tx here */
2070 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2071 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2072 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002073 writel(temp, base + NvRegBackOffControl);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002074
Szymon Janc78aea4f2010-11-27 08:39:43 +00002075 /* Setup seeds for all gear LFSRs. */
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002076 get_random_bytes(&seedset, sizeof(seedset));
2077 seedset = seedset % BACKOFF_SEEDSET_ROWS;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002078 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002079 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2080 temp |= main_seedset[seedset][i-1] & 0x3ff;
2081 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2082 writel(temp, base + NvRegBackOffControl);
2083 }
2084}
2085
Linus Torvalds1da177e2005-04-16 15:20:36 -07002086/*
2087 * nv_start_xmit: dev->hard_start_xmit function
Herbert Xu932ff272006-06-09 12:20:56 -07002088 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002089 */
Stephen Hemminger613573252009-08-31 19:50:58 +00002090static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002091{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002092 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002093 u32 tx_flags = 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002094 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2095 unsigned int fragments = skb_shinfo(skb)->nr_frags;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002096 unsigned int i;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002097 u32 offset = 0;
2098 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002099 u32 size = skb_headlen(skb);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002100 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002101 u32 empty_slots;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002102 struct ring_desc *put_tx;
2103 struct ring_desc *start_tx;
2104 struct ring_desc *prev_tx;
2105 struct nv_skb_map *prev_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002106 unsigned long flags;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002107
2108 /* add fragments to entries count */
2109 for (i = 0; i < fragments; i++) {
2110 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2111 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2112 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002113
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002114 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002115 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002116 if (unlikely(empty_slots <= entries)) {
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002117 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002118 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002119 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002120 return NETDEV_TX_BUSY;
2121 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002122 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002123
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002124 start_tx = put_tx = np->put_tx.orig;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002125
Ayaz Abdullafa454592006-01-05 22:45:45 -08002126 /* setup the header buffer */
2127 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002128 prev_tx = put_tx;
2129 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002130 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002131 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
Ayaz Abdullafa454592006-01-05 22:45:45 -08002132 PCI_DMA_TODEVICE);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002133 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002134 np->put_tx_ctx->dma_single = 1;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002135 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2136 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002137
Ayaz Abdullafa454592006-01-05 22:45:45 -08002138 tx_flags = np->tx_flags;
2139 offset += bcnt;
2140 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002141 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002142 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002143 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002144 np->put_tx_ctx = np->first_tx_ctx;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002145 } while (size);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002146
2147 /* setup the fragments */
2148 for (i = 0; i < fragments; i++) {
2149 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2150 u32 size = frag->size;
2151 offset = 0;
2152
2153 do {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002154 prev_tx = put_tx;
2155 prev_tx_ctx = np->put_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002156 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002157 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2158 PCI_DMA_TODEVICE);
2159 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002160 np->put_tx_ctx->dma_single = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002161 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2162 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002163
Ayaz Abdullafa454592006-01-05 22:45:45 -08002164 offset += bcnt;
2165 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002166 if (unlikely(put_tx++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002167 put_tx = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002168 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002169 np->put_tx_ctx = np->first_tx_ctx;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002170 } while (size);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002171 }
2172
Ayaz Abdullafa454592006-01-05 22:45:45 -08002173 /* set last fragment flag */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002174 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
Ayaz Abdullafa454592006-01-05 22:45:45 -08002175
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002176 /* save skb in this slot's context area */
2177 prev_tx_ctx->skb = skb;
Ayaz Abdullafa454592006-01-05 22:45:45 -08002178
Herbert Xu89114af2006-07-08 13:34:32 -07002179 if (skb_is_gso(skb))
Herbert Xu79671682006-06-22 02:40:14 -07002180 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
Manfred Spraulee733622005-07-31 18:32:26 +02002181 else
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002182 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
Patrick McHardy84fa7932006-08-29 16:44:56 -07002183 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002184
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002185 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla164a86e2007-01-09 13:30:10 -05002186
Ayaz Abdullafa454592006-01-05 22:45:45 -08002187 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002188 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2189 np->put_tx.orig = put_tx;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002190
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002191 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002192
Joe Perches6b808582010-11-29 07:41:53 +00002193 netdev_dbg(dev, "%s: entries %d queued for transmission. tx_flags_extra: %x\n",
2194 __func__, entries, tx_flags_extra);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002195 {
2196 int j;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002197 for (j = 0; j < 64; j++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002198 if ((j%16) == 0)
2199 dprintk("\n%03x:", j);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002200 dprintk(" %02x", ((unsigned char *)skb->data)[j]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002201 }
2202 dprintk("\n");
2203 }
2204
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002205 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002206 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002207}
2208
Stephen Hemminger613573252009-08-31 19:50:58 +00002209static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2210 struct net_device *dev)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002211{
2212 struct fe_priv *np = netdev_priv(dev);
2213 u32 tx_flags = 0;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002214 u32 tx_flags_extra;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002215 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2216 unsigned int i;
2217 u32 offset = 0;
2218 u32 bcnt;
Eric Dumazete743d312010-04-14 15:59:40 -07002219 u32 size = skb_headlen(skb);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002220 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2221 u32 empty_slots;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002222 struct ring_desc_ex *put_tx;
2223 struct ring_desc_ex *start_tx;
2224 struct ring_desc_ex *prev_tx;
2225 struct nv_skb_map *prev_tx_ctx;
2226 struct nv_skb_map *start_tx_ctx;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002227 unsigned long flags;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002228
2229 /* add fragments to entries count */
2230 for (i = 0; i < fragments; i++) {
2231 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2232 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2233 }
2234
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002235 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002236 empty_slots = nv_get_empty_tx_slots(np);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002237 if (unlikely(empty_slots <= entries)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002238 netif_stop_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002239 np->tx_stop = 1;
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002240 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002241 return NETDEV_TX_BUSY;
2242 }
Ayaz Abdulla001eb842009-01-09 11:03:44 +00002243 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002244
2245 start_tx = put_tx = np->put_tx.ex;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002246 start_tx_ctx = np->put_tx_ctx;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002247
2248 /* setup the header buffer */
2249 do {
2250 prev_tx = put_tx;
2251 prev_tx_ctx = np->put_tx_ctx;
2252 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2253 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2254 PCI_DMA_TODEVICE);
2255 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002256 np->put_tx_ctx->dma_single = 1;
Al Viro5bb7ea22007-12-09 16:06:41 +00002257 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2258 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002259 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002260
2261 tx_flags = NV_TX2_VALID;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002262 offset += bcnt;
2263 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002264 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002265 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002266 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002267 np->put_tx_ctx = np->first_tx_ctx;
2268 } while (size);
2269
2270 /* setup the fragments */
2271 for (i = 0; i < fragments; i++) {
2272 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2273 u32 size = frag->size;
2274 offset = 0;
2275
2276 do {
2277 prev_tx = put_tx;
2278 prev_tx_ctx = np->put_tx_ctx;
2279 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2280 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2281 PCI_DMA_TODEVICE);
2282 np->put_tx_ctx->dma_len = bcnt;
Eric Dumazet73a37072009-06-17 21:17:59 +00002283 np->put_tx_ctx->dma_single = 0;
Al Viro5bb7ea22007-12-09 16:06:41 +00002284 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2285 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002286 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002287
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002288 offset += bcnt;
2289 size -= bcnt;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002290 if (unlikely(put_tx++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002291 put_tx = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002292 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002293 np->put_tx_ctx = np->first_tx_ctx;
2294 } while (size);
2295 }
2296
2297 /* set last fragment flag */
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002298 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002299
2300 /* save skb in this slot's context area */
2301 prev_tx_ctx->skb = skb;
2302
2303 if (skb_is_gso(skb))
2304 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2305 else
2306 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2307 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2308
2309 /* vlan tag */
Jesse Grosseab6d182010-10-20 13:56:03 +00002310 if (vlan_tx_tag_present(skb))
2311 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2312 vlan_tx_tag_get(skb));
2313 else
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002314 start_tx->txvlan = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002315
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002316 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002317
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002318 if (np->tx_limit) {
2319 /* Limit the number of outstanding tx. Setup all fragments, but
2320 * do not set the VALID bit on the first descriptor. Save a pointer
2321 * to that descriptor and also for next skb_map element.
2322 */
2323
2324 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2325 if (!np->tx_change_owner)
2326 np->tx_change_owner = start_tx_ctx;
2327
2328 /* remove VALID bit */
2329 tx_flags &= ~NV_TX2_VALID;
2330 start_tx_ctx->first_tx_desc = start_tx;
2331 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2332 np->tx_end_flip = np->put_tx_ctx;
2333 } else {
2334 np->tx_pkts_in_progress++;
2335 }
2336 }
2337
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002338 /* set tx flags */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002339 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2340 np->put_tx.ex = put_tx;
2341
Ingo Molnarbd6ca632008-03-28 14:41:30 -07002342 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002343
Joe Perches6b808582010-11-29 07:41:53 +00002344 netdev_dbg(dev, "%s: entries %d queued for transmission. tx_flags_extra: %x\n",
2345 __func__, entries, tx_flags_extra);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002346 {
2347 int j;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002348 for (j = 0; j < 64; j++) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002349 if ((j%16) == 0)
2350 dprintk("\n%03x:", j);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002351 dprintk(" %02x", ((unsigned char *)skb->data)[j]);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002352 }
2353 dprintk("\n");
2354 }
2355
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002356 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002357 return NETDEV_TX_OK;
2358}
2359
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002360static inline void nv_tx_flip_ownership(struct net_device *dev)
2361{
2362 struct fe_priv *np = netdev_priv(dev);
2363
2364 np->tx_pkts_in_progress--;
2365 if (np->tx_change_owner) {
Al Viro30ecce92008-03-26 05:57:12 +00002366 np->tx_change_owner->first_tx_desc->flaglen |=
2367 cpu_to_le32(NV_TX2_VALID);
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002368 np->tx_pkts_in_progress++;
2369
2370 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2371 if (np->tx_change_owner == np->tx_end_flip)
2372 np->tx_change_owner = NULL;
2373
2374 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2375 }
2376}
2377
Linus Torvalds1da177e2005-04-16 15:20:36 -07002378/*
2379 * nv_tx_done: check for completed packets, release the skbs.
2380 *
2381 * Caller must own np->lock.
2382 */
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002383static int nv_tx_done(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002384{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002385 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002386 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002387 int tx_work = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002388 struct ring_desc *orig_get_tx = np->get_tx.orig;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002389
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002390 while ((np->get_tx.orig != np->put_tx.orig) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002391 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2392 (tx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002393
Joe Perches6b808582010-11-29 07:41:53 +00002394 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002395
Eric Dumazet73a37072009-06-17 21:17:59 +00002396 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002397
Linus Torvalds1da177e2005-04-16 15:20:36 -07002398 if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002399 if (flags & NV_TX_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002400 if (flags & NV_TX_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002401 if (flags & NV_TX_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002402 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002403 if (flags & NV_TX_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002404 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002405 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2406 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002407 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002408 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002409 dev->stats.tx_packets++;
2410 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002411 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002412 dev_kfree_skb_any(np->get_tx_ctx->skb);
2413 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002414 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002415 }
2416 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002417 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002418 if (flags & NV_TX2_ERROR) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002419 if (flags & NV_TX2_UNDERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002420 dev->stats.tx_fifo_errors++;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002421 if (flags & NV_TX2_CARRIERLOST)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002422 dev->stats.tx_carrier_errors++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002423 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2424 nv_legacybackoff_reseed(dev);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002425 dev->stats.tx_errors++;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002426 } else {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002427 dev->stats.tx_packets++;
2428 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002429 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002430 dev_kfree_skb_any(np->get_tx_ctx->skb);
2431 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002432 tx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002433 }
2434 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002435 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002436 np->get_tx.orig = np->first_tx.orig;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002437 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002438 np->get_tx_ctx = np->first_tx_ctx;
2439 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002440 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002441 np->tx_stop = 0;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002442 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002443 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002444 return tx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002445}
2446
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002447static int nv_tx_done_optimized(struct net_device *dev, int limit)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002448{
2449 struct fe_priv *np = netdev_priv(dev);
2450 u32 flags;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002451 int tx_work = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00002452 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002453
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002454 while ((np->get_tx.ex != np->put_tx.ex) &&
Julia Lawall217d32d2010-07-05 22:15:47 -07002455 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002456 (tx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002457
Joe Perches6b808582010-11-29 07:41:53 +00002458 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002459
Eric Dumazet73a37072009-06-17 21:17:59 +00002460 nv_unmap_txskb(np, np->get_tx_ctx);
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002461
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002462 if (flags & NV_TX2_LASTPACKET) {
Ayaz Abdulla21828162007-01-23 12:27:21 -05002463 if (!(flags & NV_TX2_ERROR))
Jeff Garzik8148ff42007-10-16 20:56:09 -04002464 dev->stats.tx_packets++;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07002465 else {
2466 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2467 if (np->driver_data & DEV_HAS_GEAR_MODE)
2468 nv_gear_backoff_reseed(dev);
2469 else
2470 nv_legacybackoff_reseed(dev);
2471 }
2472 }
2473
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002474 dev_kfree_skb_any(np->get_tx_ctx->skb);
2475 np->get_tx_ctx->skb = NULL;
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002476 tx_work++;
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002477
Szymon Janc78aea4f2010-11-27 08:39:43 +00002478 if (np->tx_limit)
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05002479 nv_tx_flip_ownership(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002480 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002481 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002482 np->get_tx.ex = np->first_tx.ex;
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002483 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002484 np->get_tx_ctx = np->first_tx_ctx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002485 }
Ayaz Abdulla445583b2007-01-21 18:10:47 -05002486 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002487 np->tx_stop = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002488 netif_wake_queue(dev);
Ayaz Abdullaaaa37d22007-01-21 18:10:42 -05002489 }
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002490 return tx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002491}
2492
2493/*
2494 * nv_tx_timeout: dev->tx_timeout function
Herbert Xu932ff272006-06-09 12:20:56 -07002495 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002496 */
2497static void nv_tx_timeout(struct net_device *dev)
2498{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002499 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002500 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002501 u32 status;
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002502 union ring_type put_tx;
2503 int saved_tx_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002504
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05002505 if (np->msi_flags & NV_MSI_X_ENABLED)
2506 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2507 else
2508 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2509
2510 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002511
Manfred Spraulc2dba062005-07-31 18:29:47 +02002512 {
2513 int i;
2514
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002515 printk(KERN_INFO "%s: Ring at %lx\n",
2516 dev->name, (unsigned long)np->ring_addr);
Manfred Spraulc2dba062005-07-31 18:29:47 +02002517 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002518 for (i = 0; i <= np->register_size; i += 32) {
Manfred Spraulc2dba062005-07-31 18:29:47 +02002519 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2520 i,
2521 readl(base + i + 0), readl(base + i + 4),
2522 readl(base + i + 8), readl(base + i + 12),
2523 readl(base + i + 16), readl(base + i + 20),
2524 readl(base + i + 24), readl(base + i + 28));
2525 }
2526 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002527 for (i = 0; i < np->tx_ring_size; i += 4) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002528 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02002529 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002530 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002531 le32_to_cpu(np->tx_ring.orig[i].buf),
2532 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2533 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2534 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2535 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2536 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2537 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2538 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002539 } else {
2540 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
Jeff Garzikf3b197a2006-05-26 21:39:03 -04002541 i,
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002542 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2543 le32_to_cpu(np->tx_ring.ex[i].buflow),
2544 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2545 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2546 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2547 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2548 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2549 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2550 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2551 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2552 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2553 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
Manfred Spraulee733622005-07-31 18:32:26 +02002554 }
Manfred Spraulc2dba062005-07-31 18:29:47 +02002555 }
2556 }
2557
Linus Torvalds1da177e2005-04-16 15:20:36 -07002558 spin_lock_irq(&np->lock);
2559
2560 /* 1) stop tx engine */
2561 nv_stop_tx(dev);
2562
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002563 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2564 saved_tx_limit = np->tx_limit;
2565 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2566 np->tx_stop = 0; /* prevent waking tx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002567 if (!nv_optimized(np))
Ayaz Abdulla33912e72009-03-05 08:02:10 +00002568 nv_tx_done(dev, np->tx_ring_size);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002569 else
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05002570 nv_tx_done_optimized(dev, np->tx_ring_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002571
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002572 /* save current HW postion */
2573 if (np->tx_change_owner)
2574 put_tx.ex = np->tx_change_owner->first_tx_desc;
2575 else
2576 put_tx = np->put_tx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002577
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002578 /* 3) clear all tx state */
2579 nv_drain_tx(dev);
2580 nv_init_tx(dev);
Ayaz Abdulla3ba4d092007-03-23 05:50:02 -05002581
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002582 /* 4) restore state to current HW position */
2583 np->get_tx = np->put_tx = put_tx;
2584 np->tx_limit = saved_tx_limit;
2585
2586 /* 5) restart tx engine */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002587 nv_start_tx(dev);
Ayaz Abdulla8f955d72009-04-25 09:17:56 +00002588 netif_wake_queue(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002589 spin_unlock_irq(&np->lock);
2590}
2591
Manfred Spraul22c6d142005-04-19 21:17:09 +02002592/*
2593 * Called when the nic notices a mismatch between the actual data len on the
2594 * wire and the len indicated in the 802 header
2595 */
2596static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2597{
2598 int hdrlen; /* length of the 802 header */
2599 int protolen; /* length as stored in the proto field */
2600
2601 /* 1) calculate len according to header */
Szymon Janc78aea4f2010-11-27 08:39:43 +00002602 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2603 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002604 hdrlen = VLAN_HLEN;
2605 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002606 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002607 hdrlen = ETH_HLEN;
2608 }
Joe Perches6b808582010-11-29 07:41:53 +00002609 netdev_dbg(dev, "%s: datalen %d, protolen %d, hdrlen %d\n",
2610 __func__, datalen, protolen, hdrlen);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002611 if (protolen > ETH_DATA_LEN)
2612 return datalen; /* Value in proto field not a len, no checks possible */
2613
2614 protolen += hdrlen;
2615 /* consistency checks: */
2616 if (datalen > ETH_ZLEN) {
2617 if (datalen >= protolen) {
2618 /* more data on wire than in 802 header, trim of
2619 * additional data.
2620 */
Joe Perches6b808582010-11-29 07:41:53 +00002621 netdev_dbg(dev, "%s: accepting %d bytes\n",
2622 __func__, protolen);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002623 return protolen;
2624 } else {
2625 /* less data on wire than mentioned in header.
2626 * Discard the packet.
2627 */
Joe Perches6b808582010-11-29 07:41:53 +00002628 netdev_dbg(dev, "%s: discarding long packet\n",
2629 __func__);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002630 return -1;
2631 }
2632 } else {
2633 /* short packet. Accept only if 802 values are also short */
2634 if (protolen > ETH_ZLEN) {
Joe Perches6b808582010-11-29 07:41:53 +00002635 netdev_dbg(dev, "%s: discarding short packet\n",
2636 __func__);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002637 return -1;
2638 }
Joe Perches6b808582010-11-29 07:41:53 +00002639 netdev_dbg(dev, "%s: accepting %d bytes\n", __func__, datalen);
Manfred Spraul22c6d142005-04-19 21:17:09 +02002640 return datalen;
2641 }
2642}
2643
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002644static int nv_rx_process(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002645{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002646 struct fe_priv *np = netdev_priv(dev);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002647 u32 flags;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002648 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002649 struct sk_buff *skb;
2650 int len;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05002651
Szymon Janc78aea4f2010-11-27 08:39:43 +00002652 while ((np->get_rx.orig != np->put_rx.orig) &&
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002653 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002654 (rx_work < limit)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002655
Joe Perches6b808582010-11-29 07:41:53 +00002656 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002657
Linus Torvalds1da177e2005-04-16 15:20:36 -07002658 /*
2659 * the packet is for us - immediately tear down the pci mapping.
2660 * TODO: check if a prefetch of the first cacheline improves
2661 * the performance.
2662 */
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002663 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2664 np->get_rx_ctx->dma_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002665 PCI_DMA_FROMDEVICE);
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002666 skb = np->get_rx_ctx->skb;
2667 np->get_rx_ctx->skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002668
2669 {
2670 int j;
Joe Perches6b808582010-11-29 07:41:53 +00002671 netdev_dbg(dev, "Dumping packet (flags 0x%x)\n", flags);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002672 for (j = 0; j < 64; j++) {
Joe Perches6b808582010-11-29 07:41:53 +00002673 if ((j%16) == 0 && j)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002674 dprintk("\n%03x:", j);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002675 dprintk(" %02x", ((unsigned char *)skb->data)[j]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002676 }
2677 dprintk("\n");
2678 }
2679 /* look at what we actually got: */
2680 if (np->desc_ver == DESC_VER_1) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002681 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2682 len = flags & LEN_MASK_V1;
2683 if (unlikely(flags & NV_RX_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002684 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002685 len = nv_getlen(dev, skb->data, len);
2686 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002687 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002688 dev_kfree_skb(skb);
2689 goto next_pkt;
2690 }
2691 }
2692 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002693 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002694 if (flags & NV_RX_SUBSTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002695 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002696 }
2697 /* the rest are hard errors */
2698 else {
2699 if (flags & NV_RX_MISSEDFRAME)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002700 dev->stats.rx_missed_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002701 if (flags & NV_RX_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002702 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002703 if (flags & NV_RX_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002704 dev->stats.rx_over_errors++;
2705 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002706 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002707 goto next_pkt;
2708 }
2709 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002710 } else {
2711 dev_kfree_skb(skb);
2712 goto next_pkt;
Manfred Spraul22c6d142005-04-19 21:17:09 +02002713 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002714 } else {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002715 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2716 len = flags & LEN_MASK_V2;
2717 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002718 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002719 len = nv_getlen(dev, skb->data, len);
2720 if (len < 0) {
Jeff Garzik8148ff42007-10-16 20:56:09 -04002721 dev->stats.rx_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002722 dev_kfree_skb(skb);
2723 goto next_pkt;
2724 }
2725 }
2726 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002727 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002728 if (flags & NV_RX2_SUBSTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002729 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002730 }
2731 /* the rest are hard errors */
2732 else {
2733 if (flags & NV_RX2_CRCERR)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002734 dev->stats.rx_crc_errors++;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002735 if (flags & NV_RX2_OVERFLOW)
Jeff Garzik8148ff42007-10-16 20:56:09 -04002736 dev->stats.rx_over_errors++;
2737 dev->stats.rx_errors++;
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002738 dev_kfree_skb(skb);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05002739 goto next_pkt;
2740 }
2741 }
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002742 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2743 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla0d63fb32007-01-09 13:30:13 -05002744 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002745 } else {
2746 dev_kfree_skb(skb);
2747 goto next_pkt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002748 }
2749 }
2750 /* got a valid packet - forward it to the network core */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002751 skb_put(skb, len);
2752 skb->protocol = eth_type_trans(skb, dev);
Joe Perches6b808582010-11-29 07:41:53 +00002753 netdev_dbg(dev, "%s: %d bytes, proto %d accepted\n",
2754 __func__, len, skb->protocol);
Tom Herbert53f224c2010-05-03 19:08:45 +00002755 napi_gro_receive(&np->napi, skb);
Jeff Garzik8148ff42007-10-16 20:56:09 -04002756 dev->stats.rx_packets++;
2757 dev->stats.rx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002758next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002759 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002760 np->get_rx.orig = np->first_rx.orig;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002761 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002762 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002763
2764 rx_work++;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002765 }
2766
Ingo Molnarbcb5feb2007-10-16 20:44:59 -04002767 return rx_work;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002768}
2769
2770static int nv_rx_process_optimized(struct net_device *dev, int limit)
2771{
2772 struct fe_priv *np = netdev_priv(dev);
2773 u32 flags;
2774 u32 vlanflags = 0;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002775 int rx_work = 0;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002776 struct sk_buff *skb;
2777 int len;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002778
Szymon Janc78aea4f2010-11-27 08:39:43 +00002779 while ((np->get_rx.ex != np->put_rx.ex) &&
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002780 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
Ingo Molnarc1b71512007-10-17 12:18:23 +02002781 (rx_work < limit)) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002782
Joe Perches6b808582010-11-29 07:41:53 +00002783 netdev_dbg(dev, "%s: flags 0x%x\n", __func__, flags);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002784
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002785 /*
2786 * the packet is for us - immediately tear down the pci mapping.
2787 * TODO: check if a prefetch of the first cacheline improves
2788 * the performance.
2789 */
2790 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2791 np->get_rx_ctx->dma_len,
2792 PCI_DMA_FROMDEVICE);
2793 skb = np->get_rx_ctx->skb;
2794 np->get_rx_ctx->skb = NULL;
2795
2796 {
2797 int j;
Joe Perches6b808582010-11-29 07:41:53 +00002798 netdev_dbg(dev, "Dumping packet (flags 0x%x)\n", flags);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002799 for (j = 0; j < 64; j++) {
Joe Perches6b808582010-11-29 07:41:53 +00002800 if ((j%16) == 0 && j)
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002801 dprintk("\n%03x:", j);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002802 dprintk(" %02x", ((unsigned char *)skb->data)[j]);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002803 }
2804 dprintk("\n");
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002805 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002806 /* look at what we actually got: */
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002807 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2808 len = flags & LEN_MASK_V2;
2809 if (unlikely(flags & NV_RX2_ERROR)) {
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002810 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002811 len = nv_getlen(dev, skb->data, len);
2812 if (len < 0) {
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002813 dev_kfree_skb(skb);
2814 goto next_pkt;
2815 }
2816 }
2817 /* framing errors are soft errors */
Ayaz Abdulla1ef68412008-08-06 12:11:03 -04002818 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00002819 if (flags & NV_RX2_SUBSTRACT1)
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002820 len--;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002821 }
2822 /* the rest are hard errors */
2823 else {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002824 dev_kfree_skb(skb);
2825 goto next_pkt;
2826 }
2827 }
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002828
Ayaz Abdullabfaffe82008-01-13 16:02:55 -05002829 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2830 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002831 skb->ip_summed = CHECKSUM_UNNECESSARY;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002832
2833 /* got a valid packet - forward it to the network core */
2834 skb_put(skb, len);
2835 skb->protocol = eth_type_trans(skb, dev);
2836 prefetch(skb->data);
2837
Joe Perches6b808582010-11-29 07:41:53 +00002838 netdev_dbg(dev, "%s: %d bytes, proto %d accepted\n",
2839 __func__, len, skb->protocol);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002840
2841 if (likely(!np->vlangrp)) {
Tom Herbert53f224c2010-05-03 19:08:45 +00002842 napi_gro_receive(&np->napi, skb);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002843 } else {
2844 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2845 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
Tom Herbert53f224c2010-05-03 19:08:45 +00002846 vlan_gro_receive(&np->napi, np->vlangrp,
2847 vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002848 } else {
Tom Herbert53f224c2010-05-03 19:08:45 +00002849 napi_gro_receive(&np->napi, skb);
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002850 }
2851 }
2852
Jeff Garzik8148ff42007-10-16 20:56:09 -04002853 dev->stats.rx_packets++;
2854 dev->stats.rx_bytes += len;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002855 } else {
2856 dev_kfree_skb(skb);
2857 }
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002858next_pkt:
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002859 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05002860 np->get_rx.ex = np->first_rx.ex;
Ayaz Abdullab01867c2007-01-21 18:10:52 -05002861 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05002862 np->get_rx_ctx = np->first_rx_ctx;
Ingo Molnarc1b71512007-10-17 12:18:23 +02002863
2864 rx_work++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002865 }
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07002866
Ingo Molnarc1b71512007-10-17 12:18:23 +02002867 return rx_work;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002868}
2869
Manfred Sprauld81c0982005-07-31 18:20:30 +02002870static void set_bufsize(struct net_device *dev)
2871{
2872 struct fe_priv *np = netdev_priv(dev);
2873
2874 if (dev->mtu <= ETH_DATA_LEN)
2875 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2876 else
2877 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2878}
2879
Linus Torvalds1da177e2005-04-16 15:20:36 -07002880/*
2881 * nv_change_mtu: dev->change_mtu function
2882 * Called with dev_base_lock held for read.
2883 */
2884static int nv_change_mtu(struct net_device *dev, int new_mtu)
2885{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002886 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002887 int old_mtu;
2888
2889 if (new_mtu < 64 || new_mtu > np->pkt_limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002890 return -EINVAL;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002891
2892 old_mtu = dev->mtu;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002893 dev->mtu = new_mtu;
Manfred Sprauld81c0982005-07-31 18:20:30 +02002894
2895 /* return early if the buffer sizes will not change */
2896 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2897 return 0;
2898 if (old_mtu == new_mtu)
2899 return 0;
2900
2901 /* synchronized against open : rtnl_lock() held by caller */
2902 if (netif_running(dev)) {
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002903 u8 __iomem *base = get_hwbase(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002904 /*
2905 * It seems that the nic preloads valid ring entries into an
2906 * internal buffer. The procedure for flushing everything is
2907 * guessed, there is probably a simpler approach.
2908 * Changing the MTU is a rare event, it shouldn't matter.
2909 */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002910 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00002911 nv_napi_disable(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002912 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002913 netif_addr_lock(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002914 spin_lock(&np->lock);
2915 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002916 nv_stop_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002917 nv_txrx_reset(dev);
2918 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002919 nv_drain_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002920 /* reinit driver view of the rx queue */
Manfred Sprauld81c0982005-07-31 18:20:30 +02002921 set_bufsize(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04002922 if (nv_init_ring(dev)) {
Manfred Sprauld81c0982005-07-31 18:20:30 +02002923 if (!np->in_shutdown)
2924 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2925 }
2926 /* reinit nic view of the rx queue */
2927 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Ayaz Abdulla0832b252006-02-04 13:13:26 -05002928 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002929 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Manfred Sprauld81c0982005-07-31 18:20:30 +02002930 base + NvRegRingSizes);
2931 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04002932 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002933 pci_push(base);
2934
2935 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04002936 nv_start_rxtx(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002937 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002938 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002939 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00002940 nv_napi_enable(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07002941 nv_enable_irq(dev);
Manfred Sprauld81c0982005-07-31 18:20:30 +02002942 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002943 return 0;
2944}
2945
Manfred Spraul72b31782005-07-31 18:33:34 +02002946static void nv_copy_mac_to_hw(struct net_device *dev)
2947{
viro@ftp.linux.org.uk25097d42005-09-06 01:36:58 +01002948 u8 __iomem *base = get_hwbase(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002949 u32 mac[2];
2950
2951 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2952 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2953 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2954
2955 writel(mac[0], base + NvRegMacAddrA);
2956 writel(mac[1], base + NvRegMacAddrB);
2957}
2958
2959/*
2960 * nv_set_mac_address: dev->set_mac_address function
2961 * Called with rtnl_lock() held.
2962 */
2963static int nv_set_mac_address(struct net_device *dev, void *addr)
2964{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04002965 struct fe_priv *np = netdev_priv(dev);
Szymon Janc78aea4f2010-11-27 08:39:43 +00002966 struct sockaddr *macaddr = (struct sockaddr *)addr;
Manfred Spraul72b31782005-07-31 18:33:34 +02002967
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07002968 if (!is_valid_ether_addr(macaddr->sa_data))
Manfred Spraul72b31782005-07-31 18:33:34 +02002969 return -EADDRNOTAVAIL;
2970
2971 /* synchronized against open : rtnl_lock() held by caller */
2972 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2973
2974 if (netif_running(dev)) {
Herbert Xu932ff272006-06-09 12:20:56 -07002975 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07002976 netif_addr_lock(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002977 spin_lock_irq(&np->lock);
2978
2979 /* stop rx engine */
2980 nv_stop_rx(dev);
2981
2982 /* set mac address */
2983 nv_copy_mac_to_hw(dev);
2984
2985 /* restart rx engine */
2986 nv_start_rx(dev);
2987 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07002988 netif_addr_unlock(dev);
Herbert Xu932ff272006-06-09 12:20:56 -07002989 netif_tx_unlock_bh(dev);
Manfred Spraul72b31782005-07-31 18:33:34 +02002990 } else {
2991 nv_copy_mac_to_hw(dev);
2992 }
2993 return 0;
2994}
2995
Linus Torvalds1da177e2005-04-16 15:20:36 -07002996/*
2997 * nv_set_multicast: dev->set_multicast function
Herbert Xu932ff272006-06-09 12:20:56 -07002998 * Called with netif_tx_lock held.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002999 */
3000static void nv_set_multicast(struct net_device *dev)
3001{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003002 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003003 u8 __iomem *base = get_hwbase(dev);
3004 u32 addr[2];
3005 u32 mask[2];
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003006 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003007
3008 memset(addr, 0, sizeof(addr));
3009 memset(mask, 0, sizeof(mask));
3010
3011 if (dev->flags & IFF_PROMISC) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003012 pff |= NVREG_PFF_PROMISC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003013 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003014 pff |= NVREG_PFF_MYADDR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003015
Jiri Pirko48e2f182010-02-22 09:22:26 +00003016 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003017 u32 alwaysOff[2];
3018 u32 alwaysOn[2];
3019
3020 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3021 if (dev->flags & IFF_ALLMULTI) {
3022 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3023 } else {
Jiri Pirko22bedad2010-04-01 21:22:57 +00003024 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003025
Jiri Pirko22bedad2010-04-01 21:22:57 +00003026 netdev_for_each_mc_addr(ha, dev) {
3027 unsigned char *addr = ha->addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003028 u32 a, b;
Jiri Pirko22bedad2010-04-01 21:22:57 +00003029
3030 a = le32_to_cpu(*(__le32 *) addr);
3031 b = le16_to_cpu(*(__le16 *) (&addr[4]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07003032 alwaysOn[0] &= a;
3033 alwaysOff[0] &= ~a;
3034 alwaysOn[1] &= b;
3035 alwaysOff[1] &= ~b;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003036 }
3037 }
3038 addr[0] = alwaysOn[0];
3039 addr[1] = alwaysOn[1];
3040 mask[0] = alwaysOn[0] | alwaysOff[0];
3041 mask[1] = alwaysOn[1] | alwaysOff[1];
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05003042 } else {
3043 mask[0] = NVREG_MCASTMASKA_NONE;
3044 mask[1] = NVREG_MCASTMASKB_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003045 }
3046 }
3047 addr[0] |= NVREG_MCASTADDRA_FORCE;
3048 pff |= NVREG_PFF_ALWAYS;
3049 spin_lock_irq(&np->lock);
3050 nv_stop_rx(dev);
3051 writel(addr[0], base + NvRegMulticastAddrA);
3052 writel(addr[1], base + NvRegMulticastAddrB);
3053 writel(mask[0], base + NvRegMulticastMaskA);
3054 writel(mask[1], base + NvRegMulticastMaskB);
3055 writel(pff, base + NvRegPacketFilterFlags);
3056 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3057 dev->name);
3058 nv_start_rx(dev);
3059 spin_unlock_irq(&np->lock);
3060}
3061
Adrian Bunkc7985052006-06-22 12:03:29 +02003062static void nv_update_pause(struct net_device *dev, u32 pause_flags)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003063{
3064 struct fe_priv *np = netdev_priv(dev);
3065 u8 __iomem *base = get_hwbase(dev);
3066
3067 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3068
3069 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3070 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3071 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3072 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3073 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3074 } else {
3075 writel(pff, base + NvRegPacketFilterFlags);
3076 }
3077 }
3078 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3079 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3080 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003081 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3082 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3083 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003084 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003085 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
Ayaz Abdulla9a33e882008-08-06 12:12:34 -04003086 /* limit the number of tx pause frames to a default of 8 */
3087 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3088 }
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05003089 writel(pause_enable, base + NvRegTxPauseFrame);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003090 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3091 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3092 } else {
3093 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3094 writel(regmisc, base + NvRegMisc1);
3095 }
3096 }
3097}
3098
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003099/**
3100 * nv_update_linkspeed: Setup the MAC according to the link partner
3101 * @dev: Network device to be configured
3102 *
3103 * The function queries the PHY and checks if there is a link partner.
3104 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3105 * set to 10 MBit HD.
3106 *
3107 * The function returns 0 if there is no link partner and 1 if there is
3108 * a good link partner.
3109 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003110static int nv_update_linkspeed(struct net_device *dev)
3111{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003112 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003113 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003114 int adv = 0;
3115 int lpa = 0;
3116 int adv_lpa, adv_pause, lpa_pause;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003117 int newls = np->linkspeed;
3118 int newdup = np->duplex;
3119 int mii_status;
3120 int retval = 0;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003121 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003122 u32 txrxFlags = 0;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003123 u32 phy_exp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003124
3125 /* BMSR_LSTATUS is latched, read it twice:
3126 * we want the current value.
3127 */
3128 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3129 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3130
3131 if (!(mii_status & BMSR_LSTATUS)) {
Joe Perches6b808582010-11-29 07:41:53 +00003132 netdev_dbg(dev,
3133 "no link detected by phy - falling back to 10HD\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003134 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3135 newdup = 0;
3136 retval = 0;
3137 goto set_speed;
3138 }
3139
3140 if (np->autoneg == 0) {
Joe Perches6b808582010-11-29 07:41:53 +00003141 netdev_dbg(dev, "%s: autoneg off, PHY set to 0x%04x\n",
3142 __func__, np->fixed_mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003143 if (np->fixed_mode & LPA_100FULL) {
3144 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3145 newdup = 1;
3146 } else if (np->fixed_mode & LPA_100HALF) {
3147 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3148 newdup = 0;
3149 } else if (np->fixed_mode & LPA_10FULL) {
3150 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3151 newdup = 1;
3152 } else {
3153 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3154 newdup = 0;
3155 }
3156 retval = 1;
3157 goto set_speed;
3158 }
3159 /* check auto negotiation is complete */
3160 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3161 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3162 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3163 newdup = 0;
3164 retval = 0;
Joe Perches6b808582010-11-29 07:41:53 +00003165 netdev_dbg(dev,
3166 "autoneg not completed - falling back to 10HD\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003167 goto set_speed;
3168 }
3169
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003170 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3171 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
Joe Perches6b808582010-11-29 07:41:53 +00003172 netdev_dbg(dev, "%s: PHY advertises 0x%04x, lpa 0x%04x\n",
3173 __func__, adv, lpa);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003174
Linus Torvalds1da177e2005-04-16 15:20:36 -07003175 retval = 1;
3176 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003177 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3178 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003179
3180 if ((control_1000 & ADVERTISE_1000FULL) &&
3181 (status_1000 & LPA_1000FULL)) {
Joe Perches6b808582010-11-29 07:41:53 +00003182 netdev_dbg(dev, "%s: GBit ethernet detected\n",
3183 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003184 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3185 newdup = 1;
3186 goto set_speed;
3187 }
3188 }
3189
Linus Torvalds1da177e2005-04-16 15:20:36 -07003190 /* FIXME: handle parallel detection properly */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003191 adv_lpa = lpa & adv;
3192 if (adv_lpa & LPA_100FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003193 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3194 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003195 } else if (adv_lpa & LPA_100HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003196 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3197 newdup = 0;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003198 } else if (adv_lpa & LPA_10FULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003199 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3200 newdup = 1;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003201 } else if (adv_lpa & LPA_10HALF) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003202 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3203 newdup = 0;
3204 } else {
Joe Perches6b808582010-11-29 07:41:53 +00003205 netdev_dbg(dev, "bad ability %04x - falling back to 10HD\n",
3206 adv_lpa);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003207 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3208 newdup = 0;
3209 }
3210
3211set_speed:
3212 if (np->duplex == newdup && np->linkspeed == newls)
3213 return retval;
3214
3215 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3216 dev->name, np->linkspeed, np->duplex, newls, newdup);
3217
3218 np->duplex = newdup;
3219 np->linkspeed = newls;
3220
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003221 /* The transmitter and receiver must be restarted for safe update */
3222 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3223 txrxFlags |= NV_RESTART_TX;
3224 nv_stop_tx(dev);
3225 }
3226 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3227 txrxFlags |= NV_RESTART_RX;
3228 nv_stop_rx(dev);
3229 }
3230
Linus Torvalds1da177e2005-04-16 15:20:36 -07003231 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003232 phyreg = readl(base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003233 phyreg &= ~(0x3FF00);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003234 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3235 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3236 phyreg |= NVREG_SLOTTIME_10_100_FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003237 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
Ayaz Abdullaa4336862008-04-18 13:50:43 -07003238 phyreg |= NVREG_SLOTTIME_1000_FULL;
3239 writel(phyreg, base + NvRegSlotTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003240 }
3241
3242 phyreg = readl(base + NvRegPhyInterface);
3243 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3244 if (np->duplex == 0)
3245 phyreg |= PHY_HALF;
3246 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3247 phyreg |= PHY_100;
3248 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3249 phyreg |= PHY_1000;
3250 writel(phyreg, base + NvRegPhyInterface);
3251
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003252 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003253 if (phyreg & PHY_RGMII) {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003254 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003255 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003256 } else {
3257 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3258 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3259 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3260 else
3261 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3262 } else {
3263 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3264 }
3265 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003266 } else {
Ayaz Abdullafd9b5582008-02-05 12:29:49 -05003267 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3268 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3269 else
3270 txreg = NVREG_TX_DEFERRAL_DEFAULT;
Ayaz Abdulla9744e212006-07-06 16:45:58 -04003271 }
3272 writel(txreg, base + NvRegTxDeferral);
3273
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04003274 if (np->desc_ver == DESC_VER_1) {
3275 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3276 } else {
3277 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3278 txreg = NVREG_TX_WM_DESC2_3_1000;
3279 else
3280 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3281 }
3282 writel(txreg, base + NvRegTxWatermark);
3283
Szymon Janc78aea4f2010-11-27 08:39:43 +00003284 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
Linus Torvalds1da177e2005-04-16 15:20:36 -07003285 base + NvRegMisc1);
3286 pci_push(base);
3287 writel(np->linkspeed, base + NvRegLinkSpeed);
3288 pci_push(base);
3289
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003290 pause_flags = 0;
3291 /* setup pause frame */
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003292 if (np->duplex != 0) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003293 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003294 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3295 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003296
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003297 switch (adv_pause) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003298 case ADVERTISE_PAUSE_CAP:
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003299 if (lpa_pause & LPA_PAUSE_CAP) {
3300 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3301 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3302 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3303 }
3304 break;
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07003305 case ADVERTISE_PAUSE_ASYM:
Szymon Janc78aea4f2010-11-27 08:39:43 +00003306 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003307 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003308 break;
Szymon Janc78aea4f2010-11-27 08:39:43 +00003309 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3310 if (lpa_pause & LPA_PAUSE_CAP) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003311 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3312 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3313 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3314 }
3315 if (lpa_pause == LPA_PAUSE_ASYM)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003316 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003317 break;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003318 }
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003319 } else {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003320 pause_flags = np->pause_flags;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003321 }
3322 }
Ayaz Abdullab6d07732006-06-10 22:47:42 -04003323 nv_update_pause(dev, pause_flags);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04003324
Ayaz Abdullab2976d22008-02-04 15:13:59 -05003325 if (txrxFlags & NV_RESTART_TX)
3326 nv_start_tx(dev);
3327 if (txrxFlags & NV_RESTART_RX)
3328 nv_start_rx(dev);
3329
Linus Torvalds1da177e2005-04-16 15:20:36 -07003330 return retval;
3331}
3332
3333static void nv_linkchange(struct net_device *dev)
3334{
3335 if (nv_update_linkspeed(dev)) {
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003336 if (!netif_carrier_ok(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003337 netif_carrier_on(dev);
3338 printk(KERN_INFO "%s: link up.\n", dev->name);
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003339 nv_txrx_gate(dev, false);
Ayaz Abdulla4ea7f292005-11-11 08:29:59 -05003340 nv_start_rx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003341 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003342 } else {
3343 if (netif_carrier_ok(dev)) {
3344 netif_carrier_off(dev);
3345 printk(KERN_INFO "%s: link down.\n", dev->name);
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00003346 nv_txrx_gate(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003347 nv_stop_rx(dev);
3348 }
3349 }
3350}
3351
3352static void nv_link_irq(struct net_device *dev)
3353{
3354 u8 __iomem *base = get_hwbase(dev);
3355 u32 miistat;
3356
3357 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05003358 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003359 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3360
3361 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3362 nv_linkchange(dev);
Joe Perches6b808582010-11-29 07:41:53 +00003363 netdev_dbg(dev, "link change notification done\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003364}
3365
Ayaz Abdulla4db0ee12008-06-09 16:51:06 -07003366static void nv_msi_workaround(struct fe_priv *np)
3367{
3368
3369 /* Need to toggle the msi irq mask within the ethernet device,
3370 * otherwise, future interrupts will not be detected.
3371 */
3372 if (np->msi_flags & NV_MSI_ENABLED) {
3373 u8 __iomem *base = np->base;
3374
3375 writel(0, base + NvRegMSIIrqMask);
3376 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3377 }
3378}
3379
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003380static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3381{
3382 struct fe_priv *np = netdev_priv(dev);
3383
3384 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3385 if (total_work > NV_DYNAMIC_THRESHOLD) {
3386 /* transition to poll based interrupts */
3387 np->quiet_count = 0;
3388 if (np->irqmask != NVREG_IRQMASK_CPU) {
3389 np->irqmask = NVREG_IRQMASK_CPU;
3390 return 1;
3391 }
3392 } else {
3393 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3394 np->quiet_count++;
3395 } else {
3396 /* reached a period of low activity, switch
3397 to per tx/rx packet interrupts */
3398 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3399 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3400 return 1;
3401 }
3402 }
3403 }
3404 }
3405 return 0;
3406}
3407
David Howells7d12e782006-10-05 14:55:46 +01003408static irqreturn_t nv_nic_irq(int foo, void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003409{
3410 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003411 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003412 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003413
Joe Perches6b808582010-11-29 07:41:53 +00003414 netdev_dbg(dev, "%s\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003415
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003416 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3417 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003418 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003419 } else {
3420 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003421 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003422 }
Joe Perches6b808582010-11-29 07:41:53 +00003423 netdev_dbg(dev, "irq: %08x\n", np->events);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003424 if (!(np->events & np->irqmask))
3425 return IRQ_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003426
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003427 nv_msi_workaround(np);
Ayaz Abdulla4db0ee12008-06-09 16:51:06 -07003428
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003429 if (napi_schedule_prep(&np->napi)) {
3430 /*
3431 * Disable further irq's (msix not enabled with napi)
3432 */
3433 writel(0, base + NvRegIrqMask);
3434 __napi_schedule(&np->napi);
3435 }
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003436
Joe Perches6b808582010-11-29 07:41:53 +00003437 netdev_dbg(dev, "%s: completed\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003438
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003439 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003440}
3441
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003442/**
3443 * All _optimized functions are used to help increase performance
3444 * (reduce CPU and increase throughput). They use descripter version 3,
3445 * compiler directives, and reduce memory accesses.
3446 */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003447static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3448{
3449 struct net_device *dev = (struct net_device *) data;
3450 struct fe_priv *np = netdev_priv(dev);
3451 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003452
Joe Perches6b808582010-11-29 07:41:53 +00003453 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003454
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003455 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3456 np->events = readl(base + NvRegIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003457 writel(np->events, base + NvRegIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003458 } else {
3459 np->events = readl(base + NvRegMSIXIrqStatus);
Ayaz Abdulla1b2bb762009-03-05 08:02:34 +00003460 writel(np->events, base + NvRegMSIXIrqStatus);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003461 }
Joe Perches6b808582010-11-29 07:41:53 +00003462 netdev_dbg(dev, "irq: %08x\n", np->events);
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003463 if (!(np->events & np->irqmask))
3464 return IRQ_NONE;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003465
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003466 nv_msi_workaround(np);
Ayaz Abdulla4db0ee12008-06-09 16:51:06 -07003467
Eric Dumazet78c29bd2009-07-02 04:04:45 +00003468 if (napi_schedule_prep(&np->napi)) {
3469 /*
3470 * Disable further irq's (msix not enabled with napi)
3471 */
3472 writel(0, base + NvRegIrqMask);
3473 __napi_schedule(&np->napi);
3474 }
Joe Perches6b808582010-11-29 07:41:53 +00003475 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003476
Ayaz Abdullab67874a2009-03-05 08:02:22 +00003477 return IRQ_HANDLED;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003478}
3479
David Howells7d12e782006-10-05 14:55:46 +01003480static irqreturn_t nv_nic_irq_tx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003481{
3482 struct net_device *dev = (struct net_device *) data;
3483 struct fe_priv *np = netdev_priv(dev);
3484 u8 __iomem *base = get_hwbase(dev);
3485 u32 events;
3486 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003487 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003488
Joe Perches6b808582010-11-29 07:41:53 +00003489 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003490
Szymon Janc78aea4f2010-11-27 08:39:43 +00003491 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003492 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3493 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
Joe Perches6b808582010-11-29 07:41:53 +00003494 netdev_dbg(dev, "tx irq: %08x\n", events);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003495 if (!(events & np->irqmask))
3496 break;
3497
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003498 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003499 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003500 spin_unlock_irqrestore(&np->lock, flags);
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003501
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003502 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003503 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003504 /* disable interrupts on the nic */
3505 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3506 pci_push(base);
3507
3508 if (!np->in_shutdown) {
3509 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3510 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3511 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003512 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003513 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003514 break;
3515 }
3516
3517 }
Joe Perches6b808582010-11-29 07:41:53 +00003518 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003519
3520 return IRQ_RETVAL(i);
3521}
3522
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003523static int nv_napi_poll(struct napi_struct *napi, int budget)
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003524{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003525 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3526 struct net_device *dev = np->dev;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003527 u8 __iomem *base = get_hwbase(dev);
Francois Romieud15e9c42006-12-17 23:03:15 +01003528 unsigned long flags;
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003529 int retcode;
Szymon Janc78aea4f2010-11-27 08:39:43 +00003530 int rx_count, tx_work = 0, rx_work = 0;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003531
stephen hemminger81a2e362010-04-28 08:25:28 +00003532 do {
3533 if (!nv_optimized(np)) {
3534 spin_lock_irqsave(&np->lock, flags);
3535 tx_work += nv_tx_done(dev, np->tx_ring_size);
3536 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003537
Tom Herbertd951f722010-05-05 18:15:21 +00003538 rx_count = nv_rx_process(dev, budget - rx_work);
stephen hemminger81a2e362010-04-28 08:25:28 +00003539 retcode = nv_alloc_rx(dev);
3540 } else {
3541 spin_lock_irqsave(&np->lock, flags);
3542 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3543 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003544
Tom Herbertd951f722010-05-05 18:15:21 +00003545 rx_count = nv_rx_process_optimized(dev,
3546 budget - rx_work);
stephen hemminger81a2e362010-04-28 08:25:28 +00003547 retcode = nv_alloc_rx_optimized(dev);
3548 }
3549 } while (retcode == 0 &&
3550 rx_count > 0 && (rx_work += rx_count) < budget);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003551
Ayaz Abdullae0379a12007-02-20 03:34:30 -05003552 if (retcode) {
Francois Romieud15e9c42006-12-17 23:03:15 +01003553 spin_lock_irqsave(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003554 if (!np->in_shutdown)
3555 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Francois Romieud15e9c42006-12-17 23:03:15 +01003556 spin_unlock_irqrestore(&np->lock, flags);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003557 }
3558
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003559 nv_change_interrupt_mode(dev, tx_work + rx_work);
3560
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003561 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3562 spin_lock_irqsave(&np->lock, flags);
3563 nv_link_irq(dev);
3564 spin_unlock_irqrestore(&np->lock, flags);
3565 }
3566 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3567 spin_lock_irqsave(&np->lock, flags);
3568 nv_linkchange(dev);
3569 spin_unlock_irqrestore(&np->lock, flags);
3570 np->link_timeout = jiffies + LINK_TIMEOUT;
3571 }
3572 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3573 spin_lock_irqsave(&np->lock, flags);
3574 if (!np->in_shutdown) {
3575 np->nic_poll_irq = np->irqmask;
3576 np->recover_error = 1;
3577 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3578 }
3579 spin_unlock_irqrestore(&np->lock, flags);
David S. Miller6c2da9c2009-04-09 01:09:33 -07003580 napi_complete(napi);
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003581 return rx_work;
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003582 }
3583
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003584 if (rx_work < budget) {
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003585 /* re-enable interrupts
3586 (msix not enabled in napi) */
David S. Miller6c2da9c2009-04-09 01:09:33 -07003587 napi_complete(napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003588
Ayaz Abdullaf27e6f32009-03-05 08:02:14 +00003589 writel(np->irqmask, base + NvRegIrqMask);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003590 }
Ayaz Abdulla4145ade2009-03-05 08:02:26 +00003591 return rx_work;
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003592}
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07003593
David Howells7d12e782006-10-05 14:55:46 +01003594static irqreturn_t nv_nic_irq_rx(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003595{
3596 struct net_device *dev = (struct net_device *) data;
3597 struct fe_priv *np = netdev_priv(dev);
3598 u8 __iomem *base = get_hwbase(dev);
3599 u32 events;
3600 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003601 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003602
Joe Perches6b808582010-11-29 07:41:53 +00003603 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003604
Szymon Janc78aea4f2010-11-27 08:39:43 +00003605 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003606 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3607 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
Joe Perches6b808582010-11-29 07:41:53 +00003608 netdev_dbg(dev, "rx irq: %08x\n", events);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003609 if (!(events & np->irqmask))
3610 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003611
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003612 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003613 if (unlikely(nv_alloc_rx_optimized(dev))) {
3614 spin_lock_irqsave(&np->lock, flags);
3615 if (!np->in_shutdown)
3616 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3617 spin_unlock_irqrestore(&np->lock, flags);
3618 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003619 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003620
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003621 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003622 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003623 /* disable interrupts on the nic */
3624 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3625 pci_push(base);
3626
3627 if (!np->in_shutdown) {
3628 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3629 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3630 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003631 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003632 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003633 break;
3634 }
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003635 }
Joe Perches6b808582010-11-29 07:41:53 +00003636 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003637
3638 return IRQ_RETVAL(i);
3639}
3640
David Howells7d12e782006-10-05 14:55:46 +01003641static irqreturn_t nv_nic_irq_other(int foo, void *data)
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003642{
3643 struct net_device *dev = (struct net_device *) data;
3644 struct fe_priv *np = netdev_priv(dev);
3645 u8 __iomem *base = get_hwbase(dev);
3646 u32 events;
3647 int i;
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003648 unsigned long flags;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003649
Joe Perches6b808582010-11-29 07:41:53 +00003650 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003651
Szymon Janc78aea4f2010-11-27 08:39:43 +00003652 for (i = 0;; i++) {
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003653 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3654 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
Joe Perches6b808582010-11-29 07:41:53 +00003655 netdev_dbg(dev, "irq: %08x\n", events);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003656 if (!(events & np->irqmask))
3657 break;
Jeff Garzikf3b197a2006-05-26 21:39:03 -04003658
Ayaz Abdulla4e16ed12007-01-23 12:00:56 -05003659 /* check tx in case we reached max loop limit in tx isr */
3660 spin_lock_irqsave(&np->lock, flags);
3661 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3662 spin_unlock_irqrestore(&np->lock, flags);
3663
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003664 if (events & NVREG_IRQ_LINK) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003665 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003666 nv_link_irq(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003667 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003668 }
3669 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003670 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003671 nv_linkchange(dev);
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003672 spin_unlock_irqrestore(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003673 np->link_timeout = jiffies + LINK_TIMEOUT;
3674 }
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003675 if (events & NVREG_IRQ_RECOVER_ERROR) {
3676 spin_lock_irq(&np->lock);
3677 /* disable interrupts on the nic */
3678 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3679 pci_push(base);
3680
3681 if (!np->in_shutdown) {
3682 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3683 np->recover_error = 1;
3684 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3685 }
3686 spin_unlock_irq(&np->lock);
3687 break;
3688 }
Ayaz Abdullaf0734ab2007-01-21 18:10:57 -05003689 if (unlikely(i > max_interrupt_work)) {
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003690 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003691 /* disable interrupts on the nic */
3692 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3693 pci_push(base);
3694
3695 if (!np->in_shutdown) {
3696 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3697 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3698 }
Peter Zijlstra0a07bc62006-09-19 14:55:22 +02003699 spin_unlock_irqrestore(&np->lock, flags);
Timo Jantunen1a2b7332007-08-14 21:56:57 +03003700 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003701 break;
3702 }
3703
3704 }
Joe Perches6b808582010-11-29 07:41:53 +00003705 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003706
3707 return IRQ_RETVAL(i);
3708}
3709
David Howells7d12e782006-10-05 14:55:46 +01003710static irqreturn_t nv_nic_irq_test(int foo, void *data)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003711{
3712 struct net_device *dev = (struct net_device *) data;
3713 struct fe_priv *np = netdev_priv(dev);
3714 u8 __iomem *base = get_hwbase(dev);
3715 u32 events;
3716
Joe Perches6b808582010-11-29 07:41:53 +00003717 netdev_dbg(dev, "%s\n", __func__);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003718
3719 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3720 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3721 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3722 } else {
3723 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3724 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3725 }
3726 pci_push(base);
Joe Perches6b808582010-11-29 07:41:53 +00003727 netdev_dbg(dev, "irq: %08x\n", events);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003728 if (!(events & NVREG_IRQ_TIMER))
3729 return IRQ_RETVAL(0);
3730
Ayaz Abdulla4db0ee12008-06-09 16:51:06 -07003731 nv_msi_workaround(np);
3732
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003733 spin_lock(&np->lock);
3734 np->intr_test = 1;
3735 spin_unlock(&np->lock);
3736
Joe Perches6b808582010-11-29 07:41:53 +00003737 netdev_dbg(dev, "%s: completed\n", __func__);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003738
3739 return IRQ_RETVAL(1);
3740}
3741
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003742static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3743{
3744 u8 __iomem *base = get_hwbase(dev);
3745 int i;
3746 u32 msixmap = 0;
3747
3748 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3749 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3750 * the remaining 8 interrupts.
3751 */
3752 for (i = 0; i < 8; i++) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003753 if ((irqmask >> i) & 0x1)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003754 msixmap |= vector << (i << 2);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003755 }
3756 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3757
3758 msixmap = 0;
3759 for (i = 0; i < 8; i++) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003760 if ((irqmask >> (i + 8)) & 0x1)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003761 msixmap |= vector << (i << 2);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003762 }
3763 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3764}
3765
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003766static int nv_request_irq(struct net_device *dev, int intr_test)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003767{
3768 struct fe_priv *np = get_nvpriv(dev);
3769 u8 __iomem *base = get_hwbase(dev);
3770 int ret = 1;
3771 int i;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003772 irqreturn_t (*handler)(int foo, void *data);
3773
3774 if (intr_test) {
3775 handler = nv_nic_irq_test;
3776 } else {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003777 if (nv_optimized(np))
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003778 handler = nv_nic_irq_optimized;
3779 else
3780 handler = nv_nic_irq;
3781 }
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003782
3783 if (np->msi_flags & NV_MSI_X_CAPABLE) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003784 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003785 np->msi_x_entry[i].entry = i;
Szymon Janc34cf97e2010-11-27 08:39:46 +00003786 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3787 if (ret == 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003788 np->msi_flags |= NV_MSI_X_ENABLED;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003789 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003790 /* Request irq for rx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003791 sprintf(np->name_rx, "%s-rx", dev->name);
3792 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08003793 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003794 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3795 pci_disable_msix(np->pci_dev);
3796 np->msi_flags &= ~NV_MSI_X_ENABLED;
3797 goto out_err;
3798 }
3799 /* Request irq for tx handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003800 sprintf(np->name_tx, "%s-tx", dev->name);
3801 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08003802 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003803 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3804 pci_disable_msix(np->pci_dev);
3805 np->msi_flags &= ~NV_MSI_X_ENABLED;
3806 goto out_free_rx;
3807 }
3808 /* Request irq for link and timer handling */
Yinghai Luddb213f2009-02-06 01:29:23 -08003809 sprintf(np->name_other, "%s-other", dev->name);
3810 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
Joe Perchesa0607fd2009-11-18 23:29:17 -08003811 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003812 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3813 pci_disable_msix(np->pci_dev);
3814 np->msi_flags &= ~NV_MSI_X_ENABLED;
3815 goto out_free_tx;
3816 }
3817 /* map interrupts to their respective vector */
3818 writel(0, base + NvRegMSIXMap0);
3819 writel(0, base + NvRegMSIXMap1);
3820 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3821 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3822 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3823 } else {
3824 /* Request irq for all interrupts */
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003825 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003826 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3827 pci_disable_msix(np->pci_dev);
3828 np->msi_flags &= ~NV_MSI_X_ENABLED;
3829 goto out_err;
3830 }
3831
3832 /* map interrupts to vector 0 */
3833 writel(0, base + NvRegMSIXMap0);
3834 writel(0, base + NvRegMSIXMap1);
3835 }
3836 }
3837 }
3838 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
Szymon Janc34cf97e2010-11-27 08:39:46 +00003839 ret = pci_enable_msi(np->pci_dev);
3840 if (ret == 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003841 np->msi_flags |= NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003842 dev->irq = np->pci_dev->irq;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003843 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003844 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3845 pci_disable_msi(np->pci_dev);
3846 np->msi_flags &= ~NV_MSI_ENABLED;
Manfred Spraula7475902007-10-17 21:52:33 +02003847 dev->irq = np->pci_dev->irq;
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003848 goto out_err;
3849 }
3850
3851 /* map interrupts to vector 0 */
3852 writel(0, base + NvRegMSIMap0);
3853 writel(0, base + NvRegMSIMap1);
3854 /* enable msi vector 0 */
3855 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3856 }
3857 }
3858 if (ret != 0) {
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05003859 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003860 goto out_err;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04003861
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003862 }
3863
3864 return 0;
3865out_free_tx:
3866 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3867out_free_rx:
3868 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3869out_err:
3870 return 1;
3871}
3872
3873static void nv_free_irq(struct net_device *dev)
3874{
3875 struct fe_priv *np = get_nvpriv(dev);
3876 int i;
3877
3878 if (np->msi_flags & NV_MSI_X_ENABLED) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00003879 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003880 free_irq(np->msi_x_entry[i].vector, dev);
Ayaz Abdulla7a1854b2006-06-10 22:48:08 -04003881 pci_disable_msix(np->pci_dev);
3882 np->msi_flags &= ~NV_MSI_X_ENABLED;
3883 } else {
3884 free_irq(np->pci_dev->irq, dev);
3885 if (np->msi_flags & NV_MSI_ENABLED) {
3886 pci_disable_msi(np->pci_dev);
3887 np->msi_flags &= ~NV_MSI_ENABLED;
3888 }
3889 }
3890}
3891
Linus Torvalds1da177e2005-04-16 15:20:36 -07003892static void nv_do_nic_poll(unsigned long data)
3893{
3894 struct net_device *dev = (struct net_device *) data;
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04003895 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003896 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003897 u32 mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003898
Linus Torvalds1da177e2005-04-16 15:20:36 -07003899 /*
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003900 * First disable irq(s) and then
Linus Torvalds1da177e2005-04-16 15:20:36 -07003901 * reenable interrupts on the nic, we have to do this before calling
3902 * nv_nic_irq because that may decide to do otherwise
3903 */
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003904
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003905 if (!using_multi_irqs(dev)) {
3906 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003907 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003908 else
Manfred Spraula7475902007-10-17 21:52:33 +02003909 disable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003910 mask = np->irqmask;
3911 } else {
3912 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003913 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003914 mask |= NVREG_IRQ_RX_ALL;
3915 }
3916 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003917 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003918 mask |= NVREG_IRQ_TX_ALL;
3919 }
3920 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003921 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003922 mask |= NVREG_IRQ_OTHER;
3923 }
3924 }
Manfred Spraula7475902007-10-17 21:52:33 +02003925 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3926
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003927 if (np->recover_error) {
3928 np->recover_error = 0;
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08003929 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003930 if (netif_running(dev)) {
3931 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07003932 netif_addr_lock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003933 spin_lock(&np->lock);
3934 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003935 nv_stop_rxtx(dev);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08003936 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3937 nv_mac_reset(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003938 nv_txrx_reset(dev);
3939 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003940 nv_drain_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003941 /* reinit driver view of the rx queue */
3942 set_bufsize(dev);
3943 if (nv_init_ring(dev)) {
3944 if (!np->in_shutdown)
3945 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3946 }
3947 /* reinit nic view of the rx queue */
3948 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3949 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00003950 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003951 base + NvRegRingSizes);
3952 pci_push(base);
3953 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3954 pci_push(base);
Ayaz Abdulladaa91a92009-02-07 00:25:00 -08003955 /* clear interrupts */
3956 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3957 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3958 else
3959 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003960
3961 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003962 nv_start_rxtx(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003963 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07003964 netif_addr_unlock(dev);
Ayaz Abdullac5cf9102006-10-30 17:32:01 -05003965 netif_tx_unlock_bh(dev);
3966 }
3967 }
3968
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003969 writel(mask, base + NvRegIrqMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003970 pci_push(base);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003971
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003972 if (!using_multi_irqs(dev)) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003973 np->nic_poll_irq = 0;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04003974 if (nv_optimized(np))
Ayaz Abdullafcc5f262007-03-23 05:49:37 -05003975 nv_nic_irq_optimized(0, dev);
3976 else
3977 nv_nic_irq(0, dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003978 if (np->msi_flags & NV_MSI_X_ENABLED)
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003979 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07003980 else
Manfred Spraula7475902007-10-17 21:52:33 +02003981 enable_irq_lockdep(np->pci_dev->irq);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003982 } else {
3983 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003984 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01003985 nv_nic_irq_rx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003986 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003987 }
3988 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003989 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
David Howells7d12e782006-10-05 14:55:46 +01003990 nv_nic_irq_tx(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003991 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003992 }
3993 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
Yinghai Lu79d30a52009-02-06 01:30:01 -08003994 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
David Howells7d12e782006-10-05 14:55:46 +01003995 nv_nic_irq_other(0, dev);
Ingo Molnar8688cfc2006-07-03 00:25:39 -07003996 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05003997 }
3998 }
Yinghai Lu79d30a52009-02-06 01:30:01 -08003999
Linus Torvalds1da177e2005-04-16 15:20:36 -07004000}
4001
Michal Schmidt2918c352005-05-12 19:42:06 -04004002#ifdef CONFIG_NET_POLL_CONTROLLER
4003static void nv_poll_controller(struct net_device *dev)
4004{
4005 nv_do_nic_poll((unsigned long) dev);
4006}
4007#endif
4008
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004009static void nv_do_stats_poll(unsigned long data)
4010{
4011 struct net_device *dev = (struct net_device *) data;
4012 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004013
Ayaz Abdulla57fff692007-01-23 12:27:00 -05004014 nv_get_hw_stats(dev);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004015
4016 if (!np->in_shutdown)
Daniel Drakebfebbb82008-03-18 11:07:18 +00004017 mod_timer(&np->stats_poll,
4018 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004019}
4020
Linus Torvalds1da177e2005-04-16 15:20:36 -07004021static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4022{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004023 struct fe_priv *np = netdev_priv(dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04004024 strcpy(info->driver, DRV_NAME);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004025 strcpy(info->version, FORCEDETH_VERSION);
4026 strcpy(info->bus_info, pci_name(np->pci_dev));
4027}
4028
4029static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4030{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004031 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004032 wolinfo->supported = WAKE_MAGIC;
4033
4034 spin_lock_irq(&np->lock);
4035 if (np->wolenabled)
4036 wolinfo->wolopts = WAKE_MAGIC;
4037 spin_unlock_irq(&np->lock);
4038}
4039
4040static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4041{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004042 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004043 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004044 u32 flags = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004045
Linus Torvalds1da177e2005-04-16 15:20:36 -07004046 if (wolinfo->wolopts == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004047 np->wolenabled = 0;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004048 } else if (wolinfo->wolopts & WAKE_MAGIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004049 np->wolenabled = 1;
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004050 flags = NVREG_WAKEUPFLAGS_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004051 }
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04004052 if (netif_running(dev)) {
4053 spin_lock_irq(&np->lock);
4054 writel(flags, base + NvRegWakeUpFlags);
4055 spin_unlock_irq(&np->lock);
4056 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004057 return 0;
4058}
4059
4060static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4061{
4062 struct fe_priv *np = netdev_priv(dev);
4063 int adv;
4064
4065 spin_lock_irq(&np->lock);
4066 ecmd->port = PORT_MII;
4067 if (!netif_running(dev)) {
4068 /* We do not track link speed / duplex setting if the
4069 * interface is disabled. Force a link check */
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004070 if (nv_update_linkspeed(dev)) {
4071 if (!netif_carrier_ok(dev))
4072 netif_carrier_on(dev);
4073 } else {
4074 if (netif_carrier_ok(dev))
4075 netif_carrier_off(dev);
4076 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004077 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004078
4079 if (netif_carrier_ok(dev)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004080 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004081 case NVREG_LINKSPEED_10:
4082 ecmd->speed = SPEED_10;
4083 break;
4084 case NVREG_LINKSPEED_100:
4085 ecmd->speed = SPEED_100;
4086 break;
4087 case NVREG_LINKSPEED_1000:
4088 ecmd->speed = SPEED_1000;
4089 break;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004090 }
4091 ecmd->duplex = DUPLEX_HALF;
4092 if (np->duplex)
4093 ecmd->duplex = DUPLEX_FULL;
4094 } else {
4095 ecmd->speed = -1;
4096 ecmd->duplex = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004097 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004098
4099 ecmd->autoneg = np->autoneg;
4100
4101 ecmd->advertising = ADVERTISED_MII;
4102 if (np->autoneg) {
4103 ecmd->advertising |= ADVERTISED_Autoneg;
4104 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004105 if (adv & ADVERTISE_10HALF)
4106 ecmd->advertising |= ADVERTISED_10baseT_Half;
4107 if (adv & ADVERTISE_10FULL)
4108 ecmd->advertising |= ADVERTISED_10baseT_Full;
4109 if (adv & ADVERTISE_100HALF)
4110 ecmd->advertising |= ADVERTISED_100baseT_Half;
4111 if (adv & ADVERTISE_100FULL)
4112 ecmd->advertising |= ADVERTISED_100baseT_Full;
4113 if (np->gigabit == PHY_GIGABIT) {
4114 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4115 if (adv & ADVERTISE_1000FULL)
4116 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4117 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004118 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004119 ecmd->supported = (SUPPORTED_Autoneg |
4120 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4121 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4122 SUPPORTED_MII);
4123 if (np->gigabit == PHY_GIGABIT)
4124 ecmd->supported |= SUPPORTED_1000baseT_Full;
4125
4126 ecmd->phy_address = np->phyaddr;
4127 ecmd->transceiver = XCVR_EXTERNAL;
4128
4129 /* ignore maxtxpkt, maxrxpkt for now */
4130 spin_unlock_irq(&np->lock);
4131 return 0;
4132}
4133
4134static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4135{
4136 struct fe_priv *np = netdev_priv(dev);
4137
4138 if (ecmd->port != PORT_MII)
4139 return -EINVAL;
4140 if (ecmd->transceiver != XCVR_EXTERNAL)
4141 return -EINVAL;
4142 if (ecmd->phy_address != np->phyaddr) {
4143 /* TODO: support switching between multiple phys. Should be
4144 * trivial, but not enabled due to lack of test hardware. */
4145 return -EINVAL;
4146 }
4147 if (ecmd->autoneg == AUTONEG_ENABLE) {
4148 u32 mask;
4149
4150 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4151 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4152 if (np->gigabit == PHY_GIGABIT)
4153 mask |= ADVERTISED_1000baseT_Full;
4154
4155 if ((ecmd->advertising & mask) == 0)
4156 return -EINVAL;
4157
4158 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4159 /* Note: autonegotiation disable, speed 1000 intentionally
4160 * forbidden - noone should need that. */
4161
4162 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4163 return -EINVAL;
4164 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4165 return -EINVAL;
4166 } else {
4167 return -EINVAL;
4168 }
4169
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004170 netif_carrier_off(dev);
4171 if (netif_running(dev)) {
Tobias Diedrich97bff092008-07-03 23:54:56 -07004172 unsigned long flags;
4173
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004174 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004175 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004176 netif_addr_lock(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004177 /* with plain spinlock lockdep complains */
4178 spin_lock_irqsave(&np->lock, flags);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004179 /* stop engines */
Tobias Diedrich97bff092008-07-03 23:54:56 -07004180 /* FIXME:
4181 * this can take some time, and interrupts are disabled
4182 * due to spin_lock_irqsave, but let's hope no daemon
4183 * is going to change the settings very often...
4184 * Worst case:
4185 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4186 * + some minor delays, which is up to a second approximately
4187 */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004188 nv_stop_rxtx(dev);
Tobias Diedrich97bff092008-07-03 23:54:56 -07004189 spin_unlock_irqrestore(&np->lock, flags);
David S. Millere308a5d2008-07-15 00:13:44 -07004190 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004191 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004192 }
4193
Linus Torvalds1da177e2005-04-16 15:20:36 -07004194 if (ecmd->autoneg == AUTONEG_ENABLE) {
4195 int adv, bmcr;
4196
4197 np->autoneg = 1;
4198
4199 /* advertise only what has been requested */
4200 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004201 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004202 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4203 adv |= ADVERTISE_10HALF;
4204 if (ecmd->advertising & ADVERTISED_10baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004205 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004206 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4207 adv |= ADVERTISE_100HALF;
4208 if (ecmd->advertising & ADVERTISED_100baseT_Full)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004209 adv |= ADVERTISE_100FULL;
4210 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4211 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4212 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4213 adv |= ADVERTISE_PAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004214 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4215
4216 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004217 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004218 adv &= ~ADVERTISE_1000FULL;
4219 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4220 adv |= ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004221 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004222 }
4223
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004224 if (netif_running(dev))
4225 printk(KERN_INFO "%s: link down.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004226 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004227 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4228 bmcr |= BMCR_ANENABLE;
4229 /* reset the phy in order for settings to stick,
4230 * and cause autoneg to start */
4231 if (phy_reset(dev, bmcr)) {
4232 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4233 return -EINVAL;
4234 }
4235 } else {
4236 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4237 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4238 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004239 } else {
4240 int adv, bmcr;
4241
4242 np->autoneg = 0;
4243
4244 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004245 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004246 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4247 adv |= ADVERTISE_10HALF;
4248 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004249 adv |= ADVERTISE_10FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004250 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4251 adv |= ADVERTISE_100HALF;
4252 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004253 adv |= ADVERTISE_100FULL;
4254 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4255 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4256 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4257 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4258 }
4259 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4260 adv |= ADVERTISE_PAUSE_ASYM;
4261 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4262 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004263 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4264 np->fixed_mode = adv;
4265
4266 if (np->gigabit == PHY_GIGABIT) {
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004267 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004268 adv &= ~ADVERTISE_1000FULL;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04004269 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004270 }
4271
4272 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004273 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4274 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004275 bmcr |= BMCR_FULLDPLX;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004276 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004277 bmcr |= BMCR_SPEED100;
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004278 if (np->phy_oui == PHY_OUI_MARVELL) {
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004279 /* reset the phy in order for forced mode settings to stick */
4280 if (phy_reset(dev, bmcr)) {
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004281 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4282 return -EINVAL;
4283 }
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004284 } else {
4285 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4286 if (netif_running(dev)) {
4287 /* Wait a bit and then reconfigure the nic. */
4288 udelay(10);
4289 nv_linkchange(dev);
4290 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004291 }
4292 }
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004293
4294 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004295 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004296 nv_enable_irq(dev);
4297 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004298
4299 return 0;
4300}
4301
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004302#define FORCEDETH_REGS_VER 1
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004303
4304static int nv_get_regs_len(struct net_device *dev)
4305{
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04004306 struct fe_priv *np = netdev_priv(dev);
4307 return np->register_size;
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004308}
4309
4310static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4311{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004312 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004313 u8 __iomem *base = get_hwbase(dev);
4314 u32 *rbuf = buf;
4315 int i;
4316
4317 regs->version = FORCEDETH_REGS_VER;
4318 spin_lock_irq(&np->lock);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004319 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004320 rbuf[i] = readl(base + i*sizeof(u32));
4321 spin_unlock_irq(&np->lock);
4322}
4323
4324static int nv_nway_reset(struct net_device *dev)
4325{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04004326 struct fe_priv *np = netdev_priv(dev);
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004327 int ret;
4328
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004329 if (np->autoneg) {
4330 int bmcr;
4331
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004332 netif_carrier_off(dev);
4333 if (netif_running(dev)) {
4334 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004335 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004336 netif_addr_lock(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004337 spin_lock(&np->lock);
4338 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004339 nv_stop_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004340 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004341 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004342 netif_tx_unlock_bh(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004343 printk(KERN_INFO "%s: link down.\n", dev->name);
4344 }
4345
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004346 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04004347 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4348 bmcr |= BMCR_ANENABLE;
4349 /* reset the phy in order for settings to stick*/
4350 if (phy_reset(dev, bmcr)) {
4351 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4352 return -EINVAL;
4353 }
4354 } else {
4355 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4356 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4357 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004358
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004359 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004360 nv_start_rxtx(dev);
Ayaz Abdullaf9430a02006-06-10 22:47:47 -04004361 nv_enable_irq(dev);
4362 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004363 ret = 0;
4364 } else {
4365 ret = -EINVAL;
4366 }
Manfred Sprauldc8216c2005-07-31 18:26:05 +02004367
4368 return ret;
4369}
4370
Zachary Amsden0674d592006-06-04 02:51:38 -07004371static int nv_set_tso(struct net_device *dev, u32 value)
4372{
4373 struct fe_priv *np = netdev_priv(dev);
4374
4375 if ((np->driver_data & DEV_HAS_CHECKSUM))
4376 return ethtool_op_set_tso(dev, value);
4377 else
Ayaz Abdulla6a788142006-06-10 22:47:26 -04004378 return -EOPNOTSUPP;
Zachary Amsden0674d592006-06-04 02:51:38 -07004379}
Zachary Amsden0674d592006-06-04 02:51:38 -07004380
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004381static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4382{
4383 struct fe_priv *np = netdev_priv(dev);
4384
4385 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4386 ring->rx_mini_max_pending = 0;
4387 ring->rx_jumbo_max_pending = 0;
4388 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4389
4390 ring->rx_pending = np->rx_ring_size;
4391 ring->rx_mini_pending = 0;
4392 ring->rx_jumbo_pending = 0;
4393 ring->tx_pending = np->tx_ring_size;
4394}
4395
4396static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4397{
4398 struct fe_priv *np = netdev_priv(dev);
4399 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004400 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004401 dma_addr_t ring_addr;
4402
4403 if (ring->rx_pending < RX_RING_MIN ||
4404 ring->tx_pending < TX_RING_MIN ||
4405 ring->rx_mini_pending != 0 ||
4406 ring->rx_jumbo_pending != 0 ||
4407 (np->desc_ver == DESC_VER_1 &&
4408 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4409 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4410 (np->desc_ver != DESC_VER_1 &&
4411 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4412 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4413 return -EINVAL;
4414 }
4415
4416 /* allocate new rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004417 if (!nv_optimized(np)) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004418 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4419 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4420 &ring_addr);
4421 } else {
4422 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4423 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4424 &ring_addr);
4425 }
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004426 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4427 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4428 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004429 /* fall back to old rings */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004430 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004431 if (rxtx_ring)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004432 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4433 rxtx_ring, ring_addr);
4434 } else {
4435 if (rxtx_ring)
4436 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4437 rxtx_ring, ring_addr);
4438 }
Szymon Janc9b03b062010-11-27 08:39:44 +00004439
4440 kfree(rx_skbuff);
4441 kfree(tx_skbuff);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004442 goto exit;
4443 }
4444
4445 if (netif_running(dev)) {
4446 nv_disable_irq(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004447 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004448 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004449 netif_addr_lock(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004450 spin_lock(&np->lock);
4451 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004452 nv_stop_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004453 nv_txrx_reset(dev);
4454 /* drain queues */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004455 nv_drain_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004456 /* delete queues */
4457 free_rings(dev);
4458 }
4459
4460 /* set new values */
4461 np->rx_ring_size = ring->rx_pending;
4462 np->tx_ring_size = ring->tx_pending;
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004463
4464 if (!nv_optimized(np)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004465 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004466 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4467 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004468 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004469 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4470 }
Szymon Janc78aea4f2010-11-27 08:39:43 +00004471 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4472 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004473 np->ring_addr = ring_addr;
4474
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004475 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4476 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004477
4478 if (netif_running(dev)) {
4479 /* reinit driver view of the queues */
4480 set_bufsize(dev);
4481 if (nv_init_ring(dev)) {
4482 if (!np->in_shutdown)
4483 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4484 }
4485
4486 /* reinit nic view of the queues */
4487 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4488 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004489 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004490 base + NvRegRingSizes);
4491 pci_push(base);
4492 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4493 pci_push(base);
4494
4495 /* restart engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004496 nv_start_rxtx(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004497 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004498 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004499 netif_tx_unlock_bh(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004500 nv_napi_enable(dev);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04004501 nv_enable_irq(dev);
4502 }
4503 return 0;
4504exit:
4505 return -ENOMEM;
4506}
4507
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004508static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4509{
4510 struct fe_priv *np = netdev_priv(dev);
4511
4512 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4513 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4514 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4515}
4516
4517static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4518{
4519 struct fe_priv *np = netdev_priv(dev);
4520 int adv, bmcr;
4521
4522 if ((!np->autoneg && np->duplex == 0) ||
4523 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4524 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4525 dev->name);
4526 return -EINVAL;
4527 }
4528 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4529 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4530 return -EINVAL;
4531 }
4532
4533 netif_carrier_off(dev);
4534 if (netif_running(dev)) {
4535 nv_disable_irq(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004536 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004537 netif_addr_lock(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004538 spin_lock(&np->lock);
4539 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004540 nv_stop_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004541 spin_unlock(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004542 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004543 netif_tx_unlock_bh(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004544 }
4545
4546 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4547 if (pause->rx_pause)
4548 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4549 if (pause->tx_pause)
4550 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4551
4552 if (np->autoneg && pause->autoneg) {
4553 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4554
4555 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4556 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4557 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4558 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4559 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4560 adv |= ADVERTISE_PAUSE_ASYM;
4561 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4562
4563 if (netif_running(dev))
4564 printk(KERN_INFO "%s: link down.\n", dev->name);
4565 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4566 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4567 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4568 } else {
4569 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4570 if (pause->rx_pause)
4571 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4572 if (pause->tx_pause)
4573 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4574
4575 if (!netif_running(dev))
4576 nv_update_linkspeed(dev);
4577 else
4578 nv_update_pause(dev, np->pause_flags);
4579 }
4580
4581 if (netif_running(dev)) {
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004582 nv_start_rxtx(dev);
Ayaz Abdullab6d07732006-06-10 22:47:42 -04004583 nv_enable_irq(dev);
4584 }
4585 return 0;
4586}
4587
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004588static u32 nv_get_rx_csum(struct net_device *dev)
4589{
4590 struct fe_priv *np = netdev_priv(dev);
Eric Dumazet807540b2010-09-23 05:40:09 +00004591 return np->rx_csum != 0;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004592}
4593
4594static int nv_set_rx_csum(struct net_device *dev, u32 data)
4595{
4596 struct fe_priv *np = netdev_priv(dev);
4597 u8 __iomem *base = get_hwbase(dev);
4598 int retcode = 0;
4599
4600 if (np->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004601 if (data) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004602 np->rx_csum = 1;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004603 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004604 } else {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04004605 np->rx_csum = 0;
4606 /* vlan is dependent on rx checksum offload */
4607 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4608 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004609 }
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004610 if (netif_running(dev)) {
4611 spin_lock_irq(&np->lock);
4612 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4613 spin_unlock_irq(&np->lock);
4614 }
4615 } else {
4616 return -EINVAL;
4617 }
4618
4619 return retcode;
4620}
4621
4622static int nv_set_tx_csum(struct net_device *dev, u32 data)
4623{
4624 struct fe_priv *np = netdev_priv(dev);
4625
4626 if (np->driver_data & DEV_HAS_CHECKSUM)
Ayaz Abdullac1086cd2009-02-07 00:24:39 -08004627 return ethtool_op_set_tx_csum(dev, data);
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04004628 else
4629 return -EOPNOTSUPP;
4630}
4631
4632static int nv_set_sg(struct net_device *dev, u32 data)
4633{
4634 struct fe_priv *np = netdev_priv(dev);
4635
4636 if (np->driver_data & DEV_HAS_CHECKSUM)
4637 return ethtool_op_set_sg(dev, data);
4638 else
4639 return -EOPNOTSUPP;
4640}
4641
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004642static int nv_get_sset_count(struct net_device *dev, int sset)
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004643{
4644 struct fe_priv *np = netdev_priv(dev);
4645
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004646 switch (sset) {
4647 case ETH_SS_TEST:
4648 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4649 return NV_TEST_COUNT_EXTENDED;
4650 else
4651 return NV_TEST_COUNT_BASE;
4652 case ETH_SS_STATS:
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004653 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4654 return NV_DEV_STATISTICS_V3_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004655 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4656 return NV_DEV_STATISTICS_V2_COUNT;
Ayaz Abdulla8ed14542009-03-05 08:01:49 +00004657 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4658 return NV_DEV_STATISTICS_V1_COUNT;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004659 else
4660 return 0;
4661 default:
4662 return -EOPNOTSUPP;
4663 }
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004664}
4665
4666static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4667{
4668 struct fe_priv *np = netdev_priv(dev);
4669
4670 /* update stats */
4671 nv_do_stats_poll((unsigned long)dev);
4672
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004673 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004674}
4675
4676static int nv_link_test(struct net_device *dev)
4677{
4678 struct fe_priv *np = netdev_priv(dev);
4679 int mii_status;
4680
4681 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4682 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4683
4684 /* check phy link status */
4685 if (!(mii_status & BMSR_LSTATUS))
4686 return 0;
4687 else
4688 return 1;
4689}
4690
4691static int nv_register_test(struct net_device *dev)
4692{
4693 u8 __iomem *base = get_hwbase(dev);
4694 int i = 0;
4695 u32 orig_read, new_read;
4696
4697 do {
4698 orig_read = readl(base + nv_registers_test[i].reg);
4699
4700 /* xor with mask to toggle bits */
4701 orig_read ^= nv_registers_test[i].mask;
4702
4703 writel(orig_read, base + nv_registers_test[i].reg);
4704
4705 new_read = readl(base + nv_registers_test[i].reg);
4706
4707 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4708 return 0;
4709
4710 /* restore original value */
4711 orig_read ^= nv_registers_test[i].mask;
4712 writel(orig_read, base + nv_registers_test[i].reg);
4713
4714 } while (nv_registers_test[++i].reg != 0);
4715
4716 return 1;
4717}
4718
4719static int nv_interrupt_test(struct net_device *dev)
4720{
4721 struct fe_priv *np = netdev_priv(dev);
4722 u8 __iomem *base = get_hwbase(dev);
4723 int ret = 1;
4724 int testcnt;
4725 u32 save_msi_flags, save_poll_interval = 0;
4726
4727 if (netif_running(dev)) {
4728 /* free current irq */
4729 nv_free_irq(dev);
4730 save_poll_interval = readl(base+NvRegPollingInterval);
4731 }
4732
4733 /* flag to test interrupt handler */
4734 np->intr_test = 0;
4735
4736 /* setup test irq */
4737 save_msi_flags = np->msi_flags;
4738 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4739 np->msi_flags |= 0x001; /* setup 1 vector */
4740 if (nv_request_irq(dev, 1))
4741 return 0;
4742
4743 /* setup timer interrupt */
4744 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4745 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4746
4747 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4748
4749 /* wait for at least one interrupt */
4750 msleep(100);
4751
4752 spin_lock_irq(&np->lock);
4753
4754 /* flag should be set within ISR */
4755 testcnt = np->intr_test;
4756 if (!testcnt)
4757 ret = 2;
4758
4759 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4760 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4761 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4762 else
4763 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4764
4765 spin_unlock_irq(&np->lock);
4766
4767 nv_free_irq(dev);
4768
4769 np->msi_flags = save_msi_flags;
4770
4771 if (netif_running(dev)) {
4772 writel(save_poll_interval, base + NvRegPollingInterval);
4773 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4774 /* restore original irq */
4775 if (nv_request_irq(dev, 0))
4776 return 0;
4777 }
4778
4779 return ret;
4780}
4781
4782static int nv_loopback_test(struct net_device *dev)
4783{
4784 struct fe_priv *np = netdev_priv(dev);
4785 u8 __iomem *base = get_hwbase(dev);
4786 struct sk_buff *tx_skb, *rx_skb;
4787 dma_addr_t test_dma_addr;
4788 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004789 u32 flags;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004790 int len, i, pkt_len;
4791 u8 *pkt_data;
4792 u32 filter_flags = 0;
4793 u32 misc1_flags = 0;
4794 int ret = 1;
4795
4796 if (netif_running(dev)) {
4797 nv_disable_irq(dev);
4798 filter_flags = readl(base + NvRegPacketFilterFlags);
4799 misc1_flags = readl(base + NvRegMisc1);
4800 } else {
4801 nv_txrx_reset(dev);
4802 }
4803
4804 /* reinit driver view of the rx queue */
4805 set_bufsize(dev);
4806 nv_init_ring(dev);
4807
4808 /* setup hardware for loopback */
4809 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4810 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4811
4812 /* reinit nic view of the rx queue */
4813 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4814 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004815 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004816 base + NvRegRingSizes);
4817 pci_push(base);
4818
4819 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004820 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004821
4822 /* setup packet for tx */
4823 pkt_len = ETH_DATA_LEN;
4824 tx_skb = dev_alloc_skb(pkt_len);
Jesper Juhl46798c82006-09-25 16:39:24 -07004825 if (!tx_skb) {
4826 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4827 " of %s\n", dev->name);
4828 ret = 0;
4829 goto out;
4830 }
Arnaldo Carvalho de Melo8b5be262007-03-20 12:08:20 -03004831 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4832 skb_tailroom(tx_skb),
4833 PCI_DMA_FROMDEVICE);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004834 pkt_data = skb_put(tx_skb, pkt_len);
4835 for (i = 0; i < pkt_len; i++)
4836 pkt_data[i] = (u8)(i & 0xff);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004837
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004838 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004839 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4840 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004841 } else {
Al Viro5bb7ea22007-12-09 16:06:41 +00004842 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4843 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004844 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004845 }
4846 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4847 pci_push(get_hwbase(dev));
4848
4849 msleep(500);
4850
4851 /* check for rx of the packet */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004852 if (!nv_optimized(np)) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004853 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004854 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4855
4856 } else {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004857 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004858 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4859 }
4860
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004861 if (flags & NV_RX_AVAIL) {
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004862 ret = 0;
4863 } else if (np->desc_ver == DESC_VER_1) {
Stephen Hemmingerf82a9352006-07-27 18:50:08 -07004864 if (flags & NV_RX_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004865 ret = 0;
4866 } else {
Szymon Janc78aea4f2010-11-27 08:39:43 +00004867 if (flags & NV_RX2_ERROR)
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004868 ret = 0;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004869 }
4870
4871 if (ret) {
4872 if (len != pkt_len) {
4873 ret = 0;
Joe Perches6b808582010-11-29 07:41:53 +00004874 netdev_dbg(dev, "loopback len mismatch %d vs %d\n",
4875 len, pkt_len);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004876 } else {
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05004877 rx_skb = np->rx_skb[0].skb;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004878 for (i = 0; i < pkt_len; i++) {
4879 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4880 ret = 0;
Joe Perches6b808582010-11-29 07:41:53 +00004881 netdev_dbg(dev, "loopback pattern check failed on byte %d\n",
4882 i);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004883 break;
4884 }
4885 }
4886 }
4887 } else {
Joe Perches6b808582010-11-29 07:41:53 +00004888 netdev_dbg(dev, "loopback - did not receive test packet\n");
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004889 }
4890
Eric Dumazet73a37072009-06-17 21:17:59 +00004891 pci_unmap_single(np->pci_dev, test_dma_addr,
Arnaldo Carvalho de Melo4305b542007-04-19 20:43:29 -07004892 (skb_end_pointer(tx_skb) - tx_skb->data),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004893 PCI_DMA_TODEVICE);
4894 dev_kfree_skb_any(tx_skb);
Jesper Juhl46798c82006-09-25 16:39:24 -07004895 out:
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004896 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004897 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004898 nv_txrx_reset(dev);
4899 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004900 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004901
4902 if (netif_running(dev)) {
4903 writel(misc1_flags, base + NvRegMisc1);
4904 writel(filter_flags, base + NvRegPacketFilterFlags);
4905 nv_enable_irq(dev);
4906 }
4907
4908 return ret;
4909}
4910
4911static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4912{
4913 struct fe_priv *np = netdev_priv(dev);
4914 u8 __iomem *base = get_hwbase(dev);
4915 int result;
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004916 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004917
4918 if (!nv_link_test(dev)) {
4919 test->flags |= ETH_TEST_FL_FAILED;
4920 buffer[0] = 1;
4921 }
4922
4923 if (test->flags & ETH_TEST_FL_OFFLINE) {
4924 if (netif_running(dev)) {
4925 netif_stop_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004926 nv_napi_disable(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004927 netif_tx_lock_bh(dev);
David S. Millere308a5d2008-07-15 00:13:44 -07004928 netif_addr_lock(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004929 spin_lock_irq(&np->lock);
4930 nv_disable_hw_interrupts(dev, np->irqmask);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004931 if (!(np->msi_flags & NV_MSI_X_ENABLED))
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004932 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004933 else
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004934 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004935 /* stop engines */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004936 nv_stop_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004937 nv_txrx_reset(dev);
4938 /* drain rx queue */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004939 nv_drain_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004940 spin_unlock_irq(&np->lock);
David S. Millere308a5d2008-07-15 00:13:44 -07004941 netif_addr_unlock(dev);
Herbert Xu58dfd9c2006-06-21 10:53:54 +10004942 netif_tx_unlock_bh(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004943 }
4944
4945 if (!nv_register_test(dev)) {
4946 test->flags |= ETH_TEST_FL_FAILED;
4947 buffer[1] = 1;
4948 }
4949
4950 result = nv_interrupt_test(dev);
4951 if (result != 1) {
4952 test->flags |= ETH_TEST_FL_FAILED;
4953 buffer[2] = 1;
4954 }
4955 if (result == 0) {
4956 /* bail out */
4957 return;
4958 }
4959
4960 if (!nv_loopback_test(dev)) {
4961 test->flags |= ETH_TEST_FL_FAILED;
4962 buffer[3] = 1;
4963 }
4964
4965 if (netif_running(dev)) {
4966 /* reinit driver view of the rx queue */
4967 set_bufsize(dev);
4968 if (nv_init_ring(dev)) {
4969 if (!np->in_shutdown)
4970 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4971 }
4972 /* reinit nic view of the rx queue */
4973 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4974 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00004975 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004976 base + NvRegRingSizes);
4977 pci_push(base);
4978 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4979 pci_push(base);
4980 /* restart rx engine */
Jeff Garzik36b30ea2007-10-16 01:40:30 -04004981 nv_start_rxtx(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004982 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00004983 nv_napi_enable(dev);
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004984 nv_enable_hw_interrupts(dev, np->irqmask);
4985 }
4986 }
4987}
4988
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004989static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4990{
4991 switch (stringset) {
4992 case ETH_SS_STATS:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004993 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004994 break;
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004995 case ETH_SS_TEST:
Jeff Garzikb9f2c042007-10-03 18:07:32 -07004996 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
Ayaz Abdulla9589c772006-06-10 22:48:13 -04004997 break;
Ayaz Abdulla52da3572006-06-10 22:48:04 -04004998 }
4999}
5000
Jeff Garzik7282d492006-09-13 14:30:00 -04005001static const struct ethtool_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005002 .get_drvinfo = nv_get_drvinfo,
5003 .get_link = ethtool_op_get_link,
5004 .get_wol = nv_get_wol,
5005 .set_wol = nv_set_wol,
5006 .get_settings = nv_get_settings,
5007 .set_settings = nv_set_settings,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02005008 .get_regs_len = nv_get_regs_len,
5009 .get_regs = nv_get_regs,
5010 .nway_reset = nv_nway_reset,
Ayaz Abdulla6a788142006-06-10 22:47:26 -04005011 .set_tso = nv_set_tso,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005012 .get_ringparam = nv_get_ringparam,
5013 .set_ringparam = nv_set_ringparam,
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005014 .get_pauseparam = nv_get_pauseparam,
5015 .set_pauseparam = nv_set_pauseparam,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005016 .get_rx_csum = nv_get_rx_csum,
5017 .set_rx_csum = nv_set_rx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005018 .set_tx_csum = nv_set_tx_csum,
Ayaz Abdulla5ed26162006-06-10 22:47:59 -04005019 .set_sg = nv_set_sg,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005020 .get_strings = nv_get_strings,
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005021 .get_ethtool_stats = nv_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07005022 .get_sset_count = nv_get_sset_count,
Ayaz Abdulla9589c772006-06-10 22:48:13 -04005023 .self_test = nv_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005024};
5025
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005026static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5027{
5028 struct fe_priv *np = get_nvpriv(dev);
5029
5030 spin_lock_irq(&np->lock);
5031
5032 /* save vlan group */
5033 np->vlangrp = grp;
5034
5035 if (grp) {
5036 /* enable vlan on MAC */
5037 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5038 } else {
5039 /* disable vlan on MAC */
5040 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5041 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5042 }
5043
5044 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5045
5046 spin_unlock_irq(&np->lock);
Stephen Hemminger25805dc2007-06-01 09:44:01 -07005047}
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005048
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005049/* The mgmt unit and driver use a semaphore to access the phy during init */
5050static int nv_mgmt_acquire_sema(struct net_device *dev)
5051{
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005052 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005053 u8 __iomem *base = get_hwbase(dev);
5054 int i;
5055 u32 tx_ctrl, mgmt_sema;
5056
5057 for (i = 0; i < 10; i++) {
5058 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5059 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5060 break;
5061 msleep(500);
5062 }
5063
5064 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5065 return 0;
5066
5067 for (i = 0; i < 2; i++) {
5068 tx_ctrl = readl(base + NvRegTransmitterControl);
5069 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5070 writel(tx_ctrl, base + NvRegTransmitterControl);
5071
5072 /* verify that semaphore was acquired */
5073 tx_ctrl = readl(base + NvRegTransmitterControl);
5074 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005075 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5076 np->mgmt_sema = 1;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005077 return 1;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005078 } else
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005079 udelay(50);
5080 }
5081
5082 return 0;
5083}
5084
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005085static void nv_mgmt_release_sema(struct net_device *dev)
5086{
5087 struct fe_priv *np = netdev_priv(dev);
5088 u8 __iomem *base = get_hwbase(dev);
5089 u32 tx_ctrl;
5090
5091 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5092 if (np->mgmt_sema) {
5093 tx_ctrl = readl(base + NvRegTransmitterControl);
5094 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5095 writel(tx_ctrl, base + NvRegTransmitterControl);
5096 }
5097 }
5098}
5099
5100
5101static int nv_mgmt_get_version(struct net_device *dev)
5102{
5103 struct fe_priv *np = netdev_priv(dev);
5104 u8 __iomem *base = get_hwbase(dev);
5105 u32 data_ready = readl(base + NvRegTransmitterControl);
5106 u32 data_ready2 = 0;
5107 unsigned long start;
5108 int ready = 0;
5109
5110 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5111 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5112 start = jiffies;
5113 while (time_before(jiffies, start + 5*HZ)) {
5114 data_ready2 = readl(base + NvRegTransmitterControl);
5115 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5116 ready = 1;
5117 break;
5118 }
5119 schedule_timeout_uninterruptible(1);
5120 }
5121
5122 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5123 return 0;
5124
5125 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5126
5127 return 1;
5128}
5129
Linus Torvalds1da177e2005-04-16 15:20:36 -07005130static int nv_open(struct net_device *dev)
5131{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005132 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005133 u8 __iomem *base = get_hwbase(dev);
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005134 int ret = 1;
5135 int oom, i;
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005136 u32 low;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005137
Joe Perches6b808582010-11-29 07:41:53 +00005138 netdev_dbg(dev, "%s\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005139
Ed Swierkcb52deb2008-12-01 12:24:43 +00005140 /* power up phy */
5141 mii_rw(dev, np->phyaddr, MII_BMCR,
5142 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5143
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005144 nv_txrx_gate(dev, false);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005145 /* erase previous misconfiguration */
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005146 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5147 nv_mac_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005148 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5149 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005150 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5151 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005152 writel(0, base + NvRegPacketFilterFlags);
5153
5154 writel(0, base + NvRegTransmitterControl);
5155 writel(0, base + NvRegReceiverControl);
5156
5157 writel(0, base + NvRegAdapterControl);
5158
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005159 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5160 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5161
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005162 /* initialize descriptor rings */
Manfred Sprauld81c0982005-07-31 18:20:30 +02005163 set_bufsize(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005164 oom = nv_init_ring(dev);
5165
5166 writel(0, base + NvRegLinkSpeed);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005167 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005168 nv_txrx_reset(dev);
5169 writel(0, base + NvRegUnknownSetupReg6);
5170
5171 np->in_shutdown = 0;
5172
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005173 /* give hw rings */
Ayaz Abdulla0832b252006-02-04 13:13:26 -05005174 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005175 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
Linus Torvalds1da177e2005-04-16 15:20:36 -07005176 base + NvRegRingSizes);
5177
Linus Torvalds1da177e2005-04-16 15:20:36 -07005178 writel(np->linkspeed, base + NvRegLinkSpeed);
Ayaz Abdulla95d161c2006-07-06 16:46:25 -04005179 if (np->desc_ver == DESC_VER_1)
5180 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5181 else
5182 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005183 writel(np->txrxctl_bits, base + NvRegTxRxControl);
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005184 writel(np->vlanctl_bits, base + NvRegVlanControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005185 pci_push(base);
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005186 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
Joe Perches344d0dc2010-11-29 07:41:52 +00005187 if (reg_delay(dev, NvRegUnknownSetupReg5,
5188 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5189 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5190 printk(KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005191
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005192 writel(0, base + NvRegMIIMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005193 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005194 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005195
Linus Torvalds1da177e2005-04-16 15:20:36 -07005196 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5197 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5198 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
Manfred Sprauld81c0982005-07-31 18:20:30 +02005199 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005200
5201 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
Ayaz Abdullaa4336862008-04-18 13:50:43 -07005202
5203 get_random_bytes(&low, sizeof(low));
5204 low &= NVREG_SLOTTIME_MASK;
5205 if (np->desc_ver == DESC_VER_1) {
5206 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5207 } else {
5208 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5209 /* setup legacy backoff */
5210 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5211 } else {
5212 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5213 nv_gear_backoff_reseed(dev);
5214 }
5215 }
Ayaz Abdulla9744e212006-07-06 16:45:58 -04005216 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5217 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005218 if (poll_interval == -1) {
5219 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5220 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5221 else
5222 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005223 } else
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005224 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005225 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5226 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5227 base + NvRegAdapterControl);
5228 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005229 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
Ayaz Abdullac42d9df2006-06-10 22:47:52 -04005230 if (np->wolenabled)
5231 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005232
5233 i = readl(base + NvRegPowerState);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005234 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005235 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5236
5237 pci_push(base);
5238 udelay(10);
5239 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5240
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005241 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005242 pci_push(base);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005243 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005244 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5245 pci_push(base);
5246
Szymon Janc78aea4f2010-11-27 08:39:43 +00005247 if (nv_request_irq(dev, 0))
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005248 goto out_drain;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005249
5250 /* ask for interrupts */
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005251 nv_enable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005252
5253 spin_lock_irq(&np->lock);
5254 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5255 writel(0, base + NvRegMulticastAddrB);
Ayaz Abdullabb9a4fd2008-01-13 16:03:04 -05005256 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5257 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005258 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5259 /* One manual link speed update: Interrupts are enabled, future link
5260 * speed changes cause interrupts and are handled by nv_link_irq().
5261 */
5262 {
5263 u32 miistat;
5264 miistat = readl(base + NvRegMIIStatus);
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005265 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005266 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5267 }
Manfred Spraul1b1b3c92005-08-06 23:47:55 +02005268 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5269 * to init hw */
5270 np->linkspeed = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005271 ret = nv_update_linkspeed(dev);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005272 nv_start_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005273 netif_start_queue(dev);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005274 nv_napi_enable(dev);
Stephen Hemmingere27cdba2006-07-31 20:37:19 -07005275
Linus Torvalds1da177e2005-04-16 15:20:36 -07005276 if (ret) {
5277 netif_carrier_on(dev);
5278 } else {
Ed Swierkf7ab6972007-09-28 22:42:13 -07005279 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005280 netif_carrier_off(dev);
5281 }
5282 if (oom)
5283 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005284
5285 /* start statistics timer */
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005286 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Daniel Drakebfebbb82008-03-18 11:07:18 +00005287 mod_timer(&np->stats_poll,
5288 round_jiffies(jiffies + STATS_INTERVAL));
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005289
Linus Torvalds1da177e2005-04-16 15:20:36 -07005290 spin_unlock_irq(&np->lock);
5291
5292 return 0;
5293out_drain:
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005294 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005295 return ret;
5296}
5297
5298static int nv_close(struct net_device *dev)
5299{
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005300 struct fe_priv *np = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005301 u8 __iomem *base;
5302
5303 spin_lock_irq(&np->lock);
5304 np->in_shutdown = 1;
5305 spin_unlock_irq(&np->lock);
Ayaz Abdulla08d93572009-03-05 08:01:55 +00005306 nv_napi_disable(dev);
Manfred Spraula7475902007-10-17 21:52:33 +02005307 synchronize_irq(np->pci_dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005308
5309 del_timer_sync(&np->oom_kick);
5310 del_timer_sync(&np->nic_poll);
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005311 del_timer_sync(&np->stats_poll);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005312
5313 netif_stop_queue(dev);
5314 spin_lock_irq(&np->lock);
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005315 nv_stop_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005316 nv_txrx_reset(dev);
5317
5318 /* disable interrupts on the nic or we will lock up */
5319 base = get_hwbase(dev);
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005320 nv_disable_hw_interrupts(dev, np->irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005321 pci_push(base);
5322 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5323
5324 spin_unlock_irq(&np->lock);
5325
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005326 nv_free_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005327
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005328 nv_drain_rxtx(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005329
Ed Swierk5a9a8e32009-06-02 00:19:52 -07005330 if (np->wolenabled || !phy_power_down) {
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005331 nv_txrx_gate(dev, false);
Tim Mann2cc49a52007-06-14 13:16:38 -07005332 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005333 nv_start_rx(dev);
Ed Swierkcb52deb2008-12-01 12:24:43 +00005334 } else {
5335 /* power down phy */
5336 mii_rw(dev, np->phyaddr, MII_BMCR,
5337 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
Ayaz Abdulla88d7d8b2009-05-01 01:41:50 +00005338 nv_txrx_gate(dev, true);
Tim Mann2cc49a52007-06-14 13:16:38 -07005339 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005340
5341 /* FIXME: power down nic */
5342
5343 return 0;
5344}
5345
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005346static const struct net_device_ops nv_netdev_ops = {
5347 .ndo_open = nv_open,
5348 .ndo_stop = nv_close,
5349 .ndo_get_stats = nv_get_stats,
Stephen Hemminger00829822008-11-20 20:14:53 -08005350 .ndo_start_xmit = nv_start_xmit,
5351 .ndo_tx_timeout = nv_tx_timeout,
5352 .ndo_change_mtu = nv_change_mtu,
5353 .ndo_validate_addr = eth_validate_addr,
5354 .ndo_set_mac_address = nv_set_mac_address,
5355 .ndo_set_multicast_list = nv_set_multicast,
5356 .ndo_vlan_rx_register = nv_vlan_rx_register,
5357#ifdef CONFIG_NET_POLL_CONTROLLER
5358 .ndo_poll_controller = nv_poll_controller,
5359#endif
5360};
5361
5362static const struct net_device_ops nv_netdev_ops_optimized = {
5363 .ndo_open = nv_open,
5364 .ndo_stop = nv_close,
5365 .ndo_get_stats = nv_get_stats,
5366 .ndo_start_xmit = nv_start_xmit_optimized,
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005367 .ndo_tx_timeout = nv_tx_timeout,
5368 .ndo_change_mtu = nv_change_mtu,
5369 .ndo_validate_addr = eth_validate_addr,
5370 .ndo_set_mac_address = nv_set_mac_address,
5371 .ndo_set_multicast_list = nv_set_multicast,
5372 .ndo_vlan_rx_register = nv_vlan_rx_register,
5373#ifdef CONFIG_NET_POLL_CONTROLLER
5374 .ndo_poll_controller = nv_poll_controller,
5375#endif
5376};
5377
Linus Torvalds1da177e2005-04-16 15:20:36 -07005378static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5379{
5380 struct net_device *dev;
5381 struct fe_priv *np;
5382 unsigned long addr;
5383 u8 __iomem *base;
5384 int err, i;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005385 u32 powerstate, txreg;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005386 u32 phystate_orig = 0, phystate;
5387 int phyinitialized = 0;
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005388 static int printed_version;
5389
5390 if (!printed_version++)
5391 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5392 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005393
5394 dev = alloc_etherdev(sizeof(struct fe_priv));
5395 err = -ENOMEM;
5396 if (!dev)
5397 goto out;
5398
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005399 np = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005400 np->dev = dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005401 np->pci_dev = pci_dev;
5402 spin_lock_init(&np->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005403 SET_NETDEV_DEV(dev, &pci_dev->dev);
5404
5405 init_timer(&np->oom_kick);
5406 np->oom_kick.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005407 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005408 init_timer(&np->nic_poll);
5409 np->nic_poll.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005410 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
Ayaz Abdulla52da3572006-06-10 22:48:04 -04005411 init_timer(&np->stats_poll);
5412 np->stats_poll.data = (unsigned long) dev;
Joe Perchesc061b182010-08-23 18:20:03 +00005413 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005414
5415 err = pci_enable_device(pci_dev);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005416 if (err)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005417 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005418
5419 pci_set_master(pci_dev);
5420
5421 err = pci_request_regions(pci_dev, DRV_NAME);
5422 if (err < 0)
5423 goto out_disable;
5424
Ayaz Abdulla9c662432008-08-06 12:11:42 -04005425 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
Ayaz Abdulla57fff692007-01-23 12:27:00 -05005426 np->register_size = NV_PCI_REGSZ_VER3;
5427 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005428 np->register_size = NV_PCI_REGSZ_VER2;
5429 else
5430 np->register_size = NV_PCI_REGSZ_VER1;
5431
Linus Torvalds1da177e2005-04-16 15:20:36 -07005432 err = -EINVAL;
5433 addr = 0;
5434 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
Joe Perches6b808582010-11-29 07:41:53 +00005435 netdev_dbg(dev, "%s: resource %d start %p len %lld flags 0x%08lx\n",
5436 pci_name(pci_dev), i,
5437 (void *)(unsigned long)pci_resource_start(pci_dev, i),
5438 (long long)pci_resource_len(pci_dev, i),
5439 pci_resource_flags(pci_dev, i));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005440 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005441 pci_resource_len(pci_dev, i) >= np->register_size) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005442 addr = pci_resource_start(pci_dev, i);
5443 break;
5444 }
5445 }
5446 if (i == DEVICE_COUNT_RESOURCE) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005447 dev_printk(KERN_INFO, &pci_dev->dev,
5448 "Couldn't find register window\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005449 goto out_relreg;
5450 }
5451
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005452 /* copy of driver data */
5453 np->driver_data = id->driver_data;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005454 /* copy of device id */
5455 np->device_id = id->device;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005456
Linus Torvalds1da177e2005-04-16 15:20:36 -07005457 /* handle different descriptor versions */
Manfred Spraulee733622005-07-31 18:32:26 +02005458 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5459 /* packet format 3: supports 40-bit addressing */
5460 np->desc_ver = DESC_VER_3;
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005461 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005462 if (dma_64bit) {
Yang Hongyang6afd1422009-04-06 19:01:15 -07005463 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005464 dev_printk(KERN_INFO, &pci_dev->dev,
5465 "64-bit DMA failed, using 32-bit addressing\n");
5466 else
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005467 dev->features |= NETIF_F_HIGHDMA;
Yang Hongyang6afd1422009-04-06 19:01:15 -07005468 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005469 dev_printk(KERN_INFO, &pci_dev->dev,
5470 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04005471 }
Ayaz Abdulla84b39322006-05-20 14:59:48 -07005472 }
Manfred Spraulee733622005-07-31 18:32:26 +02005473 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5474 /* packet format 2: supports jumbo frames */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005475 np->desc_ver = DESC_VER_2;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005476 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
Manfred Spraulee733622005-07-31 18:32:26 +02005477 } else {
5478 /* original packet format */
5479 np->desc_ver = DESC_VER_1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005480 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
Manfred Sprauld81c0982005-07-31 18:20:30 +02005481 }
Manfred Spraulee733622005-07-31 18:32:26 +02005482
5483 np->pkt_limit = NV_PKTLIMIT_1;
5484 if (id->driver_data & DEV_HAS_LARGEDESC)
5485 np->pkt_limit = NV_PKTLIMIT_2;
5486
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005487 if (id->driver_data & DEV_HAS_CHECKSUM) {
Ayaz Abdullaf2ad2d92006-08-24 17:35:41 -04005488 np->rx_csum = 1;
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005489 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
Ayaz Abdullaedcfe5f2008-08-20 16:34:37 -07005490 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Ayaz Abdullafa454592006-01-05 22:45:45 -08005491 dev->features |= NETIF_F_TSO;
Tom Herbert53f224c2010-05-03 19:08:45 +00005492 dev->features |= NETIF_F_GRO;
Ayaz Abdulla21828162007-01-23 12:27:21 -05005493 }
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005494
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005495 np->vlanctl_bits = 0;
5496 if (id->driver_data & DEV_HAS_VLAN) {
5497 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5498 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
Ayaz Abdullaee407b02006-02-04 13:13:17 -05005499 }
5500
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005501 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
Ayaz Abdulla5289b4c2008-02-05 12:30:01 -05005502 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5503 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5504 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
Ayaz Abdullab6d07732006-06-10 22:47:42 -04005505 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005506 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005507
Ayaz Abdullaeb91f612006-05-24 18:13:19 -04005508
Linus Torvalds1da177e2005-04-16 15:20:36 -07005509 err = -ENOMEM;
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005510 np->base = ioremap(addr, np->register_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005511 if (!np->base)
5512 goto out_relreg;
5513 dev->base_addr = (unsigned long)np->base;
Manfred Spraulee733622005-07-31 18:32:26 +02005514
Linus Torvalds1da177e2005-04-16 15:20:36 -07005515 dev->irq = pci_dev->irq;
Manfred Spraulee733622005-07-31 18:32:26 +02005516
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005517 np->rx_ring_size = RX_RING_DEFAULT;
5518 np->tx_ring_size = TX_RING_DEFAULT;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005519
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005520 if (!nv_optimized(np)) {
Manfred Spraulee733622005-07-31 18:32:26 +02005521 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005522 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005523 &np->ring_addr);
5524 if (!np->rx_ring.orig)
5525 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005526 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005527 } else {
5528 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005529 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
Manfred Spraulee733622005-07-31 18:32:26 +02005530 &np->ring_addr);
5531 if (!np->rx_ring.ex)
5532 goto out_unmap;
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005533 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
Manfred Spraulee733622005-07-31 18:32:26 +02005534 }
Yoann Padioleaudd00cc42007-07-19 01:49:03 -07005535 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5536 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
Ayaz Abdulla761fcd92007-01-09 13:30:07 -05005537 if (!np->rx_skb || !np->tx_skb)
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005538 goto out_freering;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005539
Jeff Garzik36b30ea2007-10-16 01:40:30 -04005540 if (!nv_optimized(np))
Stephen Hemminger00829822008-11-20 20:14:53 -08005541 dev->netdev_ops = &nv_netdev_ops;
Ayaz Abdulla86b22b02007-01-21 18:10:37 -05005542 else
Stephen Hemminger00829822008-11-20 20:14:53 -08005543 dev->netdev_ops = &nv_netdev_ops_optimized;
Stephen Hemmingerb94426b2008-11-19 22:26:51 -08005544
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005545 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005546 SET_ETHTOOL_OPS(dev, &ops);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005547 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5548
5549 pci_set_drvdata(pci_dev, dev);
5550
5551 /* read the mac address */
5552 base = get_hwbase(dev);
5553 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5554 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5555
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005556 /* check the workaround bit for correct mac address order */
5557 txreg = readl(base + NvRegTransmitPoll);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005558 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005559 /* mac address is already in correct order */
5560 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5561 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5562 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5563 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5564 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5565 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005566 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5567 /* mac address is already in correct order */
5568 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5569 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5570 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5571 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5572 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5573 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5574 /*
5575 * Set orig mac address back to the reversed version.
5576 * This flag will be cleared during low power transition.
5577 * Therefore, we should always put back the reversed address.
5578 */
5579 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5580 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5581 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005582 } else {
5583 /* need to reverse mac address to correct order */
5584 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5585 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5586 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5587 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5588 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5589 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005590 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005591 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
Ayaz Abdulla5070d342006-07-31 12:05:01 -04005592 }
John W. Linvillec704b852005-09-12 10:48:56 -04005593 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005594
John W. Linvillec704b852005-09-12 10:48:56 -04005595 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005596 /*
5597 * Bad mac address. At least one bios sets the mac address
5598 * to 01:23:45:67:89:ab
5599 */
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005600 dev_printk(KERN_ERR, &pci_dev->dev,
Johannes Berge1749612008-10-27 15:59:26 -07005601 "Invalid Mac address detected: %pM\n",
Szymon Janc78aea4f2010-11-27 08:39:43 +00005602 dev->dev_addr);
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005603 dev_printk(KERN_ERR, &pci_dev->dev,
5604 "Please complain to your hardware vendor. Switching to a random MAC.\n");
Stanislav O. Bezzubtsev655a6592009-11-15 21:17:02 -08005605 random_ether_addr(dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005606 }
5607
Joe Perches6b808582010-11-29 07:41:53 +00005608 netdev_dbg(dev, "%s: MAC Address %pM\n",
5609 pci_name(pci_dev), dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005610
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005611 /* set mac address */
5612 nv_copy_mac_to_hw(dev);
5613
Tobias Diedrich9a60a822008-06-01 00:54:42 +02005614 /* Workaround current PCI init glitch: wakeup bits aren't
5615 * being set from PCI PM capability.
5616 */
5617 device_init_wakeup(&pci_dev->dev, 1);
5618
Linus Torvalds1da177e2005-04-16 15:20:36 -07005619 /* disable WOL */
5620 writel(0, base + NvRegWakeUpFlags);
5621 np->wolenabled = 0;
5622
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005623 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005624
5625 /* take phy and nic out of low power mode */
5626 powerstate = readl(base + NvRegPowerState2);
5627 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005628 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
Auke Kok44c10132007-06-08 15:46:36 -07005629 pci_dev->revision >= 0xA3)
Ayaz Abdulla86a0f042006-04-24 18:41:31 -04005630 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5631 writel(powerstate, base + NvRegPowerState2);
5632 }
5633
Szymon Janc78aea4f2010-11-27 08:39:43 +00005634 if (np->desc_ver == DESC_VER_1)
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005635 np->tx_flags = NV_TX_VALID;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005636 else
Ayaz Abdullaac9c1892005-10-26 00:51:24 -04005637 np->tx_flags = NV_TX2_VALID;
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005638
5639 np->msi_flags = 0;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005640 if ((id->driver_data & DEV_HAS_MSI) && msi)
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005641 np->msi_flags |= NV_MSI_CAPABLE;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005642
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005643 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5644 /* msix has had reported issues when modifying irqmask
5645 as in the case of napi, therefore, disable for now
5646 */
David S. Miller0a127612010-05-03 23:33:05 -07005647#if 0
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005648 np->msi_flags |= NV_MSI_X_CAPABLE;
5649#endif
5650 }
5651
5652 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005653 np->irqmask = NVREG_IRQMASK_CPU;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005654 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5655 np->msi_flags |= 0x0001;
Ayaz Abdulla9e184762009-03-05 08:02:18 +00005656 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5657 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5658 /* start off in throughput mode */
5659 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5660 /* remove support for msix mode */
5661 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5662 } else {
5663 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5664 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5665 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5666 np->msi_flags |= 0x0003;
Ayaz Abdullad33a73c82006-02-04 13:13:31 -05005667 }
Ayaz Abdullaa971c322005-11-11 08:30:38 -05005668
Linus Torvalds1da177e2005-04-16 15:20:36 -07005669 if (id->driver_data & DEV_NEED_TIMERIRQ)
5670 np->irqmask |= NVREG_IRQ_TIMER;
5671 if (id->driver_data & DEV_NEED_LINKTIMER) {
5672 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5673 np->need_linktimer = 1;
5674 np->link_timeout = jiffies + LINK_TIMEOUT;
5675 } else {
5676 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5677 np->need_linktimer = 0;
5678 }
5679
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005680 /* Limit the number of tx's outstanding for hw bug */
5681 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5682 np->tx_limit = 1;
Ayaz Abdulla5c659322010-04-13 18:49:51 -07005683 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
Ayaz Abdulla3b446c32008-03-10 14:58:21 -05005684 pci_dev->revision >= 0xA2)
5685 np->tx_limit = 0;
5686 }
5687
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005688 /* clear phy state and temporarily halt phy interrupts */
5689 writel(0, base + NvRegMIIMask);
5690 phystate = readl(base + NvRegAdapterControl);
5691 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5692 phystate_orig = 1;
5693 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5694 writel(phystate, base + NvRegAdapterControl);
5695 }
Ayaz Abdullaeb798422008-02-04 15:14:04 -05005696 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005697
5698 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005699 /* management unit running on the mac? */
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005700 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5701 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5702 nv_mgmt_acquire_sema(dev) &&
5703 nv_mgmt_get_version(dev)) {
5704 np->mac_in_use = 1;
Szymon Janc78aea4f2010-11-27 08:39:43 +00005705 if (np->mgmt_version > 0)
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005706 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005707 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5708 pci_name(pci_dev), np->mac_in_use);
5709 /* management unit setup the phy already? */
5710 if (np->mac_in_use &&
5711 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5712 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5713 /* phy is inited by mgmt unit */
5714 phyinitialized = 1;
5715 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5716 pci_name(pci_dev));
5717 } else {
5718 /* we need to init the phy */
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005719 }
5720 }
5721 }
5722
Linus Torvalds1da177e2005-04-16 15:20:36 -07005723 /* find a suitable phy */
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005724 for (i = 1; i <= 32; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005725 int id1, id2;
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005726 int phyaddr = i & 0x1F;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005727
5728 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005729 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005730 spin_unlock_irq(&np->lock);
5731 if (id1 < 0 || id1 == 0xffff)
5732 continue;
5733 spin_lock_irq(&np->lock);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005734 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005735 spin_unlock_irq(&np->lock);
5736 if (id2 < 0 || id2 == 0xffff)
5737 continue;
5738
Ayaz Abdullaedf7e5e2006-08-24 15:43:42 -04005739 np->phy_model = id2 & PHYID2_MODEL_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005740 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5741 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
Joe Perches6b808582010-11-29 07:41:53 +00005742 netdev_dbg(dev, "%s: %s: Found PHY %04x:%04x at address %d\n",
5743 pci_name(pci_dev), __func__, id1, id2, phyaddr);
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005744 np->phyaddr = phyaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005745 np->phy_oui = id1 | id2;
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005746
5747 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5748 if (np->phy_oui == PHY_OUI_REALTEK2)
5749 np->phy_oui = PHY_OUI_REALTEK;
5750 /* Setup phy revision for Realtek */
5751 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5752 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5753
Linus Torvalds1da177e2005-04-16 15:20:36 -07005754 break;
5755 }
Ayaz Abdulla7a33e452005-11-11 08:31:11 -05005756 if (i == 33) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005757 dev_printk(KERN_INFO, &pci_dev->dev,
5758 "open: Could not find a valid PHY.\n");
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005759 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005760 }
Jeff Garzikf3b197a2006-05-26 21:39:03 -04005761
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005762 if (!phyinitialized) {
5763 /* reset it */
5764 phy_init(dev);
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005765 } else {
5766 /* see if it is a gigabit phy */
5767 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
Szymon Janc78aea4f2010-11-27 08:39:43 +00005768 if (mii_status & PHY_GIGABIT)
Ayaz Abdullaf35723e2003-02-20 03:03:54 -05005769 np->gigabit = PHY_GIGABIT;
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005770 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005771
5772 /* set default link speed settings */
5773 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5774 np->duplex = 0;
5775 np->autoneg = 1;
5776
5777 err = register_netdev(dev);
5778 if (err) {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005779 dev_printk(KERN_INFO, &pci_dev->dev,
5780 "unable to register netdev: %d\n", err);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005781 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005782 }
Jeff Garzik3f88ce42007-10-16 04:09:09 -04005783
5784 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5785 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5786 dev->name,
5787 np->phy_oui,
5788 np->phyaddr,
5789 dev->dev_addr[0],
5790 dev->dev_addr[1],
5791 dev->dev_addr[2],
5792 dev->dev_addr[3],
5793 dev->dev_addr[4],
5794 dev->dev_addr[5]);
5795
5796 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
Szymon Janc78aea4f2010-11-27 08:39:43 +00005797 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5798 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5799 "csum " : "",
5800 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5801 "vlan " : "",
5802 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5803 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5804 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5805 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5806 np->need_linktimer ? "lnktim " : "",
5807 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5808 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5809 np->desc_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005810
5811 return 0;
5812
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005813out_error:
Ayaz Abdulla7e680c22006-10-30 17:31:51 -05005814 if (phystate_orig)
5815 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005816 pci_set_drvdata(pci_dev, NULL);
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005817out_freering:
5818 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005819out_unmap:
5820 iounmap(get_hwbase(dev));
5821out_relreg:
5822 pci_release_regions(pci_dev);
5823out_disable:
5824 pci_disable_device(pci_dev);
5825out_free:
5826 free_netdev(dev);
5827out:
5828 return err;
5829}
5830
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005831static void nv_restore_phy(struct net_device *dev)
5832{
5833 struct fe_priv *np = netdev_priv(dev);
5834 u16 phy_reserved, mii_control;
5835
5836 if (np->phy_oui == PHY_OUI_REALTEK &&
5837 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5838 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5839 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5840 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5841 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5842 phy_reserved |= PHY_REALTEK_INIT8;
5843 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5844 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5845
5846 /* restart auto negotiation */
5847 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5848 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5849 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5850 }
5851}
5852
Yinghai Luf55c21f2008-09-13 13:10:31 -07005853static void nv_restore_mac_addr(struct pci_dev *pci_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005854{
5855 struct net_device *dev = pci_get_drvdata(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005856 struct fe_priv *np = netdev_priv(dev);
5857 u8 __iomem *base = get_hwbase(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005858
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005859 /* special op: write back the misordered MAC address - otherwise
5860 * the next nv_probe would see a wrong address.
5861 */
5862 writel(np->orig_mac[0], base + NvRegMacAddrA);
5863 writel(np->orig_mac[1], base + NvRegMacAddrB);
Björn Steinbrink2e3884b2008-01-07 23:22:53 -08005864 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5865 base + NvRegTransmitPoll);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005866}
5867
5868static void __devexit nv_remove(struct pci_dev *pci_dev)
5869{
5870 struct net_device *dev = pci_get_drvdata(pci_dev);
5871
5872 unregister_netdev(dev);
5873
5874 nv_restore_mac_addr(pci_dev);
Ayaz Abdullaf1489652006-07-31 12:04:45 -04005875
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04005876 /* restore any phy related changes */
5877 nv_restore_phy(dev);
5878
Ayaz Abdullacac1c522009-02-07 00:23:57 -08005879 nv_mgmt_release_sema(dev);
5880
Linus Torvalds1da177e2005-04-16 15:20:36 -07005881 /* free all structures */
Ayaz Abdullaeafa59f2006-06-10 22:47:34 -04005882 free_rings(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005883 iounmap(get_hwbase(dev));
5884 pci_release_regions(pci_dev);
5885 pci_disable_device(pci_dev);
5886 free_netdev(dev);
5887 pci_set_drvdata(pci_dev, NULL);
5888}
5889
Francois Romieua1893172006-10-10 14:33:27 -07005890#ifdef CONFIG_PM
5891static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5892{
5893 struct net_device *dev = pci_get_drvdata(pdev);
5894 struct fe_priv *np = netdev_priv(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005895 u8 __iomem *base = get_hwbase(dev);
5896 int i;
Francois Romieua1893172006-10-10 14:33:27 -07005897
Tobias Diedrich25d90812008-05-18 15:04:29 +02005898 if (netif_running(dev)) {
Szymon Janc78aea4f2010-11-27 08:39:43 +00005899 /* Gross. */
Tobias Diedrich25d90812008-05-18 15:04:29 +02005900 nv_close(dev);
5901 }
Francois Romieua1893172006-10-10 14:33:27 -07005902 netif_device_detach(dev);
5903
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005904 /* save non-pci configuration space */
Szymon Janc78aea4f2010-11-27 08:39:43 +00005905 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005906 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5907
Francois Romieua1893172006-10-10 14:33:27 -07005908 pci_save_state(pdev);
5909 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
Tobias Diedrich25d90812008-05-18 15:04:29 +02005910 pci_disable_device(pdev);
Francois Romieua1893172006-10-10 14:33:27 -07005911 pci_set_power_state(pdev, pci_choose_state(pdev, state));
Francois Romieua1893172006-10-10 14:33:27 -07005912 return 0;
5913}
5914
5915static int nv_resume(struct pci_dev *pdev)
5916{
5917 struct net_device *dev = pci_get_drvdata(pdev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005918 struct fe_priv *np = netdev_priv(dev);
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005919 u8 __iomem *base = get_hwbase(dev);
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005920 int i, rc = 0;
Francois Romieua1893172006-10-10 14:33:27 -07005921
Francois Romieua1893172006-10-10 14:33:27 -07005922 pci_set_power_state(pdev, PCI_D0);
5923 pci_restore_state(pdev);
Tobias Diedrich25d90812008-05-18 15:04:29 +02005924 /* ack any pending wake events, disable PME */
Francois Romieua1893172006-10-10 14:33:27 -07005925 pci_enable_wake(pdev, PCI_D0, 0);
5926
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005927 /* restore non-pci configuration space */
Szymon Janc78aea4f2010-11-27 08:39:43 +00005928 for (i = 0; i <= np->register_size/sizeof(u32); i++)
Tobias Diedrich1a1ca862008-05-18 15:03:44 +02005929 writel(np->saved_config_space[i], base+i*sizeof(u32));
Ayaz Abdullaa376e792008-04-10 21:30:35 -07005930
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005931 if (np->driver_data & DEV_NEED_MSI_FIX)
5932 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
Ayaz Abdullab6e44052009-02-07 00:24:15 -08005933
Ed Swierk35a74332009-04-06 17:49:12 -07005934 /* restore phy state, including autoneg */
5935 phy_init(dev);
5936
Tobias Diedrich25d90812008-05-18 15:04:29 +02005937 netif_device_attach(dev);
5938 if (netif_running(dev)) {
5939 rc = nv_open(dev);
5940 nv_set_multicast(dev);
5941 }
Francois Romieua1893172006-10-10 14:33:27 -07005942 return rc;
5943}
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005944
5945static void nv_shutdown(struct pci_dev *pdev)
5946{
5947 struct net_device *dev = pci_get_drvdata(pdev);
5948 struct fe_priv *np = netdev_priv(dev);
5949
5950 if (netif_running(dev))
5951 nv_close(dev);
5952
Tobias Diedrich34edaa82009-02-16 00:13:20 -08005953 /*
5954 * Restore the MAC so a kernel started by kexec won't get confused.
5955 * If we really go for poweroff, we must not restore the MAC,
5956 * otherwise the MAC for WOL will be reversed at least on some boards.
5957 */
Szymon Janc78aea4f2010-11-27 08:39:43 +00005958 if (system_state != SYSTEM_POWER_OFF)
Tobias Diedrich34edaa82009-02-16 00:13:20 -08005959 nv_restore_mac_addr(pdev);
Yinghai Luf55c21f2008-09-13 13:10:31 -07005960
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005961 pci_disable_device(pdev);
Tobias Diedrich34edaa82009-02-16 00:13:20 -08005962 /*
5963 * Apparently it is not possible to reinitialise from D3 hot,
5964 * only put the device into D3 if we really go for poweroff.
5965 */
Rafael J. Wysocki3cb55992008-09-05 14:00:19 -07005966 if (system_state == SYSTEM_POWER_OFF) {
5967 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
5968 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
5969 pci_set_power_state(pdev, PCI_D3hot);
5970 }
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005971}
Francois Romieua1893172006-10-10 14:33:27 -07005972#else
5973#define nv_suspend NULL
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02005974#define nv_shutdown NULL
Francois Romieua1893172006-10-10 14:33:27 -07005975#define nv_resume NULL
5976#endif /* CONFIG_PM */
5977
Alexey Dobriyana3aa1882010-01-07 11:58:11 +00005978static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005979 { /* nForce Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005980 PCI_DEVICE(0x10DE, 0x01C3),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005981 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005982 },
5983 { /* nForce2 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005984 PCI_DEVICE(0x10DE, 0x0066),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005985 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005986 },
5987 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005988 PCI_DEVICE(0x10DE, 0x00D6),
Manfred Spraulc2dba062005-07-31 18:29:47 +02005989 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005990 },
5991 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005992 PCI_DEVICE(0x10DE, 0x0086),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005993 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005994 },
5995 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00005996 PCI_DEVICE(0x10DE, 0x008C),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04005997 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005998 },
5999 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006000 PCI_DEVICE(0x10DE, 0x00E6),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006001 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006002 },
6003 { /* nForce3 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006004 PCI_DEVICE(0x10DE, 0x00DF),
Manfred Spraul8a4ae7f2005-09-21 23:22:10 -04006005 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006006 },
6007 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006008 PCI_DEVICE(0x10DE, 0x0056),
Yinghai Lu033e97b2009-02-06 01:30:56 -08006009 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006010 },
6011 { /* CK804 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006012 PCI_DEVICE(0x10DE, 0x0057),
Yinghai Lu033e97b2009-02-06 01:30:56 -08006013 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006014 },
6015 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006016 PCI_DEVICE(0x10DE, 0x0037),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006017 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006018 },
6019 { /* MCP04 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006020 PCI_DEVICE(0x10DE, 0x0038),
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006021 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
Manfred Sprauldc8216c2005-07-31 18:26:05 +02006022 },
6023 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006024 PCI_DEVICE(0x10DE, 0x0268),
6025 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006026 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006027 { /* MCP51 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006028 PCI_DEVICE(0x10DE, 0x0269),
6029 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02006030 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006031 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006032 PCI_DEVICE(0x10DE, 0x0372),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006033 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006034 },
6035 { /* MCP55 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006036 PCI_DEVICE(0x10DE, 0x0373),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006037 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
Manfred Spraulf49d16e2005-06-26 11:36:52 +02006038 },
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006039 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006040 PCI_DEVICE(0x10DE, 0x03E5),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006041 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006042 },
6043 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006044 PCI_DEVICE(0x10DE, 0x03E6),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006045 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006046 },
6047 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006048 PCI_DEVICE(0x10DE, 0x03EE),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006049 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006050 },
6051 { /* MCP61 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006052 PCI_DEVICE(0x10DE, 0x03EF),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006053 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006054 },
6055 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006056 PCI_DEVICE(0x10DE, 0x0450),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006057 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006058 },
6059 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006060 PCI_DEVICE(0x10DE, 0x0451),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006061 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006062 },
6063 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006064 PCI_DEVICE(0x10DE, 0x0452),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006065 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006066 },
6067 { /* MCP65 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006068 PCI_DEVICE(0x10DE, 0x0453),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006069 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullac99ce7e2006-06-10 22:48:28 -04006070 },
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006071 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006072 PCI_DEVICE(0x10DE, 0x054C),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006073 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006074 },
6075 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006076 PCI_DEVICE(0x10DE, 0x054D),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006077 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006078 },
6079 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006080 PCI_DEVICE(0x10DE, 0x054E),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006081 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006082 },
6083 { /* MCP67 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006084 PCI_DEVICE(0x10DE, 0x054F),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006085 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdullaf4344842006-11-06 00:43:40 -08006086 },
Ayaz Abdulla13986612007-07-22 20:43:26 -04006087 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006088 PCI_DEVICE(0x10DE, 0x07DC),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006089 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006090 },
6091 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006092 PCI_DEVICE(0x10DE, 0x07DD),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006093 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006094 },
6095 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006096 PCI_DEVICE(0x10DE, 0x07DE),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006097 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006098 },
6099 { /* MCP73 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006100 PCI_DEVICE(0x10DE, 0x07DF),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006101 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
Ayaz Abdulla13986612007-07-22 20:43:26 -04006102 },
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006103 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006104 PCI_DEVICE(0x10DE, 0x0760),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006105 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006106 },
6107 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006108 PCI_DEVICE(0x10DE, 0x0761),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006109 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006110 },
6111 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006112 PCI_DEVICE(0x10DE, 0x0762),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006113 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006114 },
6115 { /* MCP77 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006116 PCI_DEVICE(0x10DE, 0x0763),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006117 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla96fd4cd2007-10-25 03:36:42 -04006118 },
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006119 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006120 PCI_DEVICE(0x10DE, 0x0AB0),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006121 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006122 },
6123 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006124 PCI_DEVICE(0x10DE, 0x0AB1),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006125 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006126 },
6127 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006128 PCI_DEVICE(0x10DE, 0x0AB2),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006129 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006130 },
6131 { /* MCP79 Ethernet Controller */
Ayaz Abdulla3c2e1c12009-06-03 15:05:17 +00006132 PCI_DEVICE(0x10DE, 0x0AB3),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006133 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
Ayaz Abdulla490dde82007-11-23 20:54:01 -05006134 },
Ayaz Abdulla3df81c42009-06-03 15:05:35 +00006135 { /* MCP89 Ethernet Controller */
6136 PCI_DEVICE(0x10DE, 0x0D7D),
Mike Ditto7b5e0782010-07-25 21:54:28 -07006137 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
Ayaz Abdulla3df81c42009-06-03 15:05:35 +00006138 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07006139 {0,},
6140};
6141
6142static struct pci_driver driver = {
Jeff Garzik3f88ce42007-10-16 04:09:09 -04006143 .name = DRV_NAME,
6144 .id_table = pci_tbl,
6145 .probe = nv_probe,
6146 .remove = __devexit_p(nv_remove),
6147 .suspend = nv_suspend,
6148 .resume = nv_resume,
Tobias Diedrichf735a2a2008-05-18 15:02:37 +02006149 .shutdown = nv_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07006150};
6151
Linus Torvalds1da177e2005-04-16 15:20:36 -07006152static int __init init_nic(void)
6153{
Jeff Garzik29917622006-08-19 17:48:59 -04006154 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006155}
6156
6157static void __exit exit_nic(void)
6158{
6159 pci_unregister_driver(&driver);
6160}
6161
6162module_param(max_interrupt_work, int, 0);
6163MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006164module_param(optimization_mode, int, 0);
Ayaz Abdulla9e184762009-03-05 08:02:18 +00006165MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
Ayaz Abdullaa971c322005-11-11 08:30:38 -05006166module_param(poll_interval, int, 0);
6167MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
Ayaz Abdulla69fe3fd2006-06-10 22:48:18 -04006168module_param(msi, int, 0);
6169MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6170module_param(msix, int, 0);
6171MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6172module_param(dma_64bit, int, 0);
6173MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
Ayaz Abdulla9f3f7912008-04-23 14:37:30 -04006174module_param(phy_cross, int, 0);
6175MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
Ed Swierk5a9a8e32009-06-02 00:19:52 -07006176module_param(phy_power_down, int, 0);
6177MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
Linus Torvalds1da177e2005-04-16 15:20:36 -07006178
6179MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6180MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6181MODULE_LICENSE("GPL");
6182
6183MODULE_DEVICE_TABLE(pci, pci_tbl);
6184
6185module_init(init_nic);
6186module_exit(exit_nic);