Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/chip.c |
| 3 | * |
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King |
| 6 | * |
| 7 | * This file contains the core interrupt handling code, for irq-chip |
| 8 | * based architectures. |
| 9 | * |
| 10 | * Detailed information is available in Documentation/DocBook/genericirq |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/kernel_stat.h> |
| 18 | |
| 19 | #include "internals.h" |
| 20 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 21 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 22 | * irq_set_chip - set the irq chip for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 23 | * @irq: irq number |
| 24 | * @chip: pointer to irq chip description structure |
| 25 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 27 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 28 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 29 | unsigned long flags; |
| 30 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 31 | if (!desc) { |
Arjan van de Ven | 261c40c | 2008-07-25 19:45:37 -0700 | [diff] [blame] | 32 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 33 | return -EINVAL; |
| 34 | } |
| 35 | |
| 36 | if (!chip) |
| 37 | chip = &no_irq_chip; |
| 38 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 39 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 40 | irq_chip_set_defaults(chip); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 41 | desc->irq_data.chip = chip; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 42 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 43 | |
| 44 | return 0; |
| 45 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 46 | EXPORT_SYMBOL(irq_set_chip); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 47 | |
| 48 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 49 | * irq_set_type - set the irq trigger type for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 50 | * @irq: irq number |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 51 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 52 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 53 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 54 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 55 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 56 | unsigned long flags; |
| 57 | int ret = -ENXIO; |
| 58 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 59 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 60 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
| 61 | return -ENODEV; |
| 62 | } |
| 63 | |
David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 64 | type &= IRQ_TYPE_SENSE_MASK; |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 65 | if (type == IRQ_TYPE_NONE) |
| 66 | return 0; |
| 67 | |
Thomas Gleixner | 43abe43 | 2011-02-12 12:10:49 +0100 | [diff] [blame] | 68 | chip_bus_lock(desc); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 69 | raw_spin_lock_irqsave(&desc->lock, flags); |
Chris Friesen | 0b3682ba3 | 2008-10-20 12:41:58 -0600 | [diff] [blame] | 70 | ret = __irq_set_trigger(desc, irq, type); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 71 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | 43abe43 | 2011-02-12 12:10:49 +0100 | [diff] [blame] | 72 | chip_bus_sync_unlock(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 73 | return ret; |
| 74 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 75 | EXPORT_SYMBOL(irq_set_irq_type); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 76 | |
| 77 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 78 | * irq_set_handler_data - set irq handler data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 79 | * @irq: Interrupt number |
| 80 | * @data: Pointer to interrupt specific data |
| 81 | * |
| 82 | * Set the hardware irq controller data for an irq |
| 83 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 84 | int irq_set_handler_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 85 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 86 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 87 | unsigned long flags; |
| 88 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 89 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 90 | printk(KERN_ERR |
| 91 | "Trying to install controller data for IRQ%d\n", irq); |
| 92 | return -EINVAL; |
| 93 | } |
| 94 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 95 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 96 | desc->irq_data.handler_data = data; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 97 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 98 | return 0; |
| 99 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 100 | EXPORT_SYMBOL(irq_set_handler_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 101 | |
| 102 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 103 | * irq_set_msi_desc - set MSI descriptor data for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 104 | * @irq: Interrupt number |
Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 105 | * @entry: Pointer to MSI descriptor data |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 106 | * |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 107 | * Set the MSI descriptor entry for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 108 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 109 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 110 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 111 | struct irq_desc *desc = irq_to_desc(irq); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 112 | unsigned long flags; |
| 113 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 114 | if (!desc) { |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 115 | printk(KERN_ERR |
| 116 | "Trying to install msi data for IRQ%d\n", irq); |
| 117 | return -EINVAL; |
| 118 | } |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 119 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 120 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 121 | desc->irq_data.msi_desc = entry; |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 122 | if (entry) |
| 123 | entry->irq = irq; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 124 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 125 | return 0; |
| 126 | } |
| 127 | |
| 128 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 129 | * irq_set_chip_data - set irq chip data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 130 | * @irq: Interrupt number |
| 131 | * @data: Pointer to chip specific data |
| 132 | * |
| 133 | * Set the hardware irq chip data for an irq |
| 134 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 135 | int irq_set_chip_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 136 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 137 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 138 | unsigned long flags; |
| 139 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 140 | if (!desc) { |
| 141 | printk(KERN_ERR |
| 142 | "Trying to install chip data for IRQ%d\n", irq); |
| 143 | return -EINVAL; |
| 144 | } |
| 145 | |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 146 | if (!desc->irq_data.chip) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 147 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
| 148 | return -EINVAL; |
| 149 | } |
| 150 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 151 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 152 | desc->irq_data.chip_data = data; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 153 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 154 | |
| 155 | return 0; |
| 156 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 157 | EXPORT_SYMBOL(irq_set_chip_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 158 | |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 159 | struct irq_data *irq_get_irq_data(unsigned int irq) |
| 160 | { |
| 161 | struct irq_desc *desc = irq_to_desc(irq); |
| 162 | |
| 163 | return desc ? &desc->irq_data : NULL; |
| 164 | } |
| 165 | EXPORT_SYMBOL_GPL(irq_get_irq_data); |
| 166 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 167 | static void irq_state_clr_disabled(struct irq_desc *desc) |
| 168 | { |
| 169 | desc->istate &= ~IRQS_DISABLED; |
| 170 | irq_compat_clr_disabled(desc); |
| 171 | } |
| 172 | |
| 173 | static void irq_state_set_disabled(struct irq_desc *desc) |
| 174 | { |
| 175 | desc->istate |= IRQS_DISABLED; |
| 176 | irq_compat_set_disabled(desc); |
| 177 | } |
| 178 | |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame^] | 179 | static void irq_state_clr_masked(struct irq_desc *desc) |
| 180 | { |
| 181 | desc->istate &= ~IRQS_MASKED; |
| 182 | irq_compat_clr_masked(desc); |
| 183 | } |
| 184 | |
| 185 | static void irq_state_set_masked(struct irq_desc *desc) |
| 186 | { |
| 187 | desc->istate |= IRQS_MASKED; |
| 188 | irq_compat_set_masked(desc); |
| 189 | } |
| 190 | |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 191 | int irq_startup(struct irq_desc *desc) |
| 192 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 193 | irq_state_clr_disabled(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 194 | desc->depth = 0; |
| 195 | |
Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 196 | if (desc->irq_data.chip->irq_startup) { |
| 197 | int ret = desc->irq_data.chip->irq_startup(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame^] | 198 | irq_state_clr_masked(desc); |
Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 199 | return ret; |
| 200 | } |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 201 | |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 202 | irq_enable(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 203 | return 0; |
| 204 | } |
| 205 | |
| 206 | void irq_shutdown(struct irq_desc *desc) |
| 207 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 208 | irq_state_set_disabled(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 209 | desc->depth = 1; |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 210 | if (desc->irq_data.chip->irq_shutdown) |
| 211 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); |
| 212 | if (desc->irq_data.chip->irq_disable) |
| 213 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
| 214 | else |
| 215 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame^] | 216 | irq_state_set_masked(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 217 | } |
| 218 | |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 219 | void irq_enable(struct irq_desc *desc) |
| 220 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 221 | irq_state_clr_disabled(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 222 | if (desc->irq_data.chip->irq_enable) |
| 223 | desc->irq_data.chip->irq_enable(&desc->irq_data); |
| 224 | else |
| 225 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame^] | 226 | irq_state_clr_masked(desc); |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 227 | } |
| 228 | |
| 229 | void irq_disable(struct irq_desc *desc) |
| 230 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 231 | irq_state_set_disabled(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 232 | if (desc->irq_data.chip->irq_disable) { |
| 233 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 234 | } |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame^] | 235 | irq_state_set_masked(desc); |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 236 | } |
| 237 | |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 238 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 239 | /* Temporary migration helpers */ |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 240 | static void compat_irq_mask(struct irq_data *data) |
| 241 | { |
| 242 | data->chip->mask(data->irq); |
| 243 | } |
| 244 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 245 | static void compat_irq_unmask(struct irq_data *data) |
| 246 | { |
| 247 | data->chip->unmask(data->irq); |
| 248 | } |
| 249 | |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 250 | static void compat_irq_ack(struct irq_data *data) |
| 251 | { |
| 252 | data->chip->ack(data->irq); |
| 253 | } |
| 254 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 255 | static void compat_irq_mask_ack(struct irq_data *data) |
| 256 | { |
| 257 | data->chip->mask_ack(data->irq); |
| 258 | } |
| 259 | |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 260 | static void compat_irq_eoi(struct irq_data *data) |
| 261 | { |
| 262 | data->chip->eoi(data->irq); |
| 263 | } |
| 264 | |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 265 | static void compat_irq_enable(struct irq_data *data) |
| 266 | { |
| 267 | data->chip->enable(data->irq); |
| 268 | } |
| 269 | |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 270 | static void compat_irq_disable(struct irq_data *data) |
| 271 | { |
| 272 | data->chip->disable(data->irq); |
| 273 | } |
| 274 | |
| 275 | static void compat_irq_shutdown(struct irq_data *data) |
| 276 | { |
| 277 | data->chip->shutdown(data->irq); |
| 278 | } |
| 279 | |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 280 | static unsigned int compat_irq_startup(struct irq_data *data) |
| 281 | { |
| 282 | return data->chip->startup(data->irq); |
| 283 | } |
| 284 | |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 285 | static int compat_irq_set_affinity(struct irq_data *data, |
| 286 | const struct cpumask *dest, bool force) |
| 287 | { |
| 288 | return data->chip->set_affinity(data->irq, dest); |
| 289 | } |
| 290 | |
Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 291 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
| 292 | { |
| 293 | return data->chip->set_type(data->irq, type); |
| 294 | } |
| 295 | |
Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame] | 296 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
| 297 | { |
| 298 | return data->chip->set_wake(data->irq, on); |
| 299 | } |
| 300 | |
Thomas Gleixner | 21e2b8c | 2010-09-27 12:45:53 +0000 | [diff] [blame] | 301 | static int compat_irq_retrigger(struct irq_data *data) |
| 302 | { |
| 303 | return data->chip->retrigger(data->irq); |
| 304 | } |
| 305 | |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 306 | static void compat_bus_lock(struct irq_data *data) |
| 307 | { |
| 308 | data->chip->bus_lock(data->irq); |
| 309 | } |
| 310 | |
| 311 | static void compat_bus_sync_unlock(struct irq_data *data) |
| 312 | { |
| 313 | data->chip->bus_sync_unlock(data->irq); |
| 314 | } |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 315 | #endif |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 316 | |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 317 | /* |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 318 | * Fixup enable/disable function pointers |
| 319 | */ |
| 320 | void irq_chip_set_defaults(struct irq_chip *chip) |
| 321 | { |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 322 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 323 | if (chip->enable) |
| 324 | chip->irq_enable = compat_irq_enable; |
Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 325 | if (chip->disable) |
| 326 | chip->irq_disable = compat_irq_disable; |
| 327 | if (chip->shutdown) |
| 328 | chip->irq_shutdown = compat_irq_shutdown; |
Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 329 | if (chip->startup) |
| 330 | chip->irq_startup = compat_irq_startup; |
Zhang, Yanmin | b86432b | 2006-11-16 01:19:10 -0800 | [diff] [blame] | 331 | if (!chip->end) |
| 332 | chip->end = dummy_irq_chip.end; |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 333 | if (chip->bus_lock) |
| 334 | chip->irq_bus_lock = compat_bus_lock; |
| 335 | if (chip->bus_sync_unlock) |
| 336 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 337 | if (chip->mask) |
| 338 | chip->irq_mask = compat_irq_mask; |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 339 | if (chip->unmask) |
| 340 | chip->irq_unmask = compat_irq_unmask; |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 341 | if (chip->ack) |
| 342 | chip->irq_ack = compat_irq_ack; |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 343 | if (chip->mask_ack) |
| 344 | chip->irq_mask_ack = compat_irq_mask_ack; |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 345 | if (chip->eoi) |
| 346 | chip->irq_eoi = compat_irq_eoi; |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 347 | if (chip->set_affinity) |
| 348 | chip->irq_set_affinity = compat_irq_set_affinity; |
Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 349 | if (chip->set_type) |
| 350 | chip->irq_set_type = compat_irq_set_type; |
Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame] | 351 | if (chip->set_wake) |
| 352 | chip->irq_set_wake = compat_irq_set_wake; |
Thomas Gleixner | 21e2b8c | 2010-09-27 12:45:53 +0000 | [diff] [blame] | 353 | if (chip->retrigger) |
| 354 | chip->irq_retrigger = compat_irq_retrigger; |
Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 355 | #endif |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 356 | } |
| 357 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 358 | static inline void mask_ack_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 359 | { |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 360 | if (desc->irq_data.chip->irq_mask_ack) |
| 361 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 362 | else { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 363 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 364 | if (desc->irq_data.chip->irq_ack) |
| 365 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 366 | } |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame^] | 367 | irq_state_set_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 368 | } |
| 369 | |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 370 | static inline void mask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 371 | { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 372 | if (desc->irq_data.chip->irq_mask) { |
| 373 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame^] | 374 | irq_state_set_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 375 | } |
| 376 | } |
| 377 | |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 378 | static inline void unmask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 379 | { |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 380 | if (desc->irq_data.chip->irq_unmask) { |
| 381 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame^] | 382 | irq_state_clr_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 383 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 384 | } |
| 385 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 386 | /* |
| 387 | * handle_nested_irq - Handle a nested irq from a irq thread |
| 388 | * @irq: the interrupt number |
| 389 | * |
| 390 | * Handle interrupts which are nested into a threaded interrupt |
| 391 | * handler. The handler function is called inside the calling |
| 392 | * threads context. |
| 393 | */ |
| 394 | void handle_nested_irq(unsigned int irq) |
| 395 | { |
| 396 | struct irq_desc *desc = irq_to_desc(irq); |
| 397 | struct irqaction *action; |
| 398 | irqreturn_t action_ret; |
| 399 | |
| 400 | might_sleep(); |
| 401 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 402 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 403 | |
| 404 | kstat_incr_irqs_this_cpu(irq, desc); |
| 405 | |
| 406 | action = desc->action; |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 407 | if (unlikely(!action || (desc->istate & IRQS_DISABLED))) |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 408 | goto out_unlock; |
| 409 | |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 410 | irq_compat_set_progress(desc); |
| 411 | desc->istate |= IRQS_INPROGRESS; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 412 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 413 | |
| 414 | action_ret = action->thread_fn(action->irq, action->dev_id); |
| 415 | if (!noirqdebug) |
| 416 | note_interrupt(irq, desc, action_ret); |
| 417 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 418 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 419 | desc->istate &= ~IRQS_INPROGRESS; |
| 420 | irq_compat_clr_progress(desc); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 421 | |
| 422 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 423 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 424 | } |
| 425 | EXPORT_SYMBOL_GPL(handle_nested_irq); |
| 426 | |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 427 | static bool irq_check_poll(struct irq_desc *desc) |
| 428 | { |
Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 429 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 430 | return false; |
| 431 | return irq_wait_for_poll(desc); |
| 432 | } |
| 433 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 434 | /** |
| 435 | * handle_simple_irq - Simple and software-decoded IRQs. |
| 436 | * @irq: the interrupt number |
| 437 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 438 | * |
| 439 | * Simple interrupts are either sent from a demultiplexing interrupt |
| 440 | * handler or come from hardware, where no interrupt hardware control |
| 441 | * is necessary. |
| 442 | * |
| 443 | * Note: The caller is expected to handle the ack, clear, mask and |
| 444 | * unmask issues if necessary. |
| 445 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 446 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 447 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 448 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 449 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 450 | |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 451 | if (unlikely(desc->istate & IRQS_INPROGRESS)) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 452 | if (!irq_check_poll(desc)) |
| 453 | goto out_unlock; |
| 454 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 455 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 456 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 457 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 458 | if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 459 | goto out_unlock; |
| 460 | |
Thomas Gleixner | 107781e | 2011-02-07 01:21:02 +0100 | [diff] [blame] | 461 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 462 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 463 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 464 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 465 | } |
| 466 | |
| 467 | /** |
| 468 | * handle_level_irq - Level type irq handler |
| 469 | * @irq: the interrupt number |
| 470 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 471 | * |
| 472 | * Level type interrupts are active as long as the hardware line has |
| 473 | * the active level. This may require to mask the interrupt and unmask |
| 474 | * it after the associated handler has acknowledged the device, so the |
| 475 | * interrupt line is back to inactive. |
| 476 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 477 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 478 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 479 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 480 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 481 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 482 | |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 483 | if (unlikely(desc->istate & IRQS_INPROGRESS)) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 484 | if (!irq_check_poll(desc)) |
| 485 | goto out_unlock; |
| 486 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 487 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 488 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 489 | |
| 490 | /* |
| 491 | * If its disabled or no action available |
| 492 | * keep it masked and get out of here |
| 493 | */ |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 494 | if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 495 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 496 | |
Thomas Gleixner | 1529866 | 2011-02-07 01:22:17 +0100 | [diff] [blame] | 497 | handle_irq_event(desc); |
Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 498 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 499 | if (!(desc->istate & (IRQS_DISABLED | IRQS_ONESHOT))) |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 500 | unmask_irq(desc); |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 501 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 502 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 503 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 504 | EXPORT_SYMBOL_GPL(handle_level_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 505 | |
| 506 | /** |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 507 | * handle_fasteoi_irq - irq handler for transparent controllers |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 508 | * @irq: the interrupt number |
| 509 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 510 | * |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 511 | * Only a single callback will be issued to the chip: an ->eoi() |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 512 | * call when the interrupt has been serviced. This enables support |
| 513 | * for modern forms of interrupt handlers, which handle the flow |
| 514 | * details in hardware, transparently. |
| 515 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 516 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 517 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 518 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 519 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 520 | |
Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 521 | if (unlikely(desc->istate & IRQS_INPROGRESS)) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 522 | if (!irq_check_poll(desc)) |
| 523 | goto out; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 524 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 525 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 526 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 527 | |
| 528 | /* |
| 529 | * If its disabled or no action available |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 530 | * then mask it and get out of here: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 531 | */ |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 532 | if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) { |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 533 | irq_compat_set_pending(desc); |
| 534 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 535 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 536 | goto out; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 537 | } |
Thomas Gleixner | a7ae4de | 2011-02-07 01:23:07 +0100 | [diff] [blame] | 538 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 539 | out: |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 540 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 541 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 542 | } |
| 543 | |
| 544 | /** |
| 545 | * handle_edge_irq - edge type IRQ handler |
| 546 | * @irq: the interrupt number |
| 547 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 548 | * |
| 549 | * Interrupt occures on the falling and/or rising edge of a hardware |
| 550 | * signal. The occurence is latched into the irq controller hardware |
| 551 | * and must be acked in order to be reenabled. After the ack another |
| 552 | * interrupt can happen on the same source even before the first one |
Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 553 | * is handled by the associated event handler. If this happens it |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 554 | * might be necessary to disable (mask) the interrupt depending on the |
| 555 | * controller hardware. This requires to reenable the interrupt inside |
| 556 | * of the loop which handles the interrupts which have arrived while |
| 557 | * the handler was running. If all pending interrupts are handled, the |
| 558 | * loop is left. |
| 559 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 560 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 561 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 562 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 563 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 564 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 565 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 566 | /* |
| 567 | * If we're currently running this IRQ, or its disabled, |
| 568 | * we shouldn't process the IRQ. Mark it pending, handle |
| 569 | * the necessary masking and go out |
| 570 | */ |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 571 | if (unlikely((desc->istate & (IRQS_DISABLED | IRQS_INPROGRESS) || |
| 572 | !desc->action))) { |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 573 | if (!irq_check_poll(desc)) { |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 574 | irq_compat_set_pending(desc); |
| 575 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 576 | mask_ack_irq(desc); |
| 577 | goto out_unlock; |
| 578 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 579 | } |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 580 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 581 | |
| 582 | /* Start handling the irq */ |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 583 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 584 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 585 | do { |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 586 | if (unlikely(!desc->action)) { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 587 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 588 | goto out_unlock; |
| 589 | } |
| 590 | |
| 591 | /* |
| 592 | * When another irq arrived while we were handling |
| 593 | * one, we could have masked the irq. |
| 594 | * Renable it, if it was not disabled in meantime. |
| 595 | */ |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 596 | if (unlikely(desc->istate & IRQS_PENDING)) { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 597 | if (!(desc->istate & IRQS_DISABLED) && |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame^] | 598 | (desc->istate & IRQS_MASKED)) |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 599 | unmask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 600 | } |
| 601 | |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 602 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 603 | |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 604 | } while ((desc->istate & IRQS_PENDING) && |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 605 | !(desc->istate & IRQS_DISABLED)); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 606 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 607 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 608 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 609 | } |
| 610 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 611 | /** |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 612 | * handle_percpu_irq - Per CPU local irq handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 613 | * @irq: the interrupt number |
| 614 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 615 | * |
| 616 | * Per CPU interrupts on SMP machines without locking requirements |
| 617 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 618 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 619 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 620 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 621 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 622 | |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 623 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 624 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 625 | if (chip->irq_ack) |
| 626 | chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 627 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 628 | handle_irq_event_percpu(desc, desc->action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 629 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 630 | if (chip->irq_eoi) |
| 631 | chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 632 | } |
| 633 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 634 | void |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 635 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
| 636 | const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 637 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 638 | struct irq_desc *desc = irq_to_desc(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 639 | unsigned long flags; |
| 640 | |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 641 | if (!desc) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 642 | printk(KERN_ERR |
| 643 | "Trying to install type control for IRQ%d\n", irq); |
| 644 | return; |
| 645 | } |
| 646 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 647 | if (!handle) |
| 648 | handle = handle_bad_irq; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 649 | else if (desc->irq_data.chip == &no_irq_chip) { |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 650 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
Geert Uytterhoeven | b039db8 | 2006-12-20 15:59:48 +0100 | [diff] [blame] | 651 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 652 | /* |
| 653 | * Some ARM implementations install a handler for really dumb |
| 654 | * interrupt hardware without setting an irq_chip. This worked |
| 655 | * with the ARM no_irq_chip but the check in setup_irq would |
| 656 | * prevent us to setup the interrupt at all. Switch it to |
| 657 | * dummy_irq_chip for easy transition. |
| 658 | */ |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 659 | desc->irq_data.chip = &dummy_irq_chip; |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 660 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 661 | |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 662 | chip_bus_lock(desc); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 663 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 664 | |
| 665 | /* Uninstall? */ |
| 666 | if (handle == handle_bad_irq) { |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 667 | if (desc->irq_data.chip != &no_irq_chip) |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 668 | mask_ack_irq(desc); |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 669 | irq_compat_set_disabled(desc); |
| 670 | desc->istate |= IRQS_DISABLED; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 671 | desc->depth = 1; |
| 672 | } |
| 673 | desc->handle_irq = handle; |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 674 | desc->name = name; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 675 | |
| 676 | if (handle != handle_bad_irq && is_chained) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 677 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 678 | irq_startup(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 679 | } |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 680 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 681 | chip_bus_sync_unlock(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 682 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 683 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 684 | |
| 685 | void |
| 686 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
David Howells | 57a58a9 | 2006-10-05 13:06:34 +0100 | [diff] [blame] | 687 | irq_flow_handler_t handle) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 688 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 689 | irq_set_chip(irq, chip); |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 690 | __set_irq_handler(irq, handle, 0, NULL); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 691 | } |
| 692 | |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 693 | void |
| 694 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
| 695 | irq_flow_handler_t handle, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 696 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 697 | irq_set_chip(irq, chip); |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 698 | __set_irq_handler(irq, handle, 0, name); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 699 | } |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 700 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 701 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 702 | { |
Thomas Gleixner | d3c6004 | 2008-10-16 09:55:00 +0200 | [diff] [blame] | 703 | struct irq_desc *desc = irq_to_desc(irq); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 704 | unsigned long flags; |
| 705 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 706 | if (!desc) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 707 | return; |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 708 | |
| 709 | /* Sanitize flags */ |
| 710 | set &= IRQF_MODIFY_MASK; |
| 711 | clr &= IRQF_MODIFY_MASK; |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 712 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 713 | raw_spin_lock_irqsave(&desc->lock, flags); |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 714 | desc->status &= ~clr; |
| 715 | desc->status |= set; |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 716 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 717 | } |