Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_oneplus_msm8996 / 6e7b429259fc0b7f2d9b1147466656b34d114815 / . / drivers / scsi / qla4xxx / ql4_83xx.h
blob: a67926383940f91dc1b89d86b4a8306a718ce143 [file] [log] [blame]
Vikas Chaudhary6e7b4292012-08-22 07:55:08 -0400[diff] [blame^]1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2012 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#ifndef __QL483XX_H
9#define __QL483XX_H
10
11/* Indirectly Mapped Registers */
12#define QLA83XX_FLASH_SPI_STATUS 0x2808E010
13#define QLA83XX_FLASH_SPI_CONTROL 0x2808E014
14#define QLA83XX_FLASH_STATUS 0x42100004
15#define QLA83XX_FLASH_CONTROL 0x42110004
16#define QLA83XX_FLASH_ADDR 0x42110008
17#define QLA83XX_FLASH_WRDATA 0x4211000C
18#define QLA83XX_FLASH_RDDATA 0x42110018
19#define QLA83XX_FLASH_DIRECT_WINDOW 0x42110030
20#define QLA83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
21
22/* Directly Mapped Registers in 83xx register table */
23
24/* Flash access regs */
25#define QLA83XX_FLASH_LOCK 0x3850
26#define QLA83XX_FLASH_UNLOCK 0x3854
27#define QLA83XX_FLASH_LOCK_ID 0x3500
28
29/* Driver Lock regs */
30#define QLA83XX_DRV_LOCK 0x3868
31#define QLA83XX_DRV_UNLOCK 0x386C
32#define QLA83XX_DRV_LOCK_ID 0x3504
33#define QLA83XX_DRV_LOCKRECOVERY 0x379C
34
35/* IDC version */
36#define QLA83XX_IDC_VER_MAJ_VALUE 0x1
37#define QLA83XX_IDC_VER_MIN_VALUE 0x0
38
39/* IDC Registers : Driver Coexistence Defines */
40#define QLA83XX_CRB_IDC_VER_MAJOR 0x3780
41#define QLA83XX_CRB_IDC_VER_MINOR 0x3798
42#define QLA83XX_IDC_DRV_CTRL 0x3790
43#define QLA83XX_IDC_DRV_AUDIT 0x3794
44
45/* qla_83xx_reg_tbl registers */
46#define QLA83XX_PEG_HALT_STATUS1 0x34A8
47#define QLA83XX_PEG_HALT_STATUS2 0x34AC
48#define QLA83XX_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
49#define QLA83XX_FW_CAPABILITIES 0x3528
50#define QLA83XX_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
51#define QLA83XX_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
52#define QLA83XX_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
53#define QLA83XX_CRB_DRV_SCRATCH 0x3548
54#define QLA83XX_CRB_DEV_PART_INFO1 0x37E0
55#define QLA83XX_CRB_DEV_PART_INFO2 0x37E4
56
57#define QLA83XX_FW_VER_MAJOR 0x3550
58#define QLA83XX_FW_VER_MINOR 0x3554
59#define QLA83XX_FW_VER_SUB 0x3558
60#define QLA83XX_NPAR_STATE 0x359C
61#define QLA83XX_FW_IMAGE_VALID 0x35FC
62#define QLA83XX_CMDPEG_STATE 0x3650
63#define QLA83XX_ASIC_TEMP 0x37B4
64#define QLA83XX_FW_API 0x356C
65#define QLA83XX_DRV_OP_MODE 0x3570
66
67static const uint32_t qla4_83xx_reg_tbl[] = {
68 QLA83XX_PEG_HALT_STATUS1,
69 QLA83XX_PEG_HALT_STATUS2,
70 QLA83XX_PEG_ALIVE_COUNTER,
71 QLA83XX_CRB_DRV_ACTIVE,
72 QLA83XX_CRB_DEV_STATE,
73 QLA83XX_CRB_DRV_STATE,
74 QLA83XX_CRB_DRV_SCRATCH,
75 QLA83XX_CRB_DEV_PART_INFO1,
76 QLA83XX_CRB_IDC_VER_MAJOR,
77 QLA83XX_FW_VER_MAJOR,
78 QLA83XX_FW_VER_MINOR,
79 QLA83XX_FW_VER_SUB,
80 QLA83XX_CMDPEG_STATE,
81 QLA83XX_ASIC_TEMP,
82};
83
84#define QLA83XX_CRB_WIN_BASE 0x3800
85#define QLA83XX_CRB_WIN_FUNC(f) (QLA83XX_CRB_WIN_BASE+((f)*4))
86#define QLA83XX_SEM_LOCK_BASE 0x3840
87#define QLA83XX_SEM_UNLOCK_BASE 0x3844
88#define QLA83XX_SEM_LOCK_FUNC(f) (QLA83XX_SEM_LOCK_BASE+((f)*8))
89#define QLA83XX_SEM_UNLOCK_FUNC(f) (QLA83XX_SEM_UNLOCK_BASE+((f)*8))
90#define QLA83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
91#define QLA83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
92#define QLA83XX_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
93#define QLA83XX_LINK_SPEED_FACTOR 10
94
95/* FLASH API Defines */
96#define QLA83xx_FLASH_MAX_WAIT_USEC 100
97#define QLA83XX_FLASH_LOCK_TIMEOUT 10000
98#define QLA83XX_FLASH_SECTOR_SIZE 65536
99#define QLA83XX_DRV_LOCK_TIMEOUT 2000
100#define QLA83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
101#define QLA83XX_FLASH_WRITE_CMD 0xdacdacda
102#define QLA83XX_FLASH_BUFFER_WRITE_CMD 0xcadcadca
103#define QLA83XX_FLASH_READ_RETRY_COUNT 2000
104#define QLA83XX_FLASH_STATUS_READY 0x6
105#define QLA83XX_FLASH_BUFFER_WRITE_MIN 2
106#define QLA83XX_FLASH_BUFFER_WRITE_MAX 64
107#define QLA83XX_FLASH_STATUS_REG_POLL_DELAY 1
108#define QLA83XX_ERASE_MODE 1
109#define QLA83XX_WRITE_MODE 2
110#define QLA83XX_DWORD_WRITE_MODE 3
111
112#define QLA83XX_GLOBAL_RESET 0x38CC
113#define QLA83XX_WILDCARD 0x38F0
114#define QLA83XX_INFORMANT 0x38FC
115#define QLA83XX_HOST_MBX_CTRL 0x3038
116#define QLA83XX_FW_MBX_CTRL 0x303C
117#define QLA83XX_BOOTLOADER_ADDR 0x355C
118#define QLA83XX_BOOTLOADER_SIZE 0x3560
119#define QLA83XX_FW_IMAGE_ADDR 0x3564
120#define QLA83XX_MBX_INTR_ENABLE 0x1000
121#define QLA83XX_MBX_INTR_MASK 0x1200
122
123/* IDC Control Register bit defines */
124#define DONTRESET_BIT0 0x1
125#define GRACEFUL_RESET_BIT1 0x2
126
127#define QLA83XX_HALT_STATUS_INFORMATIONAL (0x1 << 29)
128#define QLA83XX_HALT_STATUS_FW_RESET (0x2 << 29)
129#define QLA83XX_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
130
131/* Firmware image definitions */
132#define QLA83XX_BOOTLOADER_FLASH_ADDR 0x10000
133#define QLA83XX_BOOT_FROM_FLASH 0
134
135#define QLA83XX_IDC_PARAM_ADDR 0x3e8020
136/* Reset template definitions */
137#define QLA83XX_MAX_RESET_SEQ_ENTRIES 16
138#define QLA83XX_RESTART_TEMPLATE_SIZE 0x2000
139#define QLA83XX_RESET_TEMPLATE_ADDR 0x4F0000
140#define QLA83XX_RESET_SEQ_VERSION 0x0101
141
142/* Reset template entry opcodes */
143#define OPCODE_NOP 0x0000
144#define OPCODE_WRITE_LIST 0x0001
145#define OPCODE_READ_WRITE_LIST 0x0002
146#define OPCODE_POLL_LIST 0x0004
147#define OPCODE_POLL_WRITE_LIST 0x0008
148#define OPCODE_READ_MODIFY_WRITE 0x0010
149#define OPCODE_SEQ_PAUSE 0x0020
150#define OPCODE_SEQ_END 0x0040
151#define OPCODE_TMPL_END 0x0080
152#define OPCODE_POLL_READ_LIST 0x0100
153
154/* Template Header */
155#define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
156struct qla4_83xx_reset_template_hdr {
157 __le16 version;
158 __le16 signature;
159 __le16 size;
160 __le16 entries;
161 __le16 hdr_size;
162 __le16 checksum;
163 __le16 init_seq_offset;
164 __le16 start_seq_offset;
165} __packed;
166
167/* Common Entry Header. */
168struct qla4_83xx_reset_entry_hdr {
169 __le16 cmd;
170 __le16 size;
171 __le16 count;
172 __le16 delay;
173} __packed;
174
175/* Generic poll entry type. */
176struct qla4_83xx_poll {
177 __le32 test_mask;
178 __le32 test_value;
179} __packed;
180
181/* Read modify write entry type. */
182struct qla4_83xx_rmw {
183 __le32 test_mask;
184 __le32 xor_value;
185 __le32 or_value;
186 uint8_t shl;
187 uint8_t shr;
188 uint8_t index_a;
189 uint8_t rsvd;
190} __packed;
191
192/* Generic Entry Item with 2 DWords. */
193struct qla4_83xx_entry {
194 __le32 arg1;
195 __le32 arg2;
196} __packed;
197
198/* Generic Entry Item with 4 DWords.*/
199struct qla4_83xx_quad_entry {
200 __le32 dr_addr;
201 __le32 dr_value;
202 __le32 ar_addr;
203 __le32 ar_value;
204} __packed;
205
206struct qla4_83xx_reset_template {
207 int seq_index;
208 int seq_error;
209 int array_index;
210 uint32_t array[QLA83XX_MAX_RESET_SEQ_ENTRIES];
211 uint8_t *buff;
212 uint8_t *stop_offset;
213 uint8_t *start_offset;
214 uint8_t *init_offset;
215 struct qla4_83xx_reset_template_hdr *hdr;
216 uint8_t seq_end;
217 uint8_t template_end;
218};
219
220/* POLLRD Entry */
221struct qla83xx_minidump_entry_pollrd {
222 struct qla8xxx_minidump_entry_hdr h;
223 uint32_t select_addr;
224 uint32_t read_addr;
225 uint32_t select_value;
226 uint16_t select_value_stride;
227 uint16_t op_count;
228 uint32_t poll_wait;
229 uint32_t poll_mask;
230 uint32_t data_size;
231 uint32_t rsvd_1;
232};
233
234/* RDMUX2 Entry */
235struct qla83xx_minidump_entry_rdmux2 {
236 struct qla8xxx_minidump_entry_hdr h;
237 uint32_t select_addr_1;
238 uint32_t select_addr_2;
239 uint32_t select_value_1;
240 uint32_t select_value_2;
241 uint32_t op_count;
242 uint32_t select_value_mask;
243 uint32_t read_addr;
244 uint8_t select_value_stride;
245 uint8_t data_size;
246 uint8_t rsvd[2];
247};
248
249/* POLLRDMWR Entry */
250struct qla83xx_minidump_entry_pollrdmwr {
251 struct qla8xxx_minidump_entry_hdr h;
252 uint32_t addr_1;
253 uint32_t addr_2;
254 uint32_t value_1;
255 uint32_t value_2;
256 uint32_t poll_wait;
257 uint32_t poll_mask;
258 uint32_t modify_mask;
259 uint32_t data_size;
260};
261
262#endif