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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
Hyok S. Choiafeb90c2006-01-13 21:05:25 +00006 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
Nicolas Pitre70b6f2b2007-12-04 14:33:33 +010014 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
Rob Herring6f6f6a72012-03-10 10:30:31 -060018#include <asm/assembler.h>
Nicolas Pitref09b9972005-10-29 21:44:55 +010019#include <asm/memory.h>
Russell King753790e2011-02-06 15:32:24 +000020#include <asm/glue-df.h>
21#include <asm/glue-pf.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/vfpmacros.h>
Rob Herring243c8652012-02-08 18:26:34 -060023#ifndef CONFIG_MULTI_IRQ_HANDLER
Russell Kinga09e64f2008-08-05 16:14:15 +010024#include <mach/entry-macro.S>
Rob Herring243c8652012-02-08 18:26:34 -060025#endif
Russell Kingd6551e82006-06-21 13:31:52 +010026#include <asm/thread_notify.h>
Catalin Marinasc4c57162009-02-16 11:42:09 +010027#include <asm/unwind.h>
Russell Kingcc20d422009-11-09 23:53:29 +000028#include <asm/unistd.h>
Tony Lindgrenf159f4e2010-07-05 14:53:10 +010029#include <asm/tls.h>
Dave Martinef4c5362011-08-19 18:00:08 +010030#include <asm/system.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
32#include "entry-header.S"
Magnus Dammcd544ce2010-12-22 13:20:08 +010033#include <asm/entry-macro-multi.S>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034
35/*
Russell Kingd9600c92011-06-26 10:34:02 +010036 * Interrupt handling.
Russell King187a51a2005-05-21 18:14:44 +010037 */
38 .macro irq_handler
eric miao52108642010-12-13 09:42:34 +010039#ifdef CONFIG_MULTI_IRQ_HANDLER
Russell Kingd9600c92011-06-26 10:34:02 +010040 ldr r1, =handle_arch_irq
eric miao52108642010-12-13 09:42:34 +010041 mov r0, sp
eric miao52108642010-12-13 09:42:34 +010042 adr lr, BSYM(9997f)
Marc Zyngierabeb24a2011-09-06 09:23:26 +010043 ldr pc, [r1]
44#else
Magnus Dammcd544ce2010-12-22 13:20:08 +010045 arch_irq_handler_default
Marc Zyngierabeb24a2011-09-06 09:23:26 +010046#endif
Russell Kingf00ec482010-09-04 10:47:48 +0100479997:
Russell King187a51a2005-05-21 18:14:44 +010048 .endm
49
Russell Kingac8b9c12011-06-26 10:22:08 +010050 .macro pabt_helper
Russell King8dfe7ac2011-06-26 12:37:35 +010051 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
Russell Kingac8b9c12011-06-26 10:22:08 +010052#ifdef MULTI_PABORT
Russell King0402bec2011-06-25 15:46:08 +010053 ldr ip, .LCprocfns
Russell Kingac8b9c12011-06-26 10:22:08 +010054 mov lr, pc
Russell King0402bec2011-06-25 15:46:08 +010055 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
Russell Kingac8b9c12011-06-26 10:22:08 +010056#else
57 bl CPU_PABORT_HANDLER
58#endif
59 .endm
60
61 .macro dabt_helper
62
63 @
64 @ Call the processor-specific abort handler:
65 @
Russell Kingda740472011-06-26 16:01:26 +010066 @ r2 - pt_regs
Russell King3e287be2011-06-26 14:35:07 +010067 @ r4 - aborted context pc
68 @ r5 - aborted context psr
Russell Kingac8b9c12011-06-26 10:22:08 +010069 @
70 @ The abort handler must return the aborted address in r0, and
71 @ the fault status register in r1. r9 must be preserved.
72 @
73#ifdef MULTI_DABORT
Russell King0402bec2011-06-25 15:46:08 +010074 ldr ip, .LCprocfns
Russell Kingac8b9c12011-06-26 10:22:08 +010075 mov lr, pc
Russell King0402bec2011-06-25 15:46:08 +010076 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
Russell Kingac8b9c12011-06-26 10:22:08 +010077#else
78 bl CPU_DABORT_HANDLER
79#endif
80 .endm
81
Nicolas Pitre785d3cd2007-12-03 15:27:56 -050082#ifdef CONFIG_KPROBES
83 .section .kprobes.text,"ax",%progbits
84#else
85 .text
86#endif
87
Russell King187a51a2005-05-21 18:14:44 +010088/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 * Invalid mode handlers
90 */
Russell Kingccea7a12005-05-31 22:22:32 +010091 .macro inv_entry, reason
92 sub sp, sp, #S_FRAME_SIZE
Catalin Marinasb86040a2009-07-24 12:32:54 +010093 ARM( stmib sp, {r1 - lr} )
94 THUMB( stmia sp, {r0 - r12} )
95 THUMB( str sp, [sp, #S_SP] )
96 THUMB( str lr, [sp, #S_LR] )
Linus Torvalds1da177e2005-04-16 15:20:36 -070097 mov r1, #\reason
98 .endm
99
100__pabt_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100101 inv_entry BAD_PREFETCH
102 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +0100103ENDPROC(__pabt_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104
105__dabt_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100106 inv_entry BAD_DATA
107 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +0100108ENDPROC(__dabt_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
110__irq_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100111 inv_entry BAD_IRQ
112 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +0100113ENDPROC(__irq_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
115__und_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100116 inv_entry BAD_UNDEFINSTR
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
Russell Kingccea7a12005-05-31 22:22:32 +0100118 @
119 @ XXX fall through to common_invalid
120 @
121
122@
123@ common_invalid - generic code for failed exception (re-entrant version of handlers)
124@
125common_invalid:
126 zero_fp
127
128 ldmia r0, {r4 - r6}
129 add r0, sp, #S_PC @ here for interlock avoidance
130 mov r7, #-1 @ "" "" "" ""
131 str r4, [sp] @ save preserved r0
132 stmia r0, {r5 - r7} @ lr_<exception>,
133 @ cpsr_<exception>, "old_r0"
134
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 mov r0, sp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 b bad_mode
Catalin Marinas93ed3972008-08-28 11:22:32 +0100137ENDPROC(__und_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138
139/*
140 * SVC mode handlers
141 */
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000142
143#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
144#define SPFIX(code...) code
145#else
146#define SPFIX(code...)
147#endif
148
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500149 .macro svc_entry, stack_hole=0
Catalin Marinasc4c57162009-02-16 11:42:09 +0100150 UNWIND(.fnstart )
151 UNWIND(.save {r0 - pc} )
Catalin Marinasb86040a2009-07-24 12:32:54 +0100152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
153#ifdef CONFIG_THUMB2_KERNEL
154 SPFIX( str r0, [sp] ) @ temporarily saved
155 SPFIX( mov r0, sp )
156 SPFIX( tst r0, #4 ) @ test original stack alignment
157 SPFIX( ldr r0, [sp] ) @ restored
158#else
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000159 SPFIX( tst sp, #4 )
Catalin Marinasb86040a2009-07-24 12:32:54 +0100160#endif
161 SPFIX( subeq sp, sp, #4 )
162 stmia sp, {r1 - r12}
Russell Kingccea7a12005-05-31 22:22:32 +0100163
Russell Kingb059bdc2011-06-25 15:44:20 +0100164 ldmia r0, {r3 - r5}
165 add r7, sp, #S_SP - 4 @ here for interlock avoidance
166 mov r6, #-1 @ "" "" "" ""
167 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
168 SPFIX( addeq r2, r2, #4 )
169 str r3, [sp, #-4]! @ save the "real" r0 copied
Russell Kingccea7a12005-05-31 22:22:32 +0100170 @ from the exception stack
171
Russell Kingb059bdc2011-06-25 15:44:20 +0100172 mov r3, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173
174 @
175 @ We are now ready to fill in the remaining blanks on the stack:
176 @
Russell Kingb059bdc2011-06-25 15:44:20 +0100177 @ r2 - sp_svc
178 @ r3 - lr_svc
179 @ r4 - lr_<exception>, already fixed up for correct return/restart
180 @ r5 - spsr_<exception>
181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 @
Russell Kingb059bdc2011-06-25 15:44:20 +0100183 stmia r7, {r2 - r6}
Russell Kingf2741b72011-06-25 17:35:19 +0100184
185#ifdef CONFIG_TRACE_IRQFLAGS
186 bl trace_hardirqs_off
187#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 .endm
189
190 .align 5
191__dabt_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100192 svc_entry
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 mov r2, sp
Russell Kingda740472011-06-26 16:01:26 +0100194 dabt_helper
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195
196 @
197 @ IRQs off again before pulling preserved data off the stack
198 @
Russell Kingac788842010-07-10 10:10:18 +0100199 disable_irq_notrace
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200
Russell King02fe2842011-06-25 11:44:06 +0100201#ifdef CONFIG_TRACE_IRQFLAGS
202 tst r5, #PSR_I_BIT
203 bleq trace_hardirqs_on
204 tst r5, #PSR_I_BIT
205 blne trace_hardirqs_off
206#endif
Russell Kingb059bdc2011-06-25 15:44:20 +0100207 svc_exit r5 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100208 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100209ENDPROC(__dabt_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210
211 .align 5
212__irq_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100213 svc_entry
Russell King1613cc12011-06-25 10:57:57 +0100214 irq_handler
215
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216#ifdef CONFIG_PREEMPT
Russell King706fdd92005-05-21 18:15:45 +0100217 get_thread_info tsk
218 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
Russell King706fdd92005-05-21 18:15:45 +0100219 ldr r0, [tsk, #TI_FLAGS] @ get flags
Russell King28fab1a2008-04-13 17:47:35 +0100220 teq r8, #0 @ if preempt count != 0
221 movne r0, #0 @ force flags to 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 tst r0, #_TIF_NEED_RESCHED
223 blne svc_preempt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224#endif
Russell King30891c92011-06-26 12:47:08 +0100225
Russell King7ad1bcb2006-08-27 12:07:02 +0100226#ifdef CONFIG_TRACE_IRQFLAGS
Russell Kingfbab1c82011-06-25 16:57:50 +0100227 @ The parent context IRQs must have been enabled to get here in
228 @ the first place, so there's no point checking the PSR I bit.
229 bl trace_hardirqs_on
Russell King7ad1bcb2006-08-27 12:07:02 +0100230#endif
Russell Kingb059bdc2011-06-25 15:44:20 +0100231 svc_exit r5 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100232 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100233ENDPROC(__irq_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234
235 .ltorg
236
237#ifdef CONFIG_PREEMPT
238svc_preempt:
Russell King28fab1a2008-04-13 17:47:35 +0100239 mov r8, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401: bl preempt_schedule_irq @ irq en/disable is done inside
Russell King706fdd92005-05-21 18:15:45 +0100241 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 tst r0, #_TIF_NEED_RESCHED
Russell King28fab1a2008-04-13 17:47:35 +0100243 moveq pc, r8 @ go again
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 b 1b
245#endif
246
247 .align 5
248__und_svc:
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500249#ifdef CONFIG_KPROBES
250 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
251 @ it obviously needs free stack space which then will belong to
252 @ the saved context.
253 svc_entry 64
254#else
Russell Kingccea7a12005-05-31 22:22:32 +0100255 svc_entry
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500256#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 @
258 @ call emulation code, which returns using r9 if it has emulated
259 @ the instruction, or the more conventional lr if we are to treat
260 @ this as a real undefined instruction
261 @
262 @ r0 - instruction
263 @
Catalin Marinas83e686e2009-09-18 23:27:07 +0100264#ifndef CONFIG_THUMB2_KERNEL
Russell Kingb059bdc2011-06-25 15:44:20 +0100265 ldr r0, [r4, #-4]
Catalin Marinas83e686e2009-09-18 23:27:07 +0100266#else
Russell Kingb059bdc2011-06-25 15:44:20 +0100267 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
Dave Martin85519182011-08-19 17:59:27 +0100268 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
Russell Kingb059bdc2011-06-25 15:44:20 +0100269 ldrhhs r9, [r4] @ bottom 16 bits
Catalin Marinas83e686e2009-09-18 23:27:07 +0100270 orrhs r0, r9, r0, lsl #16
271#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100272 adr r9, BSYM(1f)
Russell Kingb059bdc2011-06-25 15:44:20 +0100273 mov r2, r4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274 bl call_fpe
275
276 mov r0, sp @ struct pt_regs *regs
277 bl do_undefinstr
278
279 @
280 @ IRQs off again before pulling preserved data off the stack
281 @
Russell Kingac788842010-07-10 10:10:18 +01002821: disable_irq_notrace
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283
284 @
285 @ restore SPSR and restart the instruction
286 @
Russell Kingb059bdc2011-06-25 15:44:20 +0100287 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
Russell Kingdf295df2011-06-25 16:55:58 +0100288#ifdef CONFIG_TRACE_IRQFLAGS
289 tst r5, #PSR_I_BIT
290 bleq trace_hardirqs_on
291 tst r5, #PSR_I_BIT
292 blne trace_hardirqs_off
293#endif
Russell Kingb059bdc2011-06-25 15:44:20 +0100294 svc_exit r5 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100295 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100296ENDPROC(__und_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297
298 .align 5
299__pabt_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100300 svc_entry
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100301 mov r2, sp @ regs
Russell King8dfe7ac2011-06-26 12:37:35 +0100302 pabt_helper
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303
304 @
305 @ IRQs off again before pulling preserved data off the stack
306 @
Russell Kingac788842010-07-10 10:10:18 +0100307 disable_irq_notrace
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308
Russell King02fe2842011-06-25 11:44:06 +0100309#ifdef CONFIG_TRACE_IRQFLAGS
310 tst r5, #PSR_I_BIT
311 bleq trace_hardirqs_on
312 tst r5, #PSR_I_BIT
313 blne trace_hardirqs_off
314#endif
Russell Kingb059bdc2011-06-25 15:44:20 +0100315 svc_exit r5 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100316 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100317ENDPROC(__pabt_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318
319 .align 5
Russell King49f680e2005-05-31 18:02:00 +0100320.LCcralign:
321 .word cr_alignment
Paul Brook48d79272008-04-18 22:43:07 +0100322#ifdef MULTI_DABORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323.LCprocfns:
324 .word processor
325#endif
326.LCfp:
327 .word fp_enter
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328
329/*
330 * User mode handlers
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000331 *
332 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 */
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000334
335#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
336#error "sizeof(struct pt_regs) must be a multiple of 8"
337#endif
338
Russell Kingccea7a12005-05-31 22:22:32 +0100339 .macro usr_entry
Catalin Marinasc4c57162009-02-16 11:42:09 +0100340 UNWIND(.fnstart )
341 UNWIND(.cantunwind ) @ don't unwind the user space
Russell Kingccea7a12005-05-31 22:22:32 +0100342 sub sp, sp, #S_FRAME_SIZE
Catalin Marinasb86040a2009-07-24 12:32:54 +0100343 ARM( stmib sp, {r1 - r12} )
344 THUMB( stmia sp, {r0 - r12} )
Russell Kingccea7a12005-05-31 22:22:32 +0100345
Russell Kingb059bdc2011-06-25 15:44:20 +0100346 ldmia r0, {r3 - r5}
Russell Kingccea7a12005-05-31 22:22:32 +0100347 add r0, sp, #S_PC @ here for interlock avoidance
Russell Kingb059bdc2011-06-25 15:44:20 +0100348 mov r6, #-1 @ "" "" "" ""
Russell Kingccea7a12005-05-31 22:22:32 +0100349
Russell Kingb059bdc2011-06-25 15:44:20 +0100350 str r3, [sp] @ save the "real" r0 copied
Russell Kingccea7a12005-05-31 22:22:32 +0100351 @ from the exception stack
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352
353 @
354 @ We are now ready to fill in the remaining blanks on the stack:
355 @
Russell Kingb059bdc2011-06-25 15:44:20 +0100356 @ r4 - lr_<exception>, already fixed up for correct return/restart
357 @ r5 - spsr_<exception>
358 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 @
360 @ Also, separately save sp_usr and lr_usr
361 @
Russell Kingb059bdc2011-06-25 15:44:20 +0100362 stmia r0, {r4 - r6}
Catalin Marinasb86040a2009-07-24 12:32:54 +0100363 ARM( stmdb r0, {sp, lr}^ )
364 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365
366 @
367 @ Enable the alignment trap while in kernel mode
368 @
Russell King49f680e2005-05-31 18:02:00 +0100369 alignment_trap r0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370
371 @
372 @ Clear FP to mark the first stack frame
373 @
374 zero_fp
Russell Kingf2741b72011-06-25 17:35:19 +0100375
376#ifdef CONFIG_IRQSOFF_TRACER
377 bl trace_hardirqs_off
378#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 .endm
380
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100381 .macro kuser_cmpxchg_check
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400382#if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100383#ifndef CONFIG_MMU
384#warning "NPTL on non MMU needs fixing"
385#else
386 @ Make sure our user space atomic helper is restarted
387 @ if it was interrupted in a critical region. Here we
388 @ perform a quick test inline since it should be false
389 @ 99.9999% of the time. The rest is done out of line.
Russell Kingb059bdc2011-06-25 15:44:20 +0100390 cmp r4, #TASK_SIZE
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400391 blhs kuser_cmpxchg64_fixup
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100392#endif
393#endif
394 .endm
395
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 .align 5
397__dabt_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100398 usr_entry
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100399 kuser_cmpxchg_check
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 mov r2, sp
Russell Kingda740472011-06-26 16:01:26 +0100401 dabt_helper
402 b ret_from_exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100403 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100404ENDPROC(__dabt_usr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405
406 .align 5
407__irq_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100408 usr_entry
Russell Kingbc089602011-06-25 18:28:19 +0100409 kuser_cmpxchg_check
Russell King187a51a2005-05-21 18:14:44 +0100410 irq_handler
Russell King1613cc12011-06-25 10:57:57 +0100411 get_thread_info tsk
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 mov why, #0
Ming Lei9fc25522011-06-05 02:24:58 +0100413 b ret_to_user_from_irq
Catalin Marinasc4c57162009-02-16 11:42:09 +0100414 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100415ENDPROC(__irq_usr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416
417 .ltorg
418
419 .align 5
420__und_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100421 usr_entry
Russell Kingbc089602011-06-25 18:28:19 +0100422
Russell Kingb059bdc2011-06-25 15:44:20 +0100423 mov r2, r4
424 mov r3, r5
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 @
427 @ fall through to the emulation code, which returns using r9 if
428 @ it has emulated the instruction, or the more conventional lr
429 @ if we are to treat this as a real undefined instruction
430 @
431 @ r0 - instruction
432 @
Catalin Marinasb86040a2009-07-24 12:32:54 +0100433 adr r9, BSYM(ret_from_exception)
434 adr lr, BSYM(__und_usr_unknown)
Paul Brookcb170a42008-04-18 22:43:08 +0100435 tst r3, #PSR_T_BIT @ Thumb mode?
Catalin Marinasb86040a2009-07-24 12:32:54 +0100436 itet eq @ explicit IT needed for the 1f label
Paul Brookcb170a42008-04-18 22:43:08 +0100437 subeq r4, r2, #4 @ ARM instr at LR - 4
438 subne r4, r2, #2 @ Thumb instr at LR - 2
4391: ldreqt r0, [r4]
Catalin Marinas26584852009-05-30 14:00:18 +0100440#ifdef CONFIG_CPU_ENDIAN_BE8
441 reveq r0, r0 @ little endian instruction
442#endif
Paul Brookcb170a42008-04-18 22:43:08 +0100443 beq call_fpe
444 @ Thumb instruction
Dave Martinef4c5362011-08-19 18:00:08 +0100445#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
446/*
447 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
448 * can never be supported in a single kernel, this code is not applicable at
449 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
450 * made about .arch directives.
451 */
452#if __LINUX_ARM_ARCH__ < 7
453/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
454#define NEED_CPU_ARCHITECTURE
455 ldr r5, .LCcpu_architecture
456 ldr r5, [r5]
457 cmp r5, #CPU_ARCH_ARMv7
458 blo __und_usr_unknown
459/*
460 * The following code won't get run unless the running CPU really is v7, so
461 * coding round the lack of ldrht on older arches is pointless. Temporarily
462 * override the assembler target arch with the minimum required instead:
463 */
464 .arch armv6t2
465#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +01004662:
467 ARM( ldrht r5, [r4], #2 )
468 THUMB( ldrht r5, [r4] )
469 THUMB( add r4, r4, #2 )
Dave Martin85519182011-08-19 17:59:27 +0100470 cmp r5, #0xe800 @ 32bit instruction if xx != 0
Paul Brookcb170a42008-04-18 22:43:08 +0100471 blo __und_usr_unknown
4723: ldrht r0, [r4]
473 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
474 orr r0, r0, r5, lsl #16
Dave Martinef4c5362011-08-19 18:00:08 +0100475
476#if __LINUX_ARM_ARCH__ < 7
477/* If the target arch was overridden, change it back: */
478#ifdef CONFIG_CPU_32v6K
479 .arch armv6k
Paul Brookcb170a42008-04-18 22:43:08 +0100480#else
Dave Martinef4c5362011-08-19 18:00:08 +0100481 .arch armv6
482#endif
483#endif /* __LINUX_ARM_ARCH__ < 7 */
484#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
Paul Brookcb170a42008-04-18 22:43:08 +0100485 b __und_usr_unknown
486#endif
Catalin Marinasc4c57162009-02-16 11:42:09 +0100487 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100488ENDPROC(__und_usr)
Paul Brookcb170a42008-04-18 22:43:08 +0100489
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490 @
491 @ fallthrough to call_fpe
492 @
493
494/*
495 * The out of line fixup for the ldrt above.
496 */
Russell King42604152010-04-19 10:15:03 +0100497 .pushsection .fixup, "ax"
Paul Brookcb170a42008-04-18 22:43:08 +01004984: mov pc, r9
Russell King42604152010-04-19 10:15:03 +0100499 .popsection
500 .pushsection __ex_table,"a"
Paul Brookcb170a42008-04-18 22:43:08 +0100501 .long 1b, 4b
Guennadi Liakhovetskic89cefe2011-11-22 23:42:12 +0100502#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
Paul Brookcb170a42008-04-18 22:43:08 +0100503 .long 2b, 4b
504 .long 3b, 4b
505#endif
Russell King42604152010-04-19 10:15:03 +0100506 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507
508/*
509 * Check whether the instruction is a co-processor instruction.
510 * If yes, we need to call the relevant co-processor handler.
511 *
512 * Note that we don't do a full check here for the co-processor
513 * instructions; all instructions with bit 27 set are well
514 * defined. The only instructions that should fault are the
515 * co-processor instructions. However, we have to watch out
516 * for the ARM6/ARM7 SWI bug.
517 *
Catalin Marinasb5872db2008-01-10 19:16:17 +0100518 * NEON is a special case that has to be handled here. Not all
519 * NEON instructions are co-processor instructions, so we have
520 * to make a special case of checking for them. Plus, there's
521 * five groups of them, so we have a table of mask/opcode pairs
522 * to check against, and if any match then we branch off into the
523 * NEON handler code.
524 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 * Emulators may wish to make use of the following registers:
526 * r0 = instruction opcode.
527 * r2 = PC+4
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000528 * r9 = normal "successful" return address
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529 * r10 = this threads thread_info structure.
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000530 * lr = unrecognised instruction return address
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531 */
Paul Brookcb170a42008-04-18 22:43:08 +0100532 @
533 @ Fall-through from Thumb-2 __und_usr
534 @
535#ifdef CONFIG_NEON
536 adr r6, .LCneon_thumb_opcodes
537 b 2f
538#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539call_fpe:
Catalin Marinasb5872db2008-01-10 19:16:17 +0100540#ifdef CONFIG_NEON
Paul Brookcb170a42008-04-18 22:43:08 +0100541 adr r6, .LCneon_arm_opcodes
Catalin Marinasb5872db2008-01-10 19:16:17 +01005422:
543 ldr r7, [r6], #4 @ mask value
544 cmp r7, #0 @ end mask?
545 beq 1f
546 and r8, r0, r7
547 ldr r7, [r6], #4 @ opcode bits matching in mask
548 cmp r8, r7 @ NEON instruction?
549 bne 2b
550 get_thread_info r10
551 mov r7, #1
552 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
553 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
554 b do_vfp @ let VFP handler handle this
5551:
556#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
Paul Brookcb170a42008-04-18 22:43:08 +0100558 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
560 and r8, r0, #0x0f000000 @ mask out op-code bits
561 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
562#endif
563 moveq pc, lr
564 get_thread_info r10 @ get current thread
565 and r8, r0, #0x00000f00 @ mask out CP number
Catalin Marinasb86040a2009-07-24 12:32:54 +0100566 THUMB( lsr r8, r8, #8 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 mov r7, #1
568 add r6, r10, #TI_USED_CP
Catalin Marinasb86040a2009-07-24 12:32:54 +0100569 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
570 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571#ifdef CONFIG_IWMMXT
572 @ Test if we need to give access to iWMMXt coprocessors
573 ldr r5, [r10, #TI_FLAGS]
574 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
575 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
576 bcs iwmmxt_task_enable
577#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100578 ARM( add pc, pc, r8, lsr #6 )
579 THUMB( lsl r8, r8, #2 )
580 THUMB( add pc, r8 )
581 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582
Catalin Marinasa771fe62009-10-12 17:31:20 +0100583 movw_pc lr @ CP#0
Catalin Marinasb86040a2009-07-24 12:32:54 +0100584 W(b) do_fpe @ CP#1 (FPE)
585 W(b) do_fpe @ CP#2 (FPE)
Catalin Marinasa771fe62009-10-12 17:31:20 +0100586 movw_pc lr @ CP#3
Lennert Buytenhekc17fad12006-06-27 23:03:03 +0100587#ifdef CONFIG_CRUNCH
588 b crunch_task_enable @ CP#4 (MaverickCrunch)
589 b crunch_task_enable @ CP#5 (MaverickCrunch)
590 b crunch_task_enable @ CP#6 (MaverickCrunch)
591#else
Catalin Marinasa771fe62009-10-12 17:31:20 +0100592 movw_pc lr @ CP#4
593 movw_pc lr @ CP#5
594 movw_pc lr @ CP#6
Lennert Buytenhekc17fad12006-06-27 23:03:03 +0100595#endif
Catalin Marinasa771fe62009-10-12 17:31:20 +0100596 movw_pc lr @ CP#7
597 movw_pc lr @ CP#8
598 movw_pc lr @ CP#9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599#ifdef CONFIG_VFP
Catalin Marinasb86040a2009-07-24 12:32:54 +0100600 W(b) do_vfp @ CP#10 (VFP)
601 W(b) do_vfp @ CP#11 (VFP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700602#else
Catalin Marinasa771fe62009-10-12 17:31:20 +0100603 movw_pc lr @ CP#10 (VFP)
604 movw_pc lr @ CP#11 (VFP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605#endif
Catalin Marinasa771fe62009-10-12 17:31:20 +0100606 movw_pc lr @ CP#12
607 movw_pc lr @ CP#13
608 movw_pc lr @ CP#14 (Debug)
609 movw_pc lr @ CP#15 (Control)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610
Dave Martinef4c5362011-08-19 18:00:08 +0100611#ifdef NEED_CPU_ARCHITECTURE
612 .align 2
613.LCcpu_architecture:
614 .word __cpu_architecture
615#endif
616
Catalin Marinasb5872db2008-01-10 19:16:17 +0100617#ifdef CONFIG_NEON
618 .align 6
619
Paul Brookcb170a42008-04-18 22:43:08 +0100620.LCneon_arm_opcodes:
Catalin Marinasb5872db2008-01-10 19:16:17 +0100621 .word 0xfe000000 @ mask
622 .word 0xf2000000 @ opcode
623
624 .word 0xff100000 @ mask
625 .word 0xf4000000 @ opcode
626
627 .word 0x00000000 @ mask
628 .word 0x00000000 @ opcode
Paul Brookcb170a42008-04-18 22:43:08 +0100629
630.LCneon_thumb_opcodes:
631 .word 0xef000000 @ mask
632 .word 0xef000000 @ opcode
633
634 .word 0xff100000 @ mask
635 .word 0xf9000000 @ opcode
636
637 .word 0x00000000 @ mask
638 .word 0x00000000 @ opcode
Catalin Marinasb5872db2008-01-10 19:16:17 +0100639#endif
640
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641do_fpe:
Russell King5d25ac02006-03-15 12:33:43 +0000642 enable_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643 ldr r4, .LCfp
644 add r10, r10, #TI_FPSTATE @ r10 = workspace
645 ldr pc, [r4] @ Call FP module USR entry point
646
647/*
648 * The FP module is called with these registers set:
649 * r0 = instruction
650 * r2 = PC+4
651 * r9 = normal "successful" return address
652 * r10 = FP workspace
653 * lr = unrecognised FP instruction return address
654 */
655
Santosh Shilimkar124efc22010-04-30 10:45:46 +0100656 .pushsection .data
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657ENTRY(fp_enter)
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000658 .word no_fp
Santosh Shilimkar124efc22010-04-30 10:45:46 +0100659 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660
Catalin Marinas83e686e2009-09-18 23:27:07 +0100661ENTRY(no_fp)
662 mov pc, lr
663ENDPROC(no_fp)
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000664
665__und_usr_unknown:
Russell Kingecbab712009-01-27 23:20:00 +0000666 enable_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667 mov r0, sp
Catalin Marinasb86040a2009-07-24 12:32:54 +0100668 adr lr, BSYM(ret_from_exception)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 b do_undefinstr
Catalin Marinas93ed3972008-08-28 11:22:32 +0100670ENDPROC(__und_usr_unknown)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671
672 .align 5
673__pabt_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100674 usr_entry
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100675 mov r2, sp @ regs
Russell King8dfe7ac2011-06-26 12:37:35 +0100676 pabt_helper
Catalin Marinasc4c57162009-02-16 11:42:09 +0100677 UNWIND(.fnend )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 /* fall through */
679/*
680 * This is the return code to user mode for abort handlers
681 */
682ENTRY(ret_from_exception)
Catalin Marinasc4c57162009-02-16 11:42:09 +0100683 UNWIND(.fnstart )
684 UNWIND(.cantunwind )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700685 get_thread_info tsk
686 mov why, #0
687 b ret_to_user
Catalin Marinasc4c57162009-02-16 11:42:09 +0100688 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100689ENDPROC(__pabt_usr)
690ENDPROC(ret_from_exception)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691
692/*
693 * Register switch for ARMv3 and ARMv4 processors
694 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
695 * previous and next are guaranteed not to be the same.
696 */
697ENTRY(__switch_to)
Catalin Marinasc4c57162009-02-16 11:42:09 +0100698 UNWIND(.fnstart )
699 UNWIND(.cantunwind )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700 add ip, r1, #TI_CPU_SAVE
701 ldr r3, [r2, #TI_TP_VALUE]
Catalin Marinasb86040a2009-07-24 12:32:54 +0100702 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
703 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
704 THUMB( str sp, [ip], #4 )
705 THUMB( str lr, [ip], #4 )
Catalin Marinas247055a2010-09-13 16:03:21 +0100706#ifdef CONFIG_CPU_USE_DOMAINS
Russell Kingd6551e82006-06-21 13:31:52 +0100707 ldr r6, [r2, #TI_CPU_DOMAIN]
Hyok S. Choiafeb90c2006-01-13 21:05:25 +0000708#endif
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100709 set_tls r3, r4, r5
Nicolas Pitredf0698b2010-06-07 21:50:33 -0400710#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
711 ldr r7, [r2, #TI_TASK]
712 ldr r8, =__stack_chk_guard
713 ldr r7, [r7, #TSK_STACK_CANARY]
714#endif
Catalin Marinas247055a2010-09-13 16:03:21 +0100715#ifdef CONFIG_CPU_USE_DOMAINS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
Hyok S. Choiafeb90c2006-01-13 21:05:25 +0000717#endif
Russell Kingd6551e82006-06-21 13:31:52 +0100718 mov r5, r0
719 add r4, r2, #TI_CPU_SAVE
720 ldr r0, =thread_notify_head
721 mov r1, #THREAD_NOTIFY_SWITCH
722 bl atomic_notifier_call_chain
Nicolas Pitredf0698b2010-06-07 21:50:33 -0400723#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
724 str r7, [r8]
725#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100726 THUMB( mov ip, r4 )
Russell Kingd6551e82006-06-21 13:31:52 +0100727 mov r0, r5
Catalin Marinasb86040a2009-07-24 12:32:54 +0100728 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
729 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
730 THUMB( ldr sp, [ip], #4 )
731 THUMB( ldr pc, [ip] )
Catalin Marinasc4c57162009-02-16 11:42:09 +0100732 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100733ENDPROC(__switch_to)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734
735 __INIT
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100736
737/*
738 * User helpers.
739 *
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100740 * Each segment is 32-byte aligned and will be moved to the top of the high
741 * vector page. New segments (if ever needed) must be added in front of
742 * existing ones. This mechanism should be used only for things that are
743 * really small and justified, and not be abused freely.
744 *
Nicolas Pitre37b83042011-06-19 23:36:03 -0400745 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100746 */
Catalin Marinasb86040a2009-07-24 12:32:54 +0100747 THUMB( .arm )
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100748
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100749 .macro usr_ret, reg
750#ifdef CONFIG_ARM_THUMB
751 bx \reg
752#else
753 mov pc, \reg
754#endif
755 .endm
756
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100757 .align 5
758 .globl __kuser_helper_start
759__kuser_helper_start:
760
761/*
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400762 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
763 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000764 */
765
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400766__kuser_cmpxchg64: @ 0xffff0f60
767
768#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
769
770 /*
771 * Poor you. No fast solution possible...
772 * The kernel itself must perform the operation.
773 * A special ghost syscall is used for that (see traps.c).
774 */
775 stmfd sp!, {r7, lr}
776 ldr r7, 1f @ it's 20 bits
777 swi __ARM_NR_cmpxchg64
778 ldmfd sp!, {r7, pc}
7791: .word __ARM_NR_cmpxchg64
780
781#elif defined(CONFIG_CPU_32v6K)
782
783 stmfd sp!, {r4, r5, r6, r7}
784 ldrd r4, r5, [r0] @ load old val
785 ldrd r6, r7, [r1] @ load new val
786 smp_dmb arm
7871: ldrexd r0, r1, [r2] @ load current val
788 eors r3, r0, r4 @ compare with oldval (1)
789 eoreqs r3, r1, r5 @ compare with oldval (2)
790 strexdeq r3, r6, r7, [r2] @ store newval if eq
791 teqeq r3, #1 @ success?
792 beq 1b @ if no then retry
793 smp_dmb arm
794 rsbs r0, r3, #0 @ set returned val and C flag
795 ldmfd sp!, {r4, r5, r6, r7}
Will Deacon5a97d0a2012-02-03 11:08:05 +0100796 usr_ret lr
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400797
798#elif !defined(CONFIG_SMP)
799
800#ifdef CONFIG_MMU
801
802 /*
803 * The only thing that can break atomicity in this cmpxchg64
804 * implementation is either an IRQ or a data abort exception
805 * causing another process/thread to be scheduled in the middle of
806 * the critical sequence. The same strategy as for cmpxchg is used.
807 */
808 stmfd sp!, {r4, r5, r6, lr}
809 ldmia r0, {r4, r5} @ load old val
810 ldmia r1, {r6, lr} @ load new val
8111: ldmia r2, {r0, r1} @ load current val
812 eors r3, r0, r4 @ compare with oldval (1)
813 eoreqs r3, r1, r5 @ compare with oldval (2)
8142: stmeqia r2, {r6, lr} @ store newval if eq
815 rsbs r0, r3, #0 @ set return val and C flag
816 ldmfd sp!, {r4, r5, r6, pc}
817
818 .text
819kuser_cmpxchg64_fixup:
820 @ Called from kuser_cmpxchg_fixup.
Russell King3ad55152011-07-22 23:09:07 +0100821 @ r4 = address of interrupted insn (must be preserved).
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400822 @ sp = saved regs. r7 and r8 are clobbered.
823 @ 1b = first critical insn, 2b = last critical insn.
Russell King3ad55152011-07-22 23:09:07 +0100824 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400825 mov r7, #0xffff0fff
826 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
Russell King3ad55152011-07-22 23:09:07 +0100827 subs r8, r4, r7
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400828 rsbcss r8, r8, #(2b - 1b)
829 strcs r7, [sp, #S_PC]
830#if __LINUX_ARM_ARCH__ < 6
831 bcc kuser_cmpxchg32_fixup
832#endif
833 mov pc, lr
834 .previous
835
836#else
837#warning "NPTL on non MMU needs fixing"
838 mov r0, #-1
839 adds r0, r0, #0
840 usr_ret lr
841#endif
842
843#else
844#error "incoherent kernel configuration"
845#endif
846
847 /* pad to next slot */
848 .rept (16 - (. - __kuser_cmpxchg64)/4)
849 .word 0
850 .endr
851
852 .align 5
853
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000854__kuser_memory_barrier: @ 0xffff0fa0
Dave Martined3768a2010-12-01 15:39:23 +0100855 smp_dmb arm
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100856 usr_ret lr
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000857
858 .align 5
859
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100860__kuser_cmpxchg: @ 0xffff0fc0
861
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100862#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100863
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100864 /*
865 * Poor you. No fast solution possible...
866 * The kernel itself must perform the operation.
867 * A special ghost syscall is used for that (see traps.c).
868 */
Nicolas Pitre5e097442006-01-18 22:38:49 +0000869 stmfd sp!, {r7, lr}
Dave Martin55afd262010-12-01 18:12:43 +0100870 ldr r7, 1f @ it's 20 bits
Russell Kingcc20d422009-11-09 23:53:29 +0000871 swi __ARM_NR_cmpxchg
Nicolas Pitre5e097442006-01-18 22:38:49 +0000872 ldmfd sp!, {r7, pc}
Russell Kingcc20d422009-11-09 23:53:29 +00008731: .word __ARM_NR_cmpxchg
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100874
875#elif __LINUX_ARM_ARCH__ < 6
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100876
Nicolas Pitre49bca4c2006-02-08 21:19:37 +0000877#ifdef CONFIG_MMU
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100878
879 /*
880 * The only thing that can break atomicity in this cmpxchg
881 * implementation is either an IRQ or a data abort exception
882 * causing another process/thread to be scheduled in the middle
883 * of the critical sequence. To prevent this, code is added to
884 * the IRQ and data abort exception handlers to set the pc back
885 * to the beginning of the critical section if it is found to be
886 * within that critical section (see kuser_cmpxchg_fixup).
887 */
8881: ldr r3, [r2] @ load current val
889 subs r3, r3, r0 @ compare with oldval
8902: streq r1, [r2] @ store newval if eq
891 rsbs r0, r3, #0 @ set return val and C flag
892 usr_ret lr
893
894 .text
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400895kuser_cmpxchg32_fixup:
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100896 @ Called from kuser_cmpxchg_check macro.
Russell Kingb059bdc2011-06-25 15:44:20 +0100897 @ r4 = address of interrupted insn (must be preserved).
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100898 @ sp = saved regs. r7 and r8 are clobbered.
899 @ 1b = first critical insn, 2b = last critical insn.
Russell Kingb059bdc2011-06-25 15:44:20 +0100900 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100901 mov r7, #0xffff0fff
902 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
Russell Kingb059bdc2011-06-25 15:44:20 +0100903 subs r8, r4, r7
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100904 rsbcss r8, r8, #(2b - 1b)
905 strcs r7, [sp, #S_PC]
906 mov pc, lr
907 .previous
908
Nicolas Pitre49bca4c2006-02-08 21:19:37 +0000909#else
910#warning "NPTL on non MMU needs fixing"
911 mov r0, #-1
912 adds r0, r0, #0
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100913 usr_ret lr
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100914#endif
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100915
916#else
917
Dave Martined3768a2010-12-01 15:39:23 +0100918 smp_dmb arm
Nicolas Pitreb49c0f22007-11-20 17:20:29 +01009191: ldrex r3, [r2]
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100920 subs r3, r3, r0
921 strexeq r3, r1, [r2]
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100922 teqeq r3, #1
923 beq 1b
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100924 rsbs r0, r3, #0
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100925 /* beware -- each __kuser slot must be 8 instructions max */
Russell Kingf00ec482010-09-04 10:47:48 +0100926 ALT_SMP(b __kuser_memory_barrier)
927 ALT_UP(usr_ret lr)
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100928
929#endif
930
931 .align 5
932
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100933__kuser_get_tls: @ 0xffff0fe0
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100934 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100935 usr_ret lr
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100936 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
937 .rep 4
938 .word 0 @ 0xffff0ff0 software TLS value, then
939 .endr @ pad up to __kuser_helper_version
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100940
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100941__kuser_helper_version: @ 0xffff0ffc
942 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
943
944 .globl __kuser_helper_end
945__kuser_helper_end:
946
Catalin Marinasb86040a2009-07-24 12:32:54 +0100947 THUMB( .thumb )
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100948
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949/*
950 * Vector stubs.
951 *
Russell King79335232005-04-26 15:17:42 +0100952 * This code is copied to 0xffff0200 so we can use branches in the
953 * vectors, rather than ldr's. Note that this code must not
954 * exceed 0x300 bytes.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955 *
956 * Common stub entry macro:
957 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
Russell Kingccea7a12005-05-31 22:22:32 +0100958 *
959 * SP points to a minimal amount of processor-private memory, the address
960 * of which is copied into r0 for the mode specific abort handler.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +0000962 .macro vector_stub, name, mode, correction=0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700963 .align 5
964
965vector_\name:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700966 .if \correction
967 sub lr, lr, #\correction
968 .endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969
Russell Kingccea7a12005-05-31 22:22:32 +0100970 @
971 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
972 @ (parent CPSR)
973 @
974 stmia sp, {r0, lr} @ save r0, lr
975 mrs lr, spsr
976 str lr, [sp, #8] @ save spsr
977
978 @
979 @ Prepare for SVC32 mode. IRQs remain disabled.
980 @
981 mrs r0, cpsr
Catalin Marinasb86040a2009-07-24 12:32:54 +0100982 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
Russell Kingccea7a12005-05-31 22:22:32 +0100983 msr spsr_cxsf, r0
984
985 @
986 @ the branch table must immediately follow this code
987 @
Russell Kingccea7a12005-05-31 22:22:32 +0100988 and lr, lr, #0x0f
Catalin Marinasb86040a2009-07-24 12:32:54 +0100989 THUMB( adr r0, 1f )
990 THUMB( ldr lr, [r0, lr, lsl #2] )
Nicolas Pitreb7ec4792005-11-06 14:42:37 +0000991 mov r0, sp
Catalin Marinasb86040a2009-07-24 12:32:54 +0100992 ARM( ldr lr, [pc, lr, lsl #2] )
Russell Kingccea7a12005-05-31 22:22:32 +0100993 movs pc, lr @ branch to handler in SVC mode
Catalin Marinas93ed3972008-08-28 11:22:32 +0100994ENDPROC(vector_\name)
Catalin Marinas88987ef2009-07-24 12:32:52 +0100995
996 .align 2
997 @ handler addresses follow this label
9981:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 .endm
1000
Russell King79335232005-04-26 15:17:42 +01001001 .globl __stubs_start
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002__stubs_start:
1003/*
1004 * Interrupt dispatcher
1005 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001006 vector_stub irq, IRQ_MODE, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007
1008 .long __irq_usr @ 0 (USR_26 / USR_32)
1009 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1010 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1011 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1012 .long __irq_invalid @ 4
1013 .long __irq_invalid @ 5
1014 .long __irq_invalid @ 6
1015 .long __irq_invalid @ 7
1016 .long __irq_invalid @ 8
1017 .long __irq_invalid @ 9
1018 .long __irq_invalid @ a
1019 .long __irq_invalid @ b
1020 .long __irq_invalid @ c
1021 .long __irq_invalid @ d
1022 .long __irq_invalid @ e
1023 .long __irq_invalid @ f
1024
1025/*
1026 * Data abort dispatcher
1027 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1028 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001029 vector_stub dabt, ABT_MODE, 8
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030
1031 .long __dabt_usr @ 0 (USR_26 / USR_32)
1032 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1033 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1034 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1035 .long __dabt_invalid @ 4
1036 .long __dabt_invalid @ 5
1037 .long __dabt_invalid @ 6
1038 .long __dabt_invalid @ 7
1039 .long __dabt_invalid @ 8
1040 .long __dabt_invalid @ 9
1041 .long __dabt_invalid @ a
1042 .long __dabt_invalid @ b
1043 .long __dabt_invalid @ c
1044 .long __dabt_invalid @ d
1045 .long __dabt_invalid @ e
1046 .long __dabt_invalid @ f
1047
1048/*
1049 * Prefetch abort dispatcher
1050 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1051 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001052 vector_stub pabt, ABT_MODE, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053
1054 .long __pabt_usr @ 0 (USR_26 / USR_32)
1055 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1056 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1057 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1058 .long __pabt_invalid @ 4
1059 .long __pabt_invalid @ 5
1060 .long __pabt_invalid @ 6
1061 .long __pabt_invalid @ 7
1062 .long __pabt_invalid @ 8
1063 .long __pabt_invalid @ 9
1064 .long __pabt_invalid @ a
1065 .long __pabt_invalid @ b
1066 .long __pabt_invalid @ c
1067 .long __pabt_invalid @ d
1068 .long __pabt_invalid @ e
1069 .long __pabt_invalid @ f
1070
1071/*
1072 * Undef instr entry dispatcher
1073 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1074 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001075 vector_stub und, UND_MODE
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076
1077 .long __und_usr @ 0 (USR_26 / USR_32)
1078 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1079 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1080 .long __und_svc @ 3 (SVC_26 / SVC_32)
1081 .long __und_invalid @ 4
1082 .long __und_invalid @ 5
1083 .long __und_invalid @ 6
1084 .long __und_invalid @ 7
1085 .long __und_invalid @ 8
1086 .long __und_invalid @ 9
1087 .long __und_invalid @ a
1088 .long __und_invalid @ b
1089 .long __und_invalid @ c
1090 .long __und_invalid @ d
1091 .long __und_invalid @ e
1092 .long __und_invalid @ f
1093
1094 .align 5
1095
1096/*=============================================================================
1097 * Undefined FIQs
1098 *-----------------------------------------------------------------------------
1099 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1100 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1101 * Basically to switch modes, we *HAVE* to clobber one register... brain
1102 * damage alert! I don't think that we can execute any code in here in any
1103 * other mode than FIQ... Ok you can switch to another mode, but you can't
1104 * get out of that mode without clobbering one register.
1105 */
1106vector_fiq:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107 subs pc, lr, #4
1108
1109/*=============================================================================
1110 * Address exception handler
1111 *-----------------------------------------------------------------------------
1112 * These aren't too critical.
1113 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1114 */
1115
1116vector_addrexcptn:
1117 b vector_addrexcptn
1118
1119/*
1120 * We group all the following data together to optimise
1121 * for CPUs with separate I & D caches.
1122 */
1123 .align 5
1124
1125.LCvswi:
1126 .word vector_swi
1127
Russell King79335232005-04-26 15:17:42 +01001128 .globl __stubs_end
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129__stubs_end:
1130
Russell King79335232005-04-26 15:17:42 +01001131 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
Linus Torvalds1da177e2005-04-16 15:20:36 -07001132
Russell King79335232005-04-26 15:17:42 +01001133 .globl __vectors_start
1134__vectors_start:
Catalin Marinasb86040a2009-07-24 12:32:54 +01001135 ARM( swi SYS_ERROR0 )
1136 THUMB( svc #0 )
1137 THUMB( nop )
1138 W(b) vector_und + stubs_offset
1139 W(ldr) pc, .LCvswi + stubs_offset
1140 W(b) vector_pabt + stubs_offset
1141 W(b) vector_dabt + stubs_offset
1142 W(b) vector_addrexcptn + stubs_offset
1143 W(b) vector_irq + stubs_offset
1144 W(b) vector_fiq + stubs_offset
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145
Russell King79335232005-04-26 15:17:42 +01001146 .globl __vectors_end
1147__vectors_end:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148
1149 .data
1150
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151 .globl cr_alignment
1152 .globl cr_no_alignment
1153cr_alignment:
1154 .space 4
1155cr_no_alignment:
1156 .space 4
eric miao52108642010-12-13 09:42:34 +01001157
1158#ifdef CONFIG_MULTI_IRQ_HANDLER
1159 .globl handle_arch_irq
1160handle_arch_irq:
1161 .space 4
1162#endif