Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_oneplus_msm8996 / 6f74dc9bc8de41f3de474a7269a70921e773c40f / . / arch / arm / boot / dts / tegra20.dtsi
blob: ec1f0101c79c928762d22b2339dc6c9d14c777af [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Stephen Warrend17adfd2012-01-25 14:43:27 -0700[diff] [blame]7 pmc@7000f400 {
8 compatible = "nvidia,tegra20-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]12 intc: interrupt-controller@50041000 {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]13 compatible = "arm,cortex-a9-gic";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]14 interrupt-controller;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]15 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]16 reg = < 0x50041000 0x1000 >,
17 < 0x50040100 0x0100 >;
18 };
19
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]20 apbdma: dma@6000a000 {
21 compatible = "nvidia,tegra20-apbdma";
22 reg = <0x6000a000 0x1200>;
23 interrupts = < 0 104 0x04
24 0 105 0x04
25 0 106 0x04
26 0 107 0x04
27 0 108 0x04
28 0 109 0x04
29 0 110 0x04
30 0 111 0x04
31 0 112 0x04
32 0 113 0x04
33 0 114 0x04
34 0 115 0x04
35 0 116 0x04
36 0 117 0x04
37 0 118 0x04
38 0 119 0x04 >;
39 };
40
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]41 i2c@7000c000 {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 compatible = "nvidia,tegra20-i2c";
45 reg = <0x7000C000 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]46 interrupts = < 0 38 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]47 };
48
49 i2c@7000c400 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 compatible = "nvidia,tegra20-i2c";
53 reg = <0x7000C400 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]54 interrupts = < 0 84 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]55 };
56
57 i2c@7000c500 {
58 #address-cells = <1>;
59 #size-cells = <0>;
60 compatible = "nvidia,tegra20-i2c";
61 reg = <0x7000C500 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]62 interrupts = < 0 92 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]63 };
64
65 i2c@7000d000 {
66 #address-cells = <1>;
67 #size-cells = <0>;
Stephen Warren0bc2ecb2011-12-17 23:29:31 -0700[diff] [blame]68 compatible = "nvidia,tegra20-i2c-dvc";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]69 reg = <0x7000D000 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]70 interrupts = < 0 53 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]71 };
72
Stephen Warrenc404af02012-01-11 16:09:56 -0700[diff] [blame]73 tegra_i2s1: i2s@70002800 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]74 compatible = "nvidia,tegra20-i2s";
75 reg = <0x70002800 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]76 interrupts = < 0 13 0x04 >;
Stephen Warren5c8ee312012-01-11 16:09:55 -0700[diff] [blame]77 nvidia,dma-request-selector = < &apbdma 2 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]78 };
79
Stephen Warrenc404af02012-01-11 16:09:56 -0700[diff] [blame]80 tegra_i2s2: i2s@70002a00 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]81 compatible = "nvidia,tegra20-i2s";
82 reg = <0x70002a00 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]83 interrupts = < 0 3 0x04 >;
Stephen Warren5c8ee312012-01-11 16:09:55 -0700[diff] [blame]84 nvidia,dma-request-selector = < &apbdma 1 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]85 };
86
87 das@70000c00 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]88 compatible = "nvidia,tegra20-das";
89 reg = <0x70000c00 0x80>;
90 };
91
92 gpio: gpio@6000d000 {
93 compatible = "nvidia,tegra20-gpio";
94 reg = < 0x6000d000 0x1000 >;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]95 interrupts = < 0 32 0x04
96 0 33 0x04
97 0 34 0x04
98 0 35 0x04
99 0 55 0x04
100 0 87 0x04
101 0 89 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]102 #gpio-cells = <2>;
103 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame^]104 #interrupt-cells = <2>;
105 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]106 };
107
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]108 pinmux: pinmux@70000000 {
109 compatible = "nvidia,tegra20-pinmux";
110 reg = < 0x70000014 0x10 /* Tri-state registers */
111 0x70000080 0x20 /* Mux registers */
112 0x700000a0 0x14 /* Pull-up/down registers */
113 0x70000868 0xa8 >; /* Pad control registers */
114 };
115
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]116 serial@70006000 {
117 compatible = "nvidia,tegra20-uart";
118 reg = <0x70006000 0x40>;
119 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]120 interrupts = < 0 36 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]121 };
122
123 serial@70006040 {
124 compatible = "nvidia,tegra20-uart";
125 reg = <0x70006040 0x40>;
126 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]127 interrupts = < 0 37 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]128 };
129
130 serial@70006200 {
131 compatible = "nvidia,tegra20-uart";
132 reg = <0x70006200 0x100>;
133 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]134 interrupts = < 0 46 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]135 };
136
137 serial@70006300 {
138 compatible = "nvidia,tegra20-uart";
139 reg = <0x70006300 0x100>;
140 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]141 interrupts = < 0 90 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]142 };
143
144 serial@70006400 {
145 compatible = "nvidia,tegra20-uart";
146 reg = <0x70006400 0x100>;
147 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]148 interrupts = < 0 91 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]149 };
150
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]151 emc@7000f400 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 compatible = "nvidia,tegra20-emc";
155 reg = <0x7000f400 0x200>;
156 };
157
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]158 sdhci@c8000000 {
159 compatible = "nvidia,tegra20-sdhci";
160 reg = <0xc8000000 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]161 interrupts = < 0 14 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]162 };
163
164 sdhci@c8000200 {
165 compatible = "nvidia,tegra20-sdhci";
166 reg = <0xc8000200 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]167 interrupts = < 0 15 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]168 };
169
170 sdhci@c8000400 {
171 compatible = "nvidia,tegra20-sdhci";
172 reg = <0xc8000400 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]173 interrupts = < 0 19 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]174 };
175
176 sdhci@c8000600 {
177 compatible = "nvidia,tegra20-sdhci";
178 reg = <0xc8000600 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]179 interrupts = < 0 31 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]180 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]181
182 usb@c5000000 {
183 compatible = "nvidia,tegra20-ehci", "usb-ehci";
184 reg = <0xc5000000 0x4000>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]185 interrupts = < 0 20 0x04 >;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]186 phy_type = "utmi";
187 };
188
189 usb@c5004000 {
190 compatible = "nvidia,tegra20-ehci", "usb-ehci";
191 reg = <0xc5004000 0x4000>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]192 interrupts = < 0 21 0x04 >;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]193 phy_type = "ulpi";
194 };
195
196 usb@c5008000 {
197 compatible = "nvidia,tegra20-ehci", "usb-ehci";
198 reg = <0xc5008000 0x4000>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]199 interrupts = < 0 97 0x04 >;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]200 phy_type = "utmi";
201 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]202};
203