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review.evervolv.com / android_kernel_oneplus_msm8996 / 6f88fb8af6c67f281b8e2cd607f08e0089c8ccbe / . / arch / arm / boot / dts / tegra20.dtsi
blob: 37701d8727d81b4571aa0a538c33e20406d3384b [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 serial4 = &uarte;
13 };
14
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]15 host1x {
16 compatible = "nvidia,tegra20-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */
19 0 67 0x04>; /* mpcore general */
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]20 clocks = <&tegra_car 28>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]21
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x54000000 0x54000000 0x04000000>;
26
27 mpe {
28 compatible = "nvidia,tegra20-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]31 clocks = <&tegra_car 60>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]32 };
33
34 vi {
35 compatible = "nvidia,tegra20-vi";
36 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]38 clocks = <&tegra_car 100>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]39 };
40
41 epp {
42 compatible = "nvidia,tegra20-epp";
43 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]45 clocks = <&tegra_car 19>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]46 };
47
48 isp {
49 compatible = "nvidia,tegra20-isp";
50 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]52 clocks = <&tegra_car 23>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]53 };
54
55 gr2d {
56 compatible = "nvidia,tegra20-gr2d";
57 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]59 clocks = <&tegra_car 21>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]60 };
61
62 gr3d {
63 compatible = "nvidia,tegra20-gr3d";
64 reg = <0x54180000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]65 clocks = <&tegra_car 24>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]66 };
67
68 dc@54200000 {
69 compatible = "nvidia,tegra20-dc";
70 reg = <0x54200000 0x00040000>;
71 interrupts = <0 73 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]72 clocks = <&tegra_car 27>, <&tegra_car 121>;
73 clock-names = "disp1", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]74
75 rgb {
76 status = "disabled";
77 };
78 };
79
80 dc@54240000 {
81 compatible = "nvidia,tegra20-dc";
82 reg = <0x54240000 0x00040000>;
83 interrupts = <0 74 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]84 clocks = <&tegra_car 26>, <&tegra_car 121>;
85 clock-names = "disp2", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]86
87 rgb {
88 status = "disabled";
89 };
90 };
91
92 hdmi {
93 compatible = "nvidia,tegra20-hdmi";
94 reg = <0x54280000 0x00040000>;
95 interrupts = <0 75 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]96 clocks = <&tegra_car 51>, <&tegra_car 117>;
97 clock-names = "hdmi", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]98 status = "disabled";
99 };
100
101 tvo {
102 compatible = "nvidia,tegra20-tvo";
103 reg = <0x542c0000 0x00040000>;
104 interrupts = <0 76 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]105 clocks = <&tegra_car 102>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]106 status = "disabled";
107 };
108
109 dsi {
110 compatible = "nvidia,tegra20-dsi";
111 reg = <0x54300000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]112 clocks = <&tegra_car 48>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]113 status = "disabled";
114 };
115 };
116
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]117 timer@50004600 {
118 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0x50040600 0x20>;
120 interrupts = <1 13 0x304>;
121 };
122
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]123 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]124 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]125 reg = <0x50041000 0x1000
126 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]127 interrupt-controller;
128 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]129 };
130
Stephen Warrenbb2c1de2013-01-14 10:09:16 -0700[diff] [blame]131 cache-controller {
132 compatible = "arm,pl310-cache";
133 reg = <0x50043000 0x1000>;
134 arm,data-latency = <5 5 2>;
135 arm,tag-latency = <4 4 2>;
136 cache-unified;
137 cache-level = <2>;
138 };
139
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]140 timer@60005000 {
141 compatible = "nvidia,tegra20-timer";
142 reg = <0x60005000 0x60>;
143 interrupts = <0 0 0x04
144 0 1 0x04
145 0 41 0x04
146 0 42 0x04>;
Peter De Schrijver6f88fb82013-02-04 15:40:30 +0200[diff] [blame^]147 clocks = <&tegra_car 5>;
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]148 };
149
Stephen Warren270f8ce2013-01-11 13:16:22 +0530[diff] [blame]150 tegra_car: clock {
151 compatible = "nvidia,tegra20-car";
152 reg = <0x60006000 0x1000>;
153 #clock-cells = <1>;
154 };
155
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]156 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]157 compatible = "nvidia,tegra20-apbdma";
158 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]159 interrupts = <0 104 0x04
160 0 105 0x04
161 0 106 0x04
162 0 107 0x04
163 0 108 0x04
164 0 109 0x04
165 0 110 0x04
166 0 111 0x04
167 0 112 0x04
168 0 113 0x04
169 0 114 0x04
170 0 115 0x04
171 0 116 0x04
172 0 117 0x04
173 0 118 0x04
174 0 119 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]175 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]176 };
177
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]178 ahb {
179 compatible = "nvidia,tegra20-ahb";
180 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]181 };
182
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]183 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]184 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]185 reg = <0x6000d000 0x1000>;
186 interrupts = <0 32 0x04
187 0 33 0x04
188 0 34 0x04
189 0 35 0x04
190 0 55 0x04
191 0 87 0x04
192 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]193 #gpio-cells = <2>;
194 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]195 #interrupt-cells = <2>;
196 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]197 };
198
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]199 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]200 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]201 reg = <0x70000014 0x10 /* Tri-state registers */
202 0x70000080 0x20 /* Mux registers */
203 0x700000a0 0x14 /* Pull-up/down registers */
204 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]205 };
206
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]207 das {
208 compatible = "nvidia,tegra20-das";
209 reg = <0x70000c00 0x80>;
210 };
Lucas Stach0698ed12013-01-05 02:18:44 +0100[diff] [blame]211
212 tegra_ac97: ac97 {
213 compatible = "nvidia,tegra20-ac97";
214 reg = <0x70002000 0x200>;
215 interrupts = <0 81 0x04>;
216 nvidia,dma-request-selector = <&apbdma 12>;
217 clocks = <&tegra_car 3>;
218 status = "disabled";
219 };
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]220
221 tegra_i2s1: i2s@70002800 {
222 compatible = "nvidia,tegra20-i2s";
223 reg = <0x70002800 0x200>;
224 interrupts = <0 13 0x04>;
225 nvidia,dma-request-selector = <&apbdma 2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]226 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]227 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]228 };
229
230 tegra_i2s2: i2s@70002a00 {
231 compatible = "nvidia,tegra20-i2s";
232 reg = <0x70002a00 0x200>;
233 interrupts = <0 3 0x04>;
234 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]235 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]236 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]237 };
238
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]239 /*
240 * There are two serial driver i.e. 8250 based simple serial
241 * driver and APB DMA based serial driver for higher baudrate
242 * and performace. To enable the 8250 based driver, the compatible
243 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
244 * driver, the comptible is "nvidia,tegra20-hsuart".
245 */
246 uarta: serial@70006000 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]247 compatible = "nvidia,tegra20-uart";
248 reg = <0x70006000 0x40>;
249 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]250 interrupts = <0 36 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]251 nvidia,dma-request-selector = <&apbdma 8>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]252 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]253 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]254 };
255
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]256 uartb: serial@70006040 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]257 compatible = "nvidia,tegra20-uart";
258 reg = <0x70006040 0x40>;
259 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]260 interrupts = <0 37 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]261 nvidia,dma-request-selector = <&apbdma 9>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]262 clocks = <&tegra_car 96>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]263 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]264 };
265
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]266 uartc: serial@70006200 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]267 compatible = "nvidia,tegra20-uart";
268 reg = <0x70006200 0x100>;
269 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]270 interrupts = <0 46 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]271 nvidia,dma-request-selector = <&apbdma 10>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]272 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]273 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]274 };
275
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]276 uartd: serial@70006300 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]277 compatible = "nvidia,tegra20-uart";
278 reg = <0x70006300 0x100>;
279 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]280 interrupts = <0 90 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]281 nvidia,dma-request-selector = <&apbdma 19>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]282 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]283 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]284 };
285
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]286 uarte: serial@70006400 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]287 compatible = "nvidia,tegra20-uart";
288 reg = <0x70006400 0x100>;
289 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]290 interrupts = <0 91 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]291 nvidia,dma-request-selector = <&apbdma 20>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]292 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]293 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]294 };
295
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]296 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]297 compatible = "nvidia,tegra20-pwm";
298 reg = <0x7000a000 0x100>;
299 #pwm-cells = <2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]300 clocks = <&tegra_car 17>;
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]301 };
302
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]303 rtc {
304 compatible = "nvidia,tegra20-rtc";
305 reg = <0x7000e000 0x100>;
306 interrupts = <0 2 0x04>;
Peter De Schrijver6f88fb82013-02-04 15:40:30 +0200[diff] [blame^]307 clocks = <&tegra_car 4>;
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]308 };
309
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]310 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]311 compatible = "nvidia,tegra20-i2c";
312 reg = <0x7000c000 0x100>;
313 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]314 #address-cells = <1>;
315 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]316 clocks = <&tegra_car 12>, <&tegra_car 124>;
317 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]318 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]319 };
320
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]321 spi@7000c380 {
322 compatible = "nvidia,tegra20-sflash";
323 reg = <0x7000c380 0x80>;
324 interrupts = <0 39 0x04>;
325 nvidia,dma-request-selector = <&apbdma 11>;
326 #address-cells = <1>;
327 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]328 clocks = <&tegra_car 43>;
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]329 status = "disabled";
330 };
331
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]332 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]333 compatible = "nvidia,tegra20-i2c";
334 reg = <0x7000c400 0x100>;
335 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]336 #address-cells = <1>;
337 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]338 clocks = <&tegra_car 54>, <&tegra_car 124>;
339 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]340 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]341 };
342
343 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]344 compatible = "nvidia,tegra20-i2c";
345 reg = <0x7000c500 0x100>;
346 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]347 #address-cells = <1>;
348 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]349 clocks = <&tegra_car 67>, <&tegra_car 124>;
350 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]351 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]352 };
353
354 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]355 compatible = "nvidia,tegra20-i2c-dvc";
356 reg = <0x7000d000 0x200>;
357 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]358 #address-cells = <1>;
359 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]360 clocks = <&tegra_car 47>, <&tegra_car 124>;
361 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]362 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]363 };
364
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]365 spi@7000d400 {
366 compatible = "nvidia,tegra20-slink";
367 reg = <0x7000d400 0x200>;
368 interrupts = <0 59 0x04>;
369 nvidia,dma-request-selector = <&apbdma 15>;
370 #address-cells = <1>;
371 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]372 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]373 status = "disabled";
374 };
375
376 spi@7000d600 {
377 compatible = "nvidia,tegra20-slink";
378 reg = <0x7000d600 0x200>;
379 interrupts = <0 82 0x04>;
380 nvidia,dma-request-selector = <&apbdma 16>;
381 #address-cells = <1>;
382 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]383 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]384 status = "disabled";
385 };
386
387 spi@7000d800 {
388 compatible = "nvidia,tegra20-slink";
389 reg = <0x7000d480 0x200>;
390 interrupts = <0 83 0x04>;
391 nvidia,dma-request-selector = <&apbdma 17>;
392 #address-cells = <1>;
393 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]394 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]395 status = "disabled";
396 };
397
398 spi@7000da00 {
399 compatible = "nvidia,tegra20-slink";
400 reg = <0x7000da00 0x200>;
401 interrupts = <0 93 0x04>;
402 nvidia,dma-request-selector = <&apbdma 18>;
403 #address-cells = <1>;
404 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]405 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]406 status = "disabled";
407 };
408
Laxman Dewangan699ed4b2013-01-11 19:03:03 +0530[diff] [blame]409 kbc {
410 compatible = "nvidia,tegra20-kbc";
411 reg = <0x7000e200 0x100>;
412 interrupts = <0 85 0x04>;
413 clocks = <&tegra_car 36>;
414 status = "disabled";
415 };
416
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]417 pmc {
418 compatible = "nvidia,tegra20-pmc";
419 reg = <0x7000e400 0x400>;
420 };
421
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]422 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]423 compatible = "nvidia,tegra20-mc";
424 reg = <0x7000f000 0x024
425 0x7000f03c 0x3c4>;
426 interrupts = <0 77 0x04>;
427 };
428
Hiroshi Doyu109269e2013-01-29 10:30:30 +0200[diff] [blame]429 iommu {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]430 compatible = "nvidia,tegra20-gart";
431 reg = <0x7000f024 0x00000018 /* controller registers */
432 0x58000000 0x02000000>; /* GART aperture */
433 };
434
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]435 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]436 compatible = "nvidia,tegra20-emc";
437 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]438 #address-cells = <1>;
439 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]440 };
441
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]442 phy1: usb-phy@c5000400 {
443 compatible = "nvidia,tegra20-usb-phy";
444 reg = <0xc5000400 0x3c00>;
445 phy_type = "utmi";
446 nvidia,has-legacy-mode;
Stephen Warren540fc9d2013-01-22 17:12:25 -0700[diff] [blame]447 clocks = <&tegra_car 22>, <&tegra_car 127>;
448 clock-names = "phy", "pll_u";
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]449 };
450
451 phy2: usb-phy@c5004400 {
452 compatible = "nvidia,tegra20-usb-phy";
453 reg = <0xc5004400 0x3c00>;
454 phy_type = "ulpi";
Stephen Warren540fc9d2013-01-22 17:12:25 -0700[diff] [blame]455 clocks = <&tegra_car 94>, <&tegra_car 127>;
456 clock-names = "phy", "pll_u";
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]457 };
458
459 phy3: usb-phy@c5008400 {
460 compatible = "nvidia,tegra20-usb-phy";
461 reg = <0xc5008400 0x3C00>;
462 phy_type = "utmi";
Stephen Warren540fc9d2013-01-22 17:12:25 -0700[diff] [blame]463 clocks = <&tegra_car 22>, <&tegra_car 127>;
464 clock-names = "phy", "pll_u";
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]465 };
466
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]467 usb@c5000000 {
468 compatible = "nvidia,tegra20-ehci", "usb-ehci";
469 reg = <0xc5000000 0x4000>;
470 interrupts = <0 20 0x04>;
471 phy_type = "utmi";
472 nvidia,has-legacy-mode;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]473 clocks = <&tegra_car 22>;
Venu Byravarasub4e07472012-12-13 20:59:07 +0000[diff] [blame]474 nvidia,needs-double-reset;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]475 nvidia,phy = <&phy1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]476 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]477 };
478
479 usb@c5004000 {
480 compatible = "nvidia,tegra20-ehci", "usb-ehci";
481 reg = <0xc5004000 0x4000>;
482 interrupts = <0 21 0x04>;
483 phy_type = "ulpi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]484 clocks = <&tegra_car 58>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]485 nvidia,phy = <&phy2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]486 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]487 };
488
489 usb@c5008000 {
490 compatible = "nvidia,tegra20-ehci", "usb-ehci";
491 reg = <0xc5008000 0x4000>;
492 interrupts = <0 97 0x04>;
493 phy_type = "utmi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]494 clocks = <&tegra_car 59>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]495 nvidia,phy = <&phy3>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]496 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]497 };
498
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]499 sdhci@c8000000 {
500 compatible = "nvidia,tegra20-sdhci";
501 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]502 interrupts = <0 14 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]503 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]504 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]505 };
506
507 sdhci@c8000200 {
508 compatible = "nvidia,tegra20-sdhci";
509 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]510 interrupts = <0 15 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]511 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]512 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]513 };
514
515 sdhci@c8000400 {
516 compatible = "nvidia,tegra20-sdhci";
517 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]518 interrupts = <0 19 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]519 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]520 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]521 };
522
523 sdhci@c8000600 {
524 compatible = "nvidia,tegra20-sdhci";
525 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]526 interrupts = <0 31 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]527 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]528 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]529 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]530
Hiroshi Doyu4dd2bd32013-01-11 15:26:55 +0200[diff] [blame]531 cpus {
532 #address-cells = <1>;
533 #size-cells = <0>;
534
535 cpu@0 {
536 device_type = "cpu";
537 compatible = "arm,cortex-a9";
538 reg = <0>;
539 };
540
541 cpu@1 {
542 device_type = "cpu";
543 compatible = "arm,cortex-a9";
544 reg = <1>;
545 };
546 };
547
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]548 pmu {
549 compatible = "arm,cortex-a9-pmu";
550 interrupts = <0 56 0x04
551 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]552 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]553};