Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 1 | /* |
| 2 | * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC |
| 3 | * applies to AT91SAM9G45, AT91SAM9M10, |
| 4 | * AT91SAM9G46, AT91SAM9M11 SoC |
| 5 | * |
| 6 | * Copyright (C) 2011 Atmel, |
| 7 | * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> |
| 8 | * |
| 9 | * Licensed under GPLv2 or later. |
| 10 | */ |
| 11 | |
Jean-Christophe PLAGNIOL-VILLARD | 6db64d2 | 2013-05-15 01:21:50 +0800 | [diff] [blame] | 12 | #include "skeleton.dtsi" |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 13 | #include <dt-bindings/dma/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 14 | #include <dt-bindings/pinctrl/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 16 | #include <dt-bindings/gpio/gpio.h> |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 17 | |
| 18 | / { |
| 19 | model = "Atmel AT91SAM9G45 family SoC"; |
| 20 | compatible = "atmel,at91sam9g45"; |
| 21 | interrupt-parent = <&aic>; |
| 22 | |
| 23 | aliases { |
| 24 | serial0 = &dbgu; |
| 25 | serial1 = &usart0; |
| 26 | serial2 = &usart1; |
| 27 | serial3 = &usart2; |
| 28 | serial4 = &usart3; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 29 | gpio0 = &pioA; |
| 30 | gpio1 = &pioB; |
| 31 | gpio2 = &pioC; |
| 32 | gpio3 = &pioD; |
| 33 | gpio4 = &pioE; |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 34 | tcb0 = &tcb0; |
| 35 | tcb1 = &tcb1; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 36 | i2c0 = &i2c0; |
| 37 | i2c1 = &i2c1; |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 38 | ssc0 = &ssc0; |
| 39 | ssc1 = &ssc1; |
Bo Shen | f3ab052 | 2013-12-19 11:59:17 +0800 | [diff] [blame] | 40 | pwm0 = &pwm0; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 41 | }; |
| 42 | cpus { |
Lorenzo Pieralisi | e757a6e | 2013-04-18 18:31:35 +0100 | [diff] [blame] | 43 | #address-cells = <0>; |
| 44 | #size-cells = <0>; |
| 45 | |
| 46 | cpu { |
| 47 | compatible = "arm,arm926ej-s"; |
| 48 | device_type = "cpu"; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 49 | }; |
| 50 | }; |
| 51 | |
Ludovic Desroches | dcce6ce | 2012-04-02 20:44:20 +0200 | [diff] [blame] | 52 | memory { |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 53 | reg = <0x70000000 0x10000000>; |
| 54 | }; |
| 55 | |
| 56 | ahb { |
| 57 | compatible = "simple-bus"; |
| 58 | #address-cells = <1>; |
| 59 | #size-cells = <1>; |
| 60 | ranges; |
| 61 | |
| 62 | apb { |
| 63 | compatible = "simple-bus"; |
| 64 | #address-cells = <1>; |
| 65 | #size-cells = <1>; |
| 66 | ranges; |
| 67 | |
| 68 | aic: interrupt-controller@fffff000 { |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 69 | #interrupt-cells = <3>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 70 | compatible = "atmel,at91rm9200-aic"; |
| 71 | interrupt-controller; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 72 | reg = <0xfffff000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | c657394 | 2012-04-09 19:36:36 +0800 | [diff] [blame] | 73 | atmel,external-irqs = <31>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 74 | }; |
| 75 | |
Jean-Christophe PLAGNIOL-VILLARD | a7776ec | 2012-03-02 20:54:37 +0800 | [diff] [blame] | 76 | ramc0: ramc@ffffe400 { |
| 77 | compatible = "atmel,at91sam9g45-ddramc"; |
| 78 | reg = <0xffffe400 0x200 |
| 79 | 0xffffe600 0x200>; |
| 80 | }; |
| 81 | |
Jean-Christophe PLAGNIOL-VILLARD | eb5e76f | 2012-03-02 20:44:23 +0800 | [diff] [blame] | 82 | pmc: pmc@fffffc00 { |
| 83 | compatible = "atmel,at91rm9200-pmc"; |
| 84 | reg = <0xfffffc00 0x100>; |
| 85 | }; |
| 86 | |
Jean-Christophe PLAGNIOL-VILLARD | c8082d3 | 2012-03-03 03:16:27 +0800 | [diff] [blame] | 87 | rstc@fffffd00 { |
| 88 | compatible = "atmel,at91sam9g45-rstc"; |
| 89 | reg = <0xfffffd00 0x10>; |
| 90 | }; |
| 91 | |
Jean-Christophe PLAGNIOL-VILLARD | 23fa648 | 2012-02-27 11:19:34 +0100 | [diff] [blame] | 92 | pit: timer@fffffd30 { |
| 93 | compatible = "atmel,at91sam9260-pit"; |
| 94 | reg = <0xfffffd30 0xf>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 95 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Jean-Christophe PLAGNIOL-VILLARD | 23fa648 | 2012-02-27 11:19:34 +0100 | [diff] [blame] | 96 | }; |
| 97 | |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 98 | |
Jean-Christophe PLAGNIOL-VILLARD | 82015c4 | 2012-03-02 21:01:00 +0800 | [diff] [blame] | 99 | shdwc@fffffd10 { |
| 100 | compatible = "atmel,at91sam9rl-shdwc"; |
| 101 | reg = <0xfffffd10 0x10>; |
| 102 | }; |
| 103 | |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 104 | tcb0: timer@fff7c000 { |
| 105 | compatible = "atmel,at91rm9200-tcb"; |
| 106 | reg = <0xfff7c000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 107 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 108 | }; |
| 109 | |
| 110 | tcb1: timer@fffd4000 { |
| 111 | compatible = "atmel,at91rm9200-tcb"; |
| 112 | reg = <0xfffd4000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 113 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 114 | }; |
| 115 | |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 116 | dma: dma-controller@ffffec00 { |
| 117 | compatible = "atmel,at91sam9g45-dma"; |
| 118 | reg = <0xffffec00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 119 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 980ce7d | 2013-04-16 15:03:06 +0200 | [diff] [blame] | 120 | #dma-cells = <2>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 121 | }; |
| 122 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 123 | pinctrl@fffff200 { |
| 124 | #address-cells = <1>; |
| 125 | #size-cells = <1>; |
| 126 | compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; |
| 127 | ranges = <0xfffff200 0xfffff200 0xa00>; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 128 | |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 129 | atmel,mux-mask = < |
| 130 | /* A B */ |
| 131 | 0xffffffff 0xffc003ff /* pioA */ |
| 132 | 0xffffffff 0x800f8f00 /* pioB */ |
| 133 | 0xffffffff 0x00000e00 /* pioC */ |
| 134 | 0xffffffff 0xff0c1381 /* pioD */ |
| 135 | 0xffffffff 0x81ffff81 /* pioE */ |
| 136 | >; |
| 137 | |
| 138 | /* shared pinctrl settings */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 139 | dbgu { |
| 140 | pinctrl_dbgu: dbgu-0 { |
| 141 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 142 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ |
| 143 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 144 | }; |
| 145 | }; |
| 146 | |
Ludovic Desroches | cd127e1 | 2013-11-22 14:49:53 +0100 | [diff] [blame] | 147 | i2c0 { |
| 148 | pinctrl_i2c0: i2c0-0 { |
| 149 | atmel,pins = |
| 150 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */ |
| 151 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */ |
| 152 | }; |
| 153 | }; |
| 154 | |
| 155 | i2c1 { |
| 156 | pinctrl_i2c1: i2c1-0 { |
| 157 | atmel,pins = |
| 158 | <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */ |
| 159 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */ |
| 160 | }; |
| 161 | }; |
| 162 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 163 | usart0 { |
| 164 | pinctrl_usart0: usart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 165 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 166 | <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */ |
| 167 | AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 168 | }; |
| 169 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 170 | pinctrl_usart0_rts: usart0_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 171 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 172 | <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 173 | }; |
| 174 | |
| 175 | pinctrl_usart0_cts: usart0_cts-0 { |
| 176 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 177 | <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 178 | }; |
| 179 | }; |
| 180 | |
| 181 | uart1 { |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 182 | pinctrl_usart1: usart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 183 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 184 | <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */ |
| 185 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 186 | }; |
| 187 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 188 | pinctrl_usart1_rts: usart1_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 189 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 190 | <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | pinctrl_usart1_cts: usart1_cts-0 { |
| 194 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 195 | <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 196 | }; |
| 197 | }; |
| 198 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 199 | usart2 { |
| 200 | pinctrl_usart2: usart2-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 201 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 202 | <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ |
| 203 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 204 | }; |
| 205 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 206 | pinctrl_usart2_rts: usart2_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 207 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 208 | <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 209 | }; |
| 210 | |
| 211 | pinctrl_usart2_cts: usart2_cts-0 { |
| 212 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 213 | <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 214 | }; |
| 215 | }; |
| 216 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 217 | usart3 { |
| 218 | pinctrl_usart3: usart3-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 219 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 220 | <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */ |
| 221 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 222 | }; |
| 223 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 224 | pinctrl_usart3_rts: usart3_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 225 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 226 | <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | pinctrl_usart3_cts: usart3_cts-0 { |
| 230 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 231 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 232 | }; |
| 233 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 234 | |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 235 | nand { |
| 236 | pinctrl_nand: nand-0 { |
| 237 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 238 | <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/ |
| 239 | AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 240 | }; |
| 241 | }; |
| 242 | |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 243 | macb { |
| 244 | pinctrl_macb_rmii: macb_rmii-0 { |
| 245 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 246 | <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ |
| 247 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ |
| 248 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ |
| 249 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ |
| 250 | AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ |
| 251 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ |
| 252 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ |
| 253 | AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 254 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ |
| 255 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 256 | }; |
| 257 | |
| 258 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { |
| 259 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 260 | <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */ |
| 261 | AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */ |
| 262 | AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */ |
| 263 | AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */ |
| 264 | AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 265 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 266 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */ |
| 267 | AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 268 | }; |
| 269 | }; |
| 270 | |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 271 | mmc0 { |
| 272 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 273 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 274 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */ |
| 275 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
| 276 | AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 277 | }; |
| 278 | |
| 279 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 280 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 281 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ |
| 282 | AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ |
| 283 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 284 | }; |
| 285 | |
| 286 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { |
| 287 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 288 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ |
| 289 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
| 290 | AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ |
| 291 | AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 292 | }; |
| 293 | }; |
| 294 | |
| 295 | mmc1 { |
| 296 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { |
| 297 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 298 | <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */ |
| 299 | AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */ |
| 300 | AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 301 | }; |
| 302 | |
| 303 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { |
| 304 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 305 | <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ |
| 306 | AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */ |
| 307 | AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 308 | }; |
| 309 | |
| 310 | pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { |
| 311 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 312 | <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */ |
| 313 | AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ |
| 314 | AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */ |
| 315 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 316 | }; |
| 317 | }; |
| 318 | |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 319 | ssc0 { |
| 320 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 321 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 322 | <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */ |
| 323 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */ |
| 324 | AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 325 | }; |
| 326 | |
| 327 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 328 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 329 | <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */ |
| 330 | AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */ |
| 331 | AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 332 | }; |
| 333 | }; |
| 334 | |
| 335 | ssc1 { |
| 336 | pinctrl_ssc1_tx: ssc1_tx-0 { |
| 337 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 338 | <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */ |
| 339 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */ |
| 340 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 341 | }; |
| 342 | |
| 343 | pinctrl_ssc1_rx: ssc1_rx-0 { |
| 344 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 345 | <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */ |
| 346 | AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */ |
| 347 | AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 348 | }; |
| 349 | }; |
| 350 | |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 351 | spi0 { |
| 352 | pinctrl_spi0: spi0-0 { |
| 353 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 354 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */ |
| 355 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */ |
| 356 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 357 | }; |
| 358 | }; |
| 359 | |
| 360 | spi1 { |
| 361 | pinctrl_spi1: spi1-0 { |
| 362 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 363 | <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */ |
| 364 | AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */ |
| 365 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 366 | }; |
| 367 | }; |
| 368 | |
Boris BREZILLON | 028633c | 2013-05-24 10:05:56 +0000 | [diff] [blame] | 369 | tcb0 { |
| 370 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { |
| 371 | atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 372 | }; |
| 373 | |
| 374 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { |
| 375 | atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 376 | }; |
| 377 | |
| 378 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { |
| 379 | atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 380 | }; |
| 381 | |
| 382 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { |
| 383 | atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 384 | }; |
| 385 | |
| 386 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { |
| 387 | atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 388 | }; |
| 389 | |
| 390 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { |
| 391 | atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 392 | }; |
| 393 | |
| 394 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { |
| 395 | atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 396 | }; |
| 397 | |
| 398 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { |
| 399 | atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 400 | }; |
| 401 | |
| 402 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { |
| 403 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 404 | }; |
| 405 | }; |
| 406 | |
| 407 | tcb1 { |
| 408 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { |
| 409 | atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 410 | }; |
| 411 | |
| 412 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { |
| 413 | atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 414 | }; |
| 415 | |
| 416 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { |
| 417 | atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 418 | }; |
| 419 | |
| 420 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { |
| 421 | atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 422 | }; |
| 423 | |
| 424 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { |
| 425 | atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 426 | }; |
| 427 | |
| 428 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { |
| 429 | atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 430 | }; |
| 431 | |
| 432 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { |
| 433 | atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 434 | }; |
| 435 | |
| 436 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { |
| 437 | atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 438 | }; |
| 439 | |
| 440 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { |
| 441 | atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 442 | }; |
| 443 | }; |
| 444 | |
Jean-Christophe PLAGNIOL-VILLARD | ddee65b | 2013-03-29 02:10:47 +0800 | [diff] [blame] | 445 | fb { |
| 446 | pinctrl_fb: fb-0 { |
| 447 | atmel,pins = |
| 448 | <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */ |
| 449 | AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */ |
| 450 | AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */ |
| 451 | AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */ |
| 452 | AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */ |
| 453 | AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */ |
| 454 | AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */ |
| 455 | AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */ |
| 456 | AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */ |
| 457 | AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */ |
| 458 | AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */ |
| 459 | AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */ |
| 460 | AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */ |
| 461 | AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */ |
| 462 | AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */ |
| 463 | AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */ |
| 464 | AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */ |
| 465 | AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */ |
| 466 | AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */ |
| 467 | AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */ |
| 468 | AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ |
| 469 | AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */ |
| 470 | AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ |
| 471 | AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ |
| 472 | AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ |
| 473 | AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ |
| 474 | AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ |
| 475 | AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ |
| 476 | AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ |
| 477 | AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ |
| 478 | }; |
| 479 | }; |
| 480 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 481 | pioA: gpio@fffff200 { |
| 482 | compatible = "atmel,at91rm9200-gpio"; |
| 483 | reg = <0xfffff200 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 484 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 485 | #gpio-cells = <2>; |
| 486 | gpio-controller; |
| 487 | interrupt-controller; |
| 488 | #interrupt-cells = <2>; |
| 489 | }; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 490 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 491 | pioB: gpio@fffff400 { |
| 492 | compatible = "atmel,at91rm9200-gpio"; |
| 493 | reg = <0xfffff400 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 494 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 495 | #gpio-cells = <2>; |
| 496 | gpio-controller; |
| 497 | interrupt-controller; |
| 498 | #interrupt-cells = <2>; |
| 499 | }; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 500 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 501 | pioC: gpio@fffff600 { |
| 502 | compatible = "atmel,at91rm9200-gpio"; |
| 503 | reg = <0xfffff600 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 504 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 505 | #gpio-cells = <2>; |
| 506 | gpio-controller; |
| 507 | interrupt-controller; |
| 508 | #interrupt-cells = <2>; |
| 509 | }; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 510 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 511 | pioD: gpio@fffff800 { |
| 512 | compatible = "atmel,at91rm9200-gpio"; |
| 513 | reg = <0xfffff800 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 514 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 515 | #gpio-cells = <2>; |
| 516 | gpio-controller; |
| 517 | interrupt-controller; |
| 518 | #interrupt-cells = <2>; |
| 519 | }; |
| 520 | |
| 521 | pioE: gpio@fffffa00 { |
| 522 | compatible = "atmel,at91rm9200-gpio"; |
| 523 | reg = <0xfffffa00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 524 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 525 | #gpio-cells = <2>; |
| 526 | gpio-controller; |
| 527 | interrupt-controller; |
| 528 | #interrupt-cells = <2>; |
| 529 | }; |
Nicolas Ferre | 21f8187 | 2012-02-11 15:41:40 +0100 | [diff] [blame] | 530 | }; |
| 531 | |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 532 | dbgu: serial@ffffee00 { |
| 533 | compatible = "atmel,at91sam9260-usart"; |
| 534 | reg = <0xffffee00 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 535 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 536 | pinctrl-names = "default"; |
| 537 | pinctrl-0 = <&pinctrl_dbgu>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 538 | status = "disabled"; |
| 539 | }; |
| 540 | |
| 541 | usart0: serial@fff8c000 { |
| 542 | compatible = "atmel,at91sam9260-usart"; |
| 543 | reg = <0xfff8c000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 544 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 545 | atmel,use-dma-rx; |
| 546 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 547 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 548 | pinctrl-0 = <&pinctrl_usart0>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 549 | status = "disabled"; |
| 550 | }; |
| 551 | |
| 552 | usart1: serial@fff90000 { |
| 553 | compatible = "atmel,at91sam9260-usart"; |
| 554 | reg = <0xfff90000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 555 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 556 | atmel,use-dma-rx; |
| 557 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 558 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 559 | pinctrl-0 = <&pinctrl_usart1>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 560 | status = "disabled"; |
| 561 | }; |
| 562 | |
| 563 | usart2: serial@fff94000 { |
| 564 | compatible = "atmel,at91sam9260-usart"; |
| 565 | reg = <0xfff94000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 566 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 567 | atmel,use-dma-rx; |
| 568 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 569 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 570 | pinctrl-0 = <&pinctrl_usart2>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 571 | status = "disabled"; |
| 572 | }; |
| 573 | |
| 574 | usart3: serial@fff98000 { |
| 575 | compatible = "atmel,at91sam9260-usart"; |
| 576 | reg = <0xfff98000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 577 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 578 | atmel,use-dma-rx; |
| 579 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 580 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 581 | pinctrl-0 = <&pinctrl_usart3>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 582 | status = "disabled"; |
| 583 | }; |
Nicolas Ferre | 0d4f99d | 2011-12-05 18:03:05 +0100 | [diff] [blame] | 584 | |
| 585 | macb0: ethernet@fffbc000 { |
| 586 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 587 | reg = <0xfffbc000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 588 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 589 | pinctrl-names = "default"; |
| 590 | pinctrl-0 = <&pinctrl_macb_rmii>; |
Nicolas Ferre | 0d4f99d | 2011-12-05 18:03:05 +0100 | [diff] [blame] | 591 | status = "disabled"; |
| 592 | }; |
Maxime Ripard | 93b298b | 2012-05-11 15:35:38 +0200 | [diff] [blame] | 593 | |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 594 | i2c0: i2c@fff84000 { |
| 595 | compatible = "atmel,at91sam9g10-i2c"; |
| 596 | reg = <0xfff84000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 597 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | cd127e1 | 2013-11-22 14:49:53 +0100 | [diff] [blame] | 598 | pinctrl-names = "default"; |
| 599 | pinctrl-0 = <&pinctrl_i2c0>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 600 | #address-cells = <1>; |
| 601 | #size-cells = <0>; |
| 602 | status = "disabled"; |
| 603 | }; |
| 604 | |
| 605 | i2c1: i2c@fff88000 { |
| 606 | compatible = "atmel,at91sam9g10-i2c"; |
| 607 | reg = <0xfff88000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 608 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | cd127e1 | 2013-11-22 14:49:53 +0100 | [diff] [blame] | 609 | pinctrl-names = "default"; |
| 610 | pinctrl-0 = <&pinctrl_i2c1>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 611 | #address-cells = <1>; |
| 612 | #size-cells = <0>; |
| 613 | status = "disabled"; |
| 614 | }; |
| 615 | |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 616 | ssc0: ssc@fff9c000 { |
| 617 | compatible = "atmel,at91sam9g45-ssc"; |
| 618 | reg = <0xfff9c000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 619 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 620 | pinctrl-names = "default"; |
| 621 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
Bo Shen | 315656b | 2012-12-13 10:05:07 +0800 | [diff] [blame] | 622 | status = "disabled"; |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 623 | }; |
| 624 | |
| 625 | ssc1: ssc@fffa0000 { |
| 626 | compatible = "atmel,at91sam9g45-ssc"; |
| 627 | reg = <0xfffa0000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 628 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 629 | pinctrl-names = "default"; |
| 630 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
Bo Shen | 315656b | 2012-12-13 10:05:07 +0800 | [diff] [blame] | 631 | status = "disabled"; |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 632 | }; |
| 633 | |
Maxime Ripard | 93b298b | 2012-05-11 15:35:38 +0200 | [diff] [blame] | 634 | adc0: adc@fffb0000 { |
| 635 | compatible = "atmel,at91sam9260-adc"; |
| 636 | reg = <0xfffb0000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 637 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; |
Maxime Ripard | 93b298b | 2012-05-11 15:35:38 +0200 | [diff] [blame] | 638 | atmel,adc-use-external-triggers; |
| 639 | atmel,adc-channels-used = <0xff>; |
| 640 | atmel,adc-vref = <3300>; |
| 641 | atmel,adc-num-channels = <8>; |
| 642 | atmel,adc-startup-time = <40>; |
| 643 | atmel,adc-channel-base = <0x30>; |
| 644 | atmel,adc-drdy-mask = <0x10000>; |
| 645 | atmel,adc-status-register = <0x1c>; |
| 646 | atmel,adc-trigger-register = <0x08>; |
Ludovic Desroches | 4b50da6 | 2013-03-29 10:13:19 +0100 | [diff] [blame] | 647 | atmel,adc-res = <8 10>; |
| 648 | atmel,adc-res-names = "lowres", "highres"; |
| 649 | atmel,adc-use-res = "highres"; |
Maxime Ripard | 93b298b | 2012-05-11 15:35:38 +0200 | [diff] [blame] | 650 | |
| 651 | trigger@0 { |
| 652 | trigger-name = "external-rising"; |
| 653 | trigger-value = <0x1>; |
| 654 | trigger-external; |
| 655 | }; |
| 656 | trigger@1 { |
| 657 | trigger-name = "external-falling"; |
| 658 | trigger-value = <0x2>; |
| 659 | trigger-external; |
| 660 | }; |
| 661 | |
| 662 | trigger@2 { |
| 663 | trigger-name = "external-any"; |
| 664 | trigger-value = <0x3>; |
| 665 | trigger-external; |
| 666 | }; |
| 667 | |
| 668 | trigger@3 { |
| 669 | trigger-name = "continuous"; |
| 670 | trigger-value = <0x6>; |
| 671 | }; |
| 672 | }; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 673 | |
Bo Shen | f3ab052 | 2013-12-19 11:59:17 +0800 | [diff] [blame] | 674 | pwm0: pwm@fffb8000 { |
| 675 | compatible = "atmel,at91sam9rl-pwm"; |
| 676 | reg = <0xfffb8000 0x300>; |
| 677 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; |
| 678 | #pwm-cells = <3>; |
| 679 | status = "disabled"; |
| 680 | }; |
| 681 | |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 682 | mmc0: mmc@fff80000 { |
| 683 | compatible = "atmel,hsmci"; |
| 684 | reg = <0xfff80000 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 685 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 0645b93 | 2013-11-22 14:49:52 +0100 | [diff] [blame] | 686 | pinctrl-names = "default"; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 687 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; |
Ludovic Desroches | 05c1bc9 | 2013-04-16 15:03:10 +0200 | [diff] [blame] | 688 | dma-names = "rxtx"; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 689 | #address-cells = <1>; |
| 690 | #size-cells = <0>; |
| 691 | status = "disabled"; |
| 692 | }; |
| 693 | |
| 694 | mmc1: mmc@fffd0000 { |
| 695 | compatible = "atmel,hsmci"; |
| 696 | reg = <0xfffd0000 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 697 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 0645b93 | 2013-11-22 14:49:52 +0100 | [diff] [blame] | 698 | pinctrl-names = "default"; |
Ludovic Desroches | d4ae89c | 2013-05-30 18:08:22 +0200 | [diff] [blame] | 699 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; |
Ludovic Desroches | 05c1bc9 | 2013-04-16 15:03:10 +0200 | [diff] [blame] | 700 | dma-names = "rxtx"; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 701 | #address-cells = <1>; |
| 702 | #size-cells = <0>; |
| 703 | status = "disabled"; |
| 704 | }; |
Linus Torvalds | db5b0ae | 2012-12-13 10:39:26 -0800 | [diff] [blame] | 705 | |
Fabio Porcedda | 7492e7c | 2012-11-12 09:37:26 +0100 | [diff] [blame] | 706 | watchdog@fffffd40 { |
| 707 | compatible = "atmel,at91sam9260-wdt"; |
| 708 | reg = <0xfffffd40 0x10>; |
Boris BREZILLON | fe46aa6 | 2013-10-04 09:24:14 +0200 | [diff] [blame] | 709 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 710 | atmel,watchdog-type = "hardware"; |
| 711 | atmel,reset-type = "all"; |
| 712 | atmel,dbg-halt; |
| 713 | atmel,idle-halt; |
Fabio Porcedda | 7492e7c | 2012-11-12 09:37:26 +0100 | [diff] [blame] | 714 | status = "disabled"; |
| 715 | }; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 716 | |
| 717 | spi0: spi@fffa4000 { |
| 718 | #address-cells = <1>; |
| 719 | #size-cells = <0>; |
| 720 | compatible = "atmel,at91rm9200-spi"; |
| 721 | reg = <0xfffa4000 0x200>; |
| 722 | interrupts = <14 4 3>; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 723 | pinctrl-names = "default"; |
| 724 | pinctrl-0 = <&pinctrl_spi0>; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 725 | status = "disabled"; |
| 726 | }; |
| 727 | |
| 728 | spi1: spi@fffa8000 { |
| 729 | #address-cells = <1>; |
| 730 | #size-cells = <0>; |
| 731 | compatible = "atmel,at91rm9200-spi"; |
| 732 | reg = <0xfffa8000 0x200>; |
| 733 | interrupts = <15 4 3>; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 734 | pinctrl-names = "default"; |
| 735 | pinctrl-0 = <&pinctrl_spi1>; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 736 | status = "disabled"; |
| 737 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 3cba498 | 2013-05-03 20:56:01 +0800 | [diff] [blame] | 738 | |
| 739 | usb2: gadget@fff78000 { |
| 740 | #address-cells = <1>; |
| 741 | #size-cells = <0>; |
| 742 | compatible = "atmel,at91sam9rl-udc"; |
| 743 | reg = <0x00600000 0x80000 |
| 744 | 0xfff78000 0x400>; |
| 745 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; |
| 746 | status = "disabled"; |
| 747 | |
| 748 | ep0 { |
| 749 | reg = <0>; |
| 750 | atmel,fifo-size = <64>; |
| 751 | atmel,nb-banks = <1>; |
| 752 | }; |
| 753 | |
| 754 | ep1 { |
| 755 | reg = <1>; |
| 756 | atmel,fifo-size = <1024>; |
| 757 | atmel,nb-banks = <2>; |
| 758 | atmel,can-dma; |
| 759 | atmel,can-isoc; |
| 760 | }; |
| 761 | |
| 762 | ep2 { |
| 763 | reg = <2>; |
| 764 | atmel,fifo-size = <1024>; |
| 765 | atmel,nb-banks = <2>; |
| 766 | atmel,can-dma; |
| 767 | atmel,can-isoc; |
| 768 | }; |
| 769 | |
| 770 | ep3 { |
| 771 | reg = <3>; |
| 772 | atmel,fifo-size = <1024>; |
| 773 | atmel,nb-banks = <3>; |
| 774 | atmel,can-dma; |
| 775 | }; |
| 776 | |
| 777 | ep4 { |
| 778 | reg = <4>; |
| 779 | atmel,fifo-size = <1024>; |
| 780 | atmel,nb-banks = <3>; |
| 781 | atmel,can-dma; |
| 782 | }; |
| 783 | |
| 784 | ep5 { |
| 785 | reg = <5>; |
| 786 | atmel,fifo-size = <1024>; |
| 787 | atmel,nb-banks = <3>; |
| 788 | atmel,can-dma; |
| 789 | atmel,can-isoc; |
| 790 | }; |
| 791 | |
| 792 | ep6 { |
| 793 | reg = <6>; |
| 794 | atmel,fifo-size = <1024>; |
| 795 | atmel,nb-banks = <3>; |
| 796 | atmel,can-dma; |
| 797 | atmel,can-isoc; |
| 798 | }; |
| 799 | }; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 800 | }; |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 801 | |
Jean-Christophe PLAGNIOL-VILLARD | ddee65b | 2013-03-29 02:10:47 +0800 | [diff] [blame] | 802 | fb0: fb@0x00500000 { |
| 803 | compatible = "atmel,at91sam9g45-lcdc"; |
| 804 | reg = <0x00500000 0x1000>; |
| 805 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; |
| 806 | pinctrl-names = "default"; |
| 807 | pinctrl-0 = <&pinctrl_fb>; |
| 808 | status = "disabled"; |
| 809 | }; |
| 810 | |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 811 | nand0: nand@40000000 { |
| 812 | compatible = "atmel,at91rm9200-nand"; |
| 813 | #address-cells = <1>; |
| 814 | #size-cells = <1>; |
| 815 | reg = <0x40000000 0x10000000 |
| 816 | 0xffffe200 0x200 |
| 817 | >; |
| 818 | atmel,nand-addr-offset = <21>; |
| 819 | atmel,nand-cmd-offset = <22>; |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 820 | pinctrl-names = "default"; |
| 821 | pinctrl-0 = <&pinctrl_nand>; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 822 | gpios = <&pioC 8 GPIO_ACTIVE_HIGH |
| 823 | &pioC 14 GPIO_ACTIVE_HIGH |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 824 | 0 |
| 825 | >; |
| 826 | status = "disabled"; |
| 827 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 828 | |
| 829 | usb0: ohci@00700000 { |
| 830 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 831 | reg = <0x00700000 0x100000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 832 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 833 | status = "disabled"; |
| 834 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 835 | |
| 836 | usb1: ehci@00800000 { |
| 837 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 838 | reg = <0x00800000 0x100000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 839 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 840 | status = "disabled"; |
| 841 | }; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 842 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 8f24bda | 2012-02-05 18:32:37 +0800 | [diff] [blame] | 843 | |
| 844 | i2c@0 { |
| 845 | compatible = "i2c-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 846 | gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ |
| 847 | &pioA 21 GPIO_ACTIVE_HIGH /* scl */ |
Jean-Christophe PLAGNIOL-VILLARD | 8f24bda | 2012-02-05 18:32:37 +0800 | [diff] [blame] | 848 | >; |
| 849 | i2c-gpio,sda-open-drain; |
| 850 | i2c-gpio,scl-open-drain; |
| 851 | i2c-gpio,delay-us = <5>; /* ~100 kHz */ |
| 852 | #address-cells = <1>; |
| 853 | #size-cells = <0>; |
| 854 | status = "disabled"; |
| 855 | }; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 856 | }; |