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review.evervolv.com / android_kernel_oneplus_msm8996 / 70044d71d31d6973665ced5be04ef39ac1c09a48 / . / arch / arm / boot / dts / omap3.dtsi
blob: a5fc83b9c83545ce61738abf4695ceaa47453980 [file] [log] [blame]
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard71fdc6e2013-06-11 16:49:46 +0200[diff] [blame]12#include <dt-bindings/interrupt-controller/irq.h>
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]13#include <dt-bindings/pinctrl/omap.h>
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]14
Florian Vaussard98ef79572013-05-31 14:32:55 +0200[diff] [blame]15#include "skeleton.dtsi"
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]16
17/ {
18 compatible = "ti,omap3430", "ti,omap3";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]19 interrupt-parent = <&intc>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]20
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]21 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -0500[diff] [blame]22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]28 };
29
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]30 cpus {
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]31 #address-cells = <1>;
32 #size-cells = <0>;
33
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]34 cpu@0 {
35 compatible = "arm,cortex-a8";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]36 device_type = "cpu";
37 reg = <0x0>;
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]38 };
39 };
40
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]41 pmu {
42 compatible = "arm,cortex-a8-pmu";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]43 reg = <0x54000000 0x800000>;
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]44 interrupts = <3>;
45 ti,hwmods = "debugss";
46 };
47
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]48 /*
Christoph Fritz161e89a2013-03-29 17:32:05 +0100[diff] [blame]49 * The soc node represents the soc top level view. It is used for IPs
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]50 * that are not memory mapped in the MPU view or for the MPU itself.
51 */
52 soc {
53 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]54 mpu {
55 compatible = "ti,omap3-mpu";
56 ti,hwmods = "mpu";
57 };
58
59 iva {
60 compatible = "ti,iva2.2";
61 ti,hwmods = "iva";
62
63 dsp {
64 compatible = "ti,omap3-c64";
65 };
66 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]67 };
68
69 /*
70 * XXX: Use a flat representation of the OMAP3 interconnect.
71 * The real OMAP interconnect network is quite complex.
72 * Since that will not bring real advantage to represent that in DT for
73 * the moment, just use a fake OCP bus entry to represent the whole bus
74 * hierarchy.
75 */
76 ocp {
77 compatible = "simple-bus";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]78 reg = <0x68000000 0x10000>;
79 interrupts = <9 10>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges;
83 ti,hwmods = "l3_main";
84
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]85 aes: aes@480c5000 {
86 compatible = "ti,omap3-aes";
87 ti,hwmods = "aes";
88 reg = <0x480c5000 0x50>;
89 interrupts = <0>;
90 };
91
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]92 prm: prm@48306000 {
93 compatible = "ti,omap3-prm";
94 reg = <0x48306000 0x4000>;
95
96 prm_clocks: clocks {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 };
100
101 prm_clockdomains: clockdomains {
102 };
103 };
104
105 cm: cm@48004000 {
106 compatible = "ti,omap3-cm";
107 reg = <0x48004000 0x4000>;
108
109 cm_clocks: clocks {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 };
113
114 cm_clockdomains: clockdomains {
115 };
116 };
117
118 scrm: scrm@48002000 {
119 compatible = "ti,omap3-scrm";
120 reg = <0x48002000 0x2000>;
121
122 scrm_clocks: clocks {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 };
126
127 scrm_clockdomains: clockdomains {
128 };
129 };
130
Jon Hunter510c0ff2012-10-25 14:24:14 -0500[diff] [blame]131 counter32k: counter@48320000 {
132 compatible = "ti,omap-counter32k";
133 reg = <0x48320000 0x20>;
134 ti,hwmods = "counter_32k";
135 };
136
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]137 intc: interrupt-controller@48200000 {
138 compatible = "ti,omap2-intc";
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]139 interrupt-controller;
140 #interrupt-cells = <1>;
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]141 ti,intc-size = <96>;
142 reg = <0x48200000 0x1000>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]143 };
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]144
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]145 sdma: dma-controller@48056000 {
146 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
147 reg = <0x48056000 0x1000>;
148 interrupts = <12>,
149 <13>,
150 <14>,
151 <15>;
152 #dma-cells = <1>;
153 #dma-channels = <32>;
154 #dma-requests = <96>;
155 };
156
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]157 omap3_pmx_core: pinmux@48002030 {
158 compatible = "ti,omap3-padconf", "pinctrl-single";
Laurent Pinchart3d495382014-01-07 14:01:39 -0800[diff] [blame]159 reg = <0x48002030 0x0238>;
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]160 #address-cells = <1>;
161 #size-cells = <0>;
Tony Lindgren30a69ef2013-10-10 15:45:13 -0700[diff] [blame]162 #interrupt-cells = <1>;
163 interrupt-controller;
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]164 pinctrl-single,register-width = <16>;
Tony Lindgrend623a0e2013-10-07 10:22:01 -0700[diff] [blame]165 pinctrl-single,function-mask = <0xff1f>;
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]166 };
167
Lee Jonesb7317772013-07-22 11:52:34 +0100[diff] [blame]168 omap3_pmx_wkup: pinmux@48002a00 {
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]169 compatible = "ti,omap3-padconf", "pinctrl-single";
Christoph Fritz161e89a2013-03-29 17:32:05 +0100[diff] [blame]170 reg = <0x48002a00 0x5c>;
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]171 #address-cells = <1>;
172 #size-cells = <0>;
Tony Lindgren30a69ef2013-10-10 15:45:13 -0700[diff] [blame]173 #interrupt-cells = <1>;
174 interrupt-controller;
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]175 pinctrl-single,register-width = <16>;
Tony Lindgrend623a0e2013-10-07 10:22:01 -0700[diff] [blame]176 pinctrl-single,function-mask = <0xff1f>;
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]177 };
178
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]179 gpio1: gpio@48310000 {
180 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]181 reg = <0x48310000 0x200>;
182 interrupts = <29>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]183 ti,hwmods = "gpio1";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]184 ti,gpio-always-on;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]185 gpio-controller;
186 #gpio-cells = <2>;
187 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]188 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]189 };
190
191 gpio2: gpio@49050000 {
192 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]193 reg = <0x49050000 0x200>;
194 interrupts = <30>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]195 ti,hwmods = "gpio2";
196 gpio-controller;
197 #gpio-cells = <2>;
198 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]199 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]200 };
201
202 gpio3: gpio@49052000 {
203 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]204 reg = <0x49052000 0x200>;
205 interrupts = <31>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]206 ti,hwmods = "gpio3";
207 gpio-controller;
208 #gpio-cells = <2>;
209 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]210 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]211 };
212
213 gpio4: gpio@49054000 {
214 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]215 reg = <0x49054000 0x200>;
216 interrupts = <32>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]217 ti,hwmods = "gpio4";
218 gpio-controller;
219 #gpio-cells = <2>;
220 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]221 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]222 };
223
224 gpio5: gpio@49056000 {
225 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]226 reg = <0x49056000 0x200>;
227 interrupts = <33>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]228 ti,hwmods = "gpio5";
229 gpio-controller;
230 #gpio-cells = <2>;
231 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]232 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]233 };
234
235 gpio6: gpio@49058000 {
236 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]237 reg = <0x49058000 0x200>;
238 interrupts = <34>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]239 ti,hwmods = "gpio6";
240 gpio-controller;
241 #gpio-cells = <2>;
242 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]243 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]244 };
245
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]246 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]247 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]248 reg = <0x4806a000 0x2000>;
249 interrupts = <72>;
250 dmas = <&sdma 49 &sdma 50>;
251 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]252 ti,hwmods = "uart1";
253 clock-frequency = <48000000>;
254 };
255
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]256 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]257 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]258 reg = <0x4806c000 0x400>;
259 interrupts = <73>;
260 dmas = <&sdma 51 &sdma 52>;
261 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]262 ti,hwmods = "uart2";
263 clock-frequency = <48000000>;
264 };
265
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]266 uart3: serial@49020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]267 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]268 reg = <0x49020000 0x400>;
269 interrupts = <74>;
270 dmas = <&sdma 53 &sdma 54>;
271 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]272 ti,hwmods = "uart3";
273 clock-frequency = <48000000>;
274 };
275
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]276 i2c1: i2c@48070000 {
277 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]278 reg = <0x48070000 0x80>;
279 interrupts = <56>;
280 dmas = <&sdma 27 &sdma 28>;
281 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]282 #address-cells = <1>;
283 #size-cells = <0>;
284 ti,hwmods = "i2c1";
285 };
286
287 i2c2: i2c@48072000 {
288 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]289 reg = <0x48072000 0x80>;
290 interrupts = <57>;
291 dmas = <&sdma 29 &sdma 30>;
292 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]293 #address-cells = <1>;
294 #size-cells = <0>;
295 ti,hwmods = "i2c2";
296 };
297
298 i2c3: i2c@48060000 {
299 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]300 reg = <0x48060000 0x80>;
301 interrupts = <61>;
302 dmas = <&sdma 25 &sdma 26>;
303 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]304 #address-cells = <1>;
305 #size-cells = <0>;
306 ti,hwmods = "i2c3";
307 };
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]308
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]309 mailbox: mailbox@48094000 {
310 compatible = "ti,omap3-mailbox";
311 ti,hwmods = "mailbox";
312 reg = <0x48094000 0x200>;
313 interrupts = <26>;
314 };
315
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]316 mcspi1: spi@48098000 {
317 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]318 reg = <0x48098000 0x100>;
319 interrupts = <65>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]320 #address-cells = <1>;
321 #size-cells = <0>;
322 ti,hwmods = "mcspi1";
323 ti,spi-num-cs = <4>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]324 dmas = <&sdma 35>,
325 <&sdma 36>,
326 <&sdma 37>,
327 <&sdma 38>,
328 <&sdma 39>,
329 <&sdma 40>,
330 <&sdma 41>,
331 <&sdma 42>;
332 dma-names = "tx0", "rx0", "tx1", "rx1",
333 "tx2", "rx2", "tx3", "rx3";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]334 };
335
336 mcspi2: spi@4809a000 {
337 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]338 reg = <0x4809a000 0x100>;
339 interrupts = <66>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]340 #address-cells = <1>;
341 #size-cells = <0>;
342 ti,hwmods = "mcspi2";
343 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]344 dmas = <&sdma 43>,
345 <&sdma 44>,
346 <&sdma 45>,
347 <&sdma 46>;
348 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]349 };
350
351 mcspi3: spi@480b8000 {
352 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]353 reg = <0x480b8000 0x100>;
354 interrupts = <91>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]355 #address-cells = <1>;
356 #size-cells = <0>;
357 ti,hwmods = "mcspi3";
358 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]359 dmas = <&sdma 15>,
360 <&sdma 16>,
361 <&sdma 23>,
362 <&sdma 24>;
363 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]364 };
365
366 mcspi4: spi@480ba000 {
367 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]368 reg = <0x480ba000 0x100>;
369 interrupts = <48>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]370 #address-cells = <1>;
371 #size-cells = <0>;
372 ti,hwmods = "mcspi4";
373 ti,spi-num-cs = <1>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]374 dmas = <&sdma 70>, <&sdma 71>;
375 dma-names = "tx0", "rx0";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]376 };
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]377
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]378 hdqw1w: 1w@480b2000 {
379 compatible = "ti,omap3-1w";
380 reg = <0x480b2000 0x1000>;
381 interrupts = <58>;
382 ti,hwmods = "hdq1w";
383 };
384
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]385 mmc1: mmc@4809c000 {
386 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]387 reg = <0x4809c000 0x200>;
388 interrupts = <83>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]389 ti,hwmods = "mmc1";
390 ti,dual-volt;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]391 dmas = <&sdma 61>, <&sdma 62>;
392 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]393 };
394
395 mmc2: mmc@480b4000 {
396 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]397 reg = <0x480b4000 0x200>;
398 interrupts = <86>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]399 ti,hwmods = "mmc2";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]400 dmas = <&sdma 47>, <&sdma 48>;
401 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]402 };
403
404 mmc3: mmc@480ad000 {
405 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]406 reg = <0x480ad000 0x200>;
407 interrupts = <94>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]408 ti,hwmods = "mmc3";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]409 dmas = <&sdma 77>, <&sdma 78>;
410 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]411 };
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]412
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]413 mmu_isp: mmu@480bd400 {
414 compatible = "ti,omap3-mmu-isp";
415 ti,hwmods = "mmu_isp";
416 reg = <0x480bd400 0x80>;
417 interrupts = <8>;
418 };
419
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]420 wdt2: wdt@48314000 {
421 compatible = "ti,omap3-wdt";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]422 reg = <0x48314000 0x80>;
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]423 ti,hwmods = "wd_timer2";
424 };
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]425
426 mcbsp1: mcbsp@48074000 {
427 compatible = "ti,omap3-mcbsp";
428 reg = <0x48074000 0xff>;
429 reg-names = "mpu";
430 interrupts = <16>, /* OCP compliant interrupt */
431 <59>, /* TX interrupt */
432 <60>; /* RX interrupt */
433 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]434 ti,buffer-size = <128>;
435 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]436 dmas = <&sdma 31>,
437 <&sdma 32>;
438 dma-names = "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]439 };
440
441 mcbsp2: mcbsp@49022000 {
442 compatible = "ti,omap3-mcbsp";
443 reg = <0x49022000 0xff>,
444 <0x49028000 0xff>;
445 reg-names = "mpu", "sidetone";
446 interrupts = <17>, /* OCP compliant interrupt */
447 <62>, /* TX interrupt */
448 <63>, /* RX interrupt */
449 <4>; /* Sidetone */
450 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]451 ti,buffer-size = <1280>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]452 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]453 dmas = <&sdma 33>,
454 <&sdma 34>;
455 dma-names = "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]456 };
457
458 mcbsp3: mcbsp@49024000 {
459 compatible = "ti,omap3-mcbsp";
460 reg = <0x49024000 0xff>,
461 <0x4902a000 0xff>;
462 reg-names = "mpu", "sidetone";
463 interrupts = <22>, /* OCP compliant interrupt */
464 <89>, /* TX interrupt */
465 <90>, /* RX interrupt */
466 <5>; /* Sidetone */
467 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]468 ti,buffer-size = <128>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]469 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]470 dmas = <&sdma 17>,
471 <&sdma 18>;
472 dma-names = "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]473 };
474
475 mcbsp4: mcbsp@49026000 {
476 compatible = "ti,omap3-mcbsp";
477 reg = <0x49026000 0xff>;
478 reg-names = "mpu";
479 interrupts = <23>, /* OCP compliant interrupt */
480 <54>, /* TX interrupt */
481 <55>; /* RX interrupt */
482 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]483 ti,buffer-size = <128>;
484 ti,hwmods = "mcbsp4";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]485 dmas = <&sdma 19>,
486 <&sdma 20>;
487 dma-names = "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]488 };
489
490 mcbsp5: mcbsp@48096000 {
491 compatible = "ti,omap3-mcbsp";
492 reg = <0x48096000 0xff>;
493 reg-names = "mpu";
494 interrupts = <27>, /* OCP compliant interrupt */
495 <81>, /* TX interrupt */
496 <82>; /* RX interrupt */
497 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]498 ti,buffer-size = <128>;
499 ti,hwmods = "mcbsp5";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]500 dmas = <&sdma 21>,
501 <&sdma 22>;
502 dma-names = "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]503 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]504
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]505 sham: sham@480c3000 {
506 compatible = "ti,omap3-sham";
507 ti,hwmods = "sham";
508 reg = <0x480c3000 0x64>;
509 interrupts = <49>;
510 };
511
512 smartreflex_core: smartreflex@480cb000 {
513 compatible = "ti,omap3-smartreflex-core";
514 ti,hwmods = "smartreflex_core";
515 reg = <0x480cb000 0x400>;
516 interrupts = <19>;
517 };
518
519 smartreflex_mpu_iva: smartreflex@480c9000 {
520 compatible = "ti,omap3-smartreflex-iva";
521 ti,hwmods = "smartreflex_mpu_iva";
522 reg = <0x480c9000 0x400>;
523 interrupts = <18>;
524 };
525
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]526 timer1: timer@48318000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]527 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]528 reg = <0x48318000 0x400>;
529 interrupts = <37>;
530 ti,hwmods = "timer1";
531 ti,timer-alwon;
532 };
533
534 timer2: timer@49032000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]535 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]536 reg = <0x49032000 0x400>;
537 interrupts = <38>;
538 ti,hwmods = "timer2";
539 };
540
541 timer3: timer@49034000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]542 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]543 reg = <0x49034000 0x400>;
544 interrupts = <39>;
545 ti,hwmods = "timer3";
546 };
547
548 timer4: timer@49036000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]549 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]550 reg = <0x49036000 0x400>;
551 interrupts = <40>;
552 ti,hwmods = "timer4";
553 };
554
555 timer5: timer@49038000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]556 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]557 reg = <0x49038000 0x400>;
558 interrupts = <41>;
559 ti,hwmods = "timer5";
560 ti,timer-dsp;
561 };
562
563 timer6: timer@4903a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]564 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]565 reg = <0x4903a000 0x400>;
566 interrupts = <42>;
567 ti,hwmods = "timer6";
568 ti,timer-dsp;
569 };
570
571 timer7: timer@4903c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]572 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]573 reg = <0x4903c000 0x400>;
574 interrupts = <43>;
575 ti,hwmods = "timer7";
576 ti,timer-dsp;
577 };
578
579 timer8: timer@4903e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]580 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]581 reg = <0x4903e000 0x400>;
582 interrupts = <44>;
583 ti,hwmods = "timer8";
584 ti,timer-pwm;
585 ti,timer-dsp;
586 };
587
588 timer9: timer@49040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]589 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]590 reg = <0x49040000 0x400>;
591 interrupts = <45>;
592 ti,hwmods = "timer9";
593 ti,timer-pwm;
594 };
595
596 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]597 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]598 reg = <0x48086000 0x400>;
599 interrupts = <46>;
600 ti,hwmods = "timer10";
601 ti,timer-pwm;
602 };
603
604 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]605 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]606 reg = <0x48088000 0x400>;
607 interrupts = <47>;
608 ti,hwmods = "timer11";
609 ti,timer-pwm;
610 };
611
612 timer12: timer@48304000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]613 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]614 reg = <0x48304000 0x400>;
615 interrupts = <95>;
616 ti,hwmods = "timer12";
617 ti,timer-alwon;
618 ti,timer-secure;
619 };
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]620
621 usbhstll: usbhstll@48062000 {
622 compatible = "ti,usbhs-tll";
623 reg = <0x48062000 0x1000>;
624 interrupts = <78>;
625 ti,hwmods = "usb_tll_hs";
626 };
627
628 usbhshost: usbhshost@48064000 {
629 compatible = "ti,usbhs-host";
630 reg = <0x48064000 0x400>;
631 ti,hwmods = "usb_host_hs";
632 #address-cells = <1>;
633 #size-cells = <1>;
634 ranges;
635
636 usbhsohci: ohci@48064400 {
637 compatible = "ti,ohci-omap3", "usb-ohci";
638 reg = <0x48064400 0x400>;
639 interrupt-parent = <&intc>;
640 interrupts = <76>;
641 };
642
643 usbhsehci: ehci@48064800 {
644 compatible = "ti,ehci-omap", "usb-ehci";
645 reg = <0x48064800 0x400>;
646 interrupt-parent = <&intc>;
647 interrupts = <77>;
648 };
649 };
650
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]651 gpmc: gpmc@6e000000 {
652 compatible = "ti,omap3430-gpmc";
653 ti,hwmods = "gpmc";
Javier Martinez Canillas41644e72013-02-27 02:30:51 +0100[diff] [blame]654 reg = <0x6e000000 0x02d0>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]655 interrupts = <20>;
656 gpmc,num-cs = <8>;
657 gpmc,num-waitpins = <4>;
658 #address-cells = <2>;
659 #size-cells = <1>;
660 };
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]661
662 usb_otg_hs: usb_otg_hs@480ab000 {
663 compatible = "ti,omap3-musb";
664 reg = <0x480ab000 0x1000>;
Tony Lindgren304e71e2013-05-14 20:28:15 -0700[diff] [blame]665 interrupts = <92>, <93>;
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]666 interrupt-names = "mc", "dma";
667 ti,hwmods = "usb_otg_hs";
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]668 multipoint = <1>;
669 num-eps = <16>;
670 ram-bits = <12>;
671 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]672 };
673};
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]674
675/include/ "omap3xxx-clocks.dtsi"