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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Pierre Ossman70f10482007-07-11 20:04:50 +02002 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
Russell Kingc8ebae32011-01-11 19:35:53 +00005 * Copyright (C) 2010 ST-Ericsson SA
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
16#include <linux/interrupt.h>
Russell King613b1522011-01-30 21:06:53 +000017#include <linux/kernel.h>
Lee Jones000bc9d2012-04-16 10:18:43 +010018#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/highmem.h>
Nicolas Pitre019a5f52007-10-11 01:06:03 -040022#include <linux/log2.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include <linux/mmc/host.h>
Linus Walleij34177802010-10-19 12:43:58 +010024#include <linux/mmc/card.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000025#include <linux/amba/bus.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000026#include <linux/clk.h>
Jens Axboebd6dee62007-10-24 09:01:09 +020027#include <linux/scatterlist.h>
Russell King89001442009-07-09 15:16:07 +010028#include <linux/gpio.h>
Lee Jones9a597012012-04-12 16:51:13 +010029#include <linux/of_gpio.h>
Linus Walleij34e84f32009-09-22 14:41:40 +010030#include <linux/regulator/consumer.h>
Russell Kingc8ebae32011-01-11 19:35:53 +000031#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/amba/mmci.h>
Russell King1c3be362011-08-14 09:17:05 +010034#include <linux/pm_runtime.h>
Viresh Kumar258aea72012-02-01 16:12:19 +053035#include <linux/types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Russell King7b09cda2005-07-01 12:02:59 +010037#include <asm/div64.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include <asm/io.h>
Russell Kingc6b8fda2005-10-28 14:05:16 +010039#include <asm/sizes.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040
41#include "mmci.h"
42
43#define DRIVER_NAME "mmci-pl18x"
44
Linus Torvalds1da177e2005-04-16 15:20:36 -070045static unsigned int fmax = 515633;
46
Rabin Vincent4956e102010-07-21 12:54:40 +010047/**
48 * struct variant_data - MMCI variant-specific quirks
49 * @clkreg: default value for MCICLOCK register
Rabin Vincent4380c142010-07-21 12:55:18 +010050 * @clkreg_enable: enable value for MMCICLOCK register
Rabin Vincent08458ef2010-07-21 12:55:59 +010051 * @datalength_bits: number of bits in the MMCIDATALENGTH register
Rabin Vincent8301bb62010-08-09 12:57:30 +010052 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
53 * is asserted (likewise for RX)
54 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
55 * is asserted (likewise for RX)
Linus Walleij34177802010-10-19 12:43:58 +010056 * @sdio: variant supports SDIO
Linus Walleijb70a67f2010-12-06 09:24:14 +010057 * @st_clkdiv: true if using a ST-specific clock divider algorithm
Philippe Langlais1784b152011-03-25 08:51:52 +010058 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010059 * @pwrreg_powerup: power up value for MMCIPOWER register
Ulf Hansson4d1a3a02011-12-13 16:57:07 +010060 * @signal_direction: input/out direction of bus signals can be indicated
Rabin Vincent4956e102010-07-21 12:54:40 +010061 */
62struct variant_data {
63 unsigned int clkreg;
Rabin Vincent4380c142010-07-21 12:55:18 +010064 unsigned int clkreg_enable;
Rabin Vincent08458ef2010-07-21 12:55:59 +010065 unsigned int datalength_bits;
Rabin Vincent8301bb62010-08-09 12:57:30 +010066 unsigned int fifosize;
67 unsigned int fifohalfsize;
Linus Walleij34177802010-10-19 12:43:58 +010068 bool sdio;
Linus Walleijb70a67f2010-12-06 09:24:14 +010069 bool st_clkdiv;
Philippe Langlais1784b152011-03-25 08:51:52 +010070 bool blksz_datactrl16;
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010071 u32 pwrreg_powerup;
Ulf Hansson4d1a3a02011-12-13 16:57:07 +010072 bool signal_direction;
Rabin Vincent4956e102010-07-21 12:54:40 +010073};
74
75static struct variant_data variant_arm = {
Rabin Vincent8301bb62010-08-09 12:57:30 +010076 .fifosize = 16 * 4,
77 .fifohalfsize = 8 * 4,
Rabin Vincent08458ef2010-07-21 12:55:59 +010078 .datalength_bits = 16,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010079 .pwrreg_powerup = MCI_PWR_UP,
Rabin Vincent4956e102010-07-21 12:54:40 +010080};
81
Pawel Moll768fbc12011-03-11 17:18:07 +000082static struct variant_data variant_arm_extended_fifo = {
83 .fifosize = 128 * 4,
84 .fifohalfsize = 64 * 4,
85 .datalength_bits = 16,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010086 .pwrreg_powerup = MCI_PWR_UP,
Pawel Moll768fbc12011-03-11 17:18:07 +000087};
88
Rabin Vincent4956e102010-07-21 12:54:40 +010089static struct variant_data variant_u300 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +010090 .fifosize = 16 * 4,
91 .fifohalfsize = 8 * 4,
Linus Walleij49ac2152011-03-04 14:54:16 +010092 .clkreg_enable = MCI_ST_U300_HWFCEN,
Rabin Vincent08458ef2010-07-21 12:55:59 +010093 .datalength_bits = 16,
Linus Walleij34177802010-10-19 12:43:58 +010094 .sdio = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010095 .pwrreg_powerup = MCI_PWR_ON,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +010096 .signal_direction = true,
Rabin Vincent4956e102010-07-21 12:54:40 +010097};
98
Linus Walleij34fd4212012-04-10 17:43:59 +010099static struct variant_data variant_nomadik = {
100 .fifosize = 16 * 4,
101 .fifohalfsize = 8 * 4,
102 .clkreg = MCI_CLK_ENABLE,
103 .datalength_bits = 24,
104 .sdio = true,
105 .st_clkdiv = true,
106 .pwrreg_powerup = MCI_PWR_ON,
107 .signal_direction = true,
108};
109
Rabin Vincent4956e102010-07-21 12:54:40 +0100110static struct variant_data variant_ux500 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +0100111 .fifosize = 30 * 4,
112 .fifohalfsize = 8 * 4,
Rabin Vincent4956e102010-07-21 12:54:40 +0100113 .clkreg = MCI_CLK_ENABLE,
Linus Walleij49ac2152011-03-04 14:54:16 +0100114 .clkreg_enable = MCI_ST_UX500_HWFCEN,
Rabin Vincent08458ef2010-07-21 12:55:59 +0100115 .datalength_bits = 24,
Linus Walleij34177802010-10-19 12:43:58 +0100116 .sdio = true,
Linus Walleijb70a67f2010-12-06 09:24:14 +0100117 .st_clkdiv = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100118 .pwrreg_powerup = MCI_PWR_ON,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100119 .signal_direction = true,
Rabin Vincent4956e102010-07-21 12:54:40 +0100120};
Linus Walleijb70a67f2010-12-06 09:24:14 +0100121
Philippe Langlais1784b152011-03-25 08:51:52 +0100122static struct variant_data variant_ux500v2 = {
123 .fifosize = 30 * 4,
124 .fifohalfsize = 8 * 4,
125 .clkreg = MCI_CLK_ENABLE,
126 .clkreg_enable = MCI_ST_UX500_HWFCEN,
127 .datalength_bits = 24,
128 .sdio = true,
129 .st_clkdiv = true,
130 .blksz_datactrl16 = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100131 .pwrreg_powerup = MCI_PWR_ON,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100132 .signal_direction = true,
Philippe Langlais1784b152011-03-25 08:51:52 +0100133};
134
Linus Walleija6a64642009-09-14 12:56:14 +0100135/*
136 * This must be called with host->lock held
137 */
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100138static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
139{
140 if (host->clk_reg != clk) {
141 host->clk_reg = clk;
142 writel(clk, host->base + MMCICLOCK);
143 }
144}
145
146/*
147 * This must be called with host->lock held
148 */
149static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
150{
151 if (host->pwr_reg != pwr) {
152 host->pwr_reg = pwr;
153 writel(pwr, host->base + MMCIPOWER);
154 }
155}
156
157/*
158 * This must be called with host->lock held
159 */
Linus Walleija6a64642009-09-14 12:56:14 +0100160static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
161{
Rabin Vincent4956e102010-07-21 12:54:40 +0100162 struct variant_data *variant = host->variant;
163 u32 clk = variant->clkreg;
Linus Walleija6a64642009-09-14 12:56:14 +0100164
165 if (desired) {
166 if (desired >= host->mclk) {
Linus Walleij991a86e2010-12-10 09:35:53 +0100167 clk = MCI_CLK_BYPASS;
Linus Walleij399bc482011-04-01 07:59:17 +0100168 if (variant->st_clkdiv)
169 clk |= MCI_ST_UX500_NEG_EDGE;
Linus Walleija6a64642009-09-14 12:56:14 +0100170 host->cclk = host->mclk;
Linus Walleijb70a67f2010-12-06 09:24:14 +0100171 } else if (variant->st_clkdiv) {
172 /*
173 * DB8500 TRM says f = mclk / (clkdiv + 2)
174 * => clkdiv = (mclk / f) - 2
175 * Round the divider up so we don't exceed the max
176 * frequency
177 */
178 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
179 if (clk >= 256)
180 clk = 255;
181 host->cclk = host->mclk / (clk + 2);
Linus Walleija6a64642009-09-14 12:56:14 +0100182 } else {
Linus Walleijb70a67f2010-12-06 09:24:14 +0100183 /*
184 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
185 * => clkdiv = mclk / (2 * f) - 1
186 */
Linus Walleija6a64642009-09-14 12:56:14 +0100187 clk = host->mclk / (2 * desired) - 1;
188 if (clk >= 256)
189 clk = 255;
190 host->cclk = host->mclk / (2 * (clk + 1));
191 }
Rabin Vincent4380c142010-07-21 12:55:18 +0100192
193 clk |= variant->clkreg_enable;
Linus Walleija6a64642009-09-14 12:56:14 +0100194 clk |= MCI_CLK_ENABLE;
195 /* This hasn't proven to be worthwhile */
196 /* clk |= MCI_CLK_PWRSAVE; */
197 }
198
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100199 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
Linus Walleij771dc152010-04-08 07:38:52 +0100200 clk |= MCI_4BIT_BUS;
201 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
202 clk |= MCI_ST_8BIT_BUS;
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100203
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100204 mmci_write_clkreg(host, clk);
Linus Walleija6a64642009-09-14 12:56:14 +0100205}
206
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207static void
208mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
209{
210 writel(0, host->base + MMCICOMMAND);
211
Russell Kinge47c2222007-01-08 16:42:51 +0000212 BUG_ON(host->data);
213
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 host->mrq = NULL;
215 host->cmd = NULL;
216
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 mmc_request_done(host->mmc, mrq);
Ulf Hansson2cd976c2011-12-13 17:01:11 +0100218
219 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
220 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221}
222
Linus Walleij2686b4b2010-10-19 12:39:48 +0100223static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
224{
225 void __iomem *base = host->base;
226
227 if (host->singleirq) {
228 unsigned int mask0 = readl(base + MMCIMASK0);
229
230 mask0 &= ~MCI_IRQ1MASK;
231 mask0 |= mask;
232
233 writel(mask0, base + MMCIMASK0);
234 }
235
236 writel(mask, base + MMCIMASK1);
237}
238
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239static void mmci_stop_data(struct mmci_host *host)
240{
241 writel(0, host->base + MMCIDATACTRL);
Linus Walleij2686b4b2010-10-19 12:39:48 +0100242 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243 host->data = NULL;
244}
245
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100246static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
247{
248 unsigned int flags = SG_MITER_ATOMIC;
249
250 if (data->flags & MMC_DATA_READ)
251 flags |= SG_MITER_TO_SG;
252 else
253 flags |= SG_MITER_FROM_SG;
254
255 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
256}
257
Russell Kingc8ebae32011-01-11 19:35:53 +0000258/*
259 * All the DMA operation mode stuff goes inside this ifdef.
260 * This assumes that you have a generic DMA device interface,
261 * no custom DMA interfaces are supported.
262 */
263#ifdef CONFIG_DMA_ENGINE
264static void __devinit mmci_dma_setup(struct mmci_host *host)
265{
266 struct mmci_platform_data *plat = host->plat;
267 const char *rxname, *txname;
268 dma_cap_mask_t mask;
269
270 if (!plat || !plat->dma_filter) {
271 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
272 return;
273 }
274
Per Forlin58c7ccb2011-07-01 18:55:24 +0200275 /* initialize pre request cookie */
276 host->next_data.cookie = 1;
277
Russell Kingc8ebae32011-01-11 19:35:53 +0000278 /* Try to acquire a generic DMA engine slave channel */
279 dma_cap_zero(mask);
280 dma_cap_set(DMA_SLAVE, mask);
281
282 /*
283 * If only an RX channel is specified, the driver will
284 * attempt to use it bidirectionally, however if it is
285 * is specified but cannot be located, DMA will be disabled.
286 */
287 if (plat->dma_rx_param) {
288 host->dma_rx_channel = dma_request_channel(mask,
289 plat->dma_filter,
290 plat->dma_rx_param);
291 /* E.g if no DMA hardware is present */
292 if (!host->dma_rx_channel)
293 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
294 }
295
296 if (plat->dma_tx_param) {
297 host->dma_tx_channel = dma_request_channel(mask,
298 plat->dma_filter,
299 plat->dma_tx_param);
300 if (!host->dma_tx_channel)
301 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
302 } else {
303 host->dma_tx_channel = host->dma_rx_channel;
304 }
305
306 if (host->dma_rx_channel)
307 rxname = dma_chan_name(host->dma_rx_channel);
308 else
309 rxname = "none";
310
311 if (host->dma_tx_channel)
312 txname = dma_chan_name(host->dma_tx_channel);
313 else
314 txname = "none";
315
316 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
317 rxname, txname);
318
319 /*
320 * Limit the maximum segment size in any SG entry according to
321 * the parameters of the DMA engine device.
322 */
323 if (host->dma_tx_channel) {
324 struct device *dev = host->dma_tx_channel->device->dev;
325 unsigned int max_seg_size = dma_get_max_seg_size(dev);
326
327 if (max_seg_size < host->mmc->max_seg_size)
328 host->mmc->max_seg_size = max_seg_size;
329 }
330 if (host->dma_rx_channel) {
331 struct device *dev = host->dma_rx_channel->device->dev;
332 unsigned int max_seg_size = dma_get_max_seg_size(dev);
333
334 if (max_seg_size < host->mmc->max_seg_size)
335 host->mmc->max_seg_size = max_seg_size;
336 }
337}
338
339/*
340 * This is used in __devinit or __devexit so inline it
341 * so it can be discarded.
342 */
343static inline void mmci_dma_release(struct mmci_host *host)
344{
345 struct mmci_platform_data *plat = host->plat;
346
347 if (host->dma_rx_channel)
348 dma_release_channel(host->dma_rx_channel);
349 if (host->dma_tx_channel && plat->dma_tx_param)
350 dma_release_channel(host->dma_tx_channel);
351 host->dma_rx_channel = host->dma_tx_channel = NULL;
352}
353
354static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
355{
356 struct dma_chan *chan = host->dma_current;
357 enum dma_data_direction dir;
358 u32 status;
359 int i;
360
361 /* Wait up to 1ms for the DMA to complete */
362 for (i = 0; ; i++) {
363 status = readl(host->base + MMCISTATUS);
364 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
365 break;
366 udelay(10);
367 }
368
369 /*
370 * Check to see whether we still have some data left in the FIFO -
371 * this catches DMA controllers which are unable to monitor the
372 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
373 * contiguous buffers. On TX, we'll get a FIFO underrun error.
374 */
375 if (status & MCI_RXDATAAVLBLMASK) {
376 dmaengine_terminate_all(chan);
377 if (!data->error)
378 data->error = -EIO;
379 }
380
381 if (data->flags & MMC_DATA_WRITE) {
382 dir = DMA_TO_DEVICE;
383 } else {
384 dir = DMA_FROM_DEVICE;
385 }
386
Per Forlin58c7ccb2011-07-01 18:55:24 +0200387 if (!data->host_cookie)
388 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
Russell Kingc8ebae32011-01-11 19:35:53 +0000389
390 /*
391 * Use of DMA with scatter-gather is impossible.
392 * Give up with DMA and switch back to PIO mode.
393 */
394 if (status & MCI_RXDATAAVLBLMASK) {
395 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
396 mmci_dma_release(host);
397 }
398}
399
400static void mmci_dma_data_error(struct mmci_host *host)
401{
402 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
403 dmaengine_terminate_all(host->dma_current);
404}
405
Per Forlin58c7ccb2011-07-01 18:55:24 +0200406static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
407 struct mmci_host_next *next)
Russell Kingc8ebae32011-01-11 19:35:53 +0000408{
409 struct variant_data *variant = host->variant;
410 struct dma_slave_config conf = {
411 .src_addr = host->phybase + MMCIFIFO,
412 .dst_addr = host->phybase + MMCIFIFO,
413 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
414 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
415 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
416 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
Viresh Kumar258aea72012-02-01 16:12:19 +0530417 .device_fc = false,
Russell Kingc8ebae32011-01-11 19:35:53 +0000418 };
Russell Kingc8ebae32011-01-11 19:35:53 +0000419 struct dma_chan *chan;
420 struct dma_device *device;
421 struct dma_async_tx_descriptor *desc;
Vinod Koul05f57992011-10-14 10:45:11 +0530422 enum dma_data_direction buffer_dirn;
Russell Kingc8ebae32011-01-11 19:35:53 +0000423 int nr_sg;
424
Per Forlin58c7ccb2011-07-01 18:55:24 +0200425 /* Check if next job is already prepared */
426 if (data->host_cookie && !next &&
427 host->dma_current && host->dma_desc_current)
428 return 0;
429
430 if (!next) {
431 host->dma_current = NULL;
432 host->dma_desc_current = NULL;
433 }
Russell Kingc8ebae32011-01-11 19:35:53 +0000434
435 if (data->flags & MMC_DATA_READ) {
Vinod Koul05f57992011-10-14 10:45:11 +0530436 conf.direction = DMA_DEV_TO_MEM;
437 buffer_dirn = DMA_FROM_DEVICE;
Russell Kingc8ebae32011-01-11 19:35:53 +0000438 chan = host->dma_rx_channel;
439 } else {
Vinod Koul05f57992011-10-14 10:45:11 +0530440 conf.direction = DMA_MEM_TO_DEV;
441 buffer_dirn = DMA_TO_DEVICE;
Russell Kingc8ebae32011-01-11 19:35:53 +0000442 chan = host->dma_tx_channel;
443 }
444
445 /* If there's no DMA channel, fall back to PIO */
446 if (!chan)
447 return -EINVAL;
448
449 /* If less than or equal to the fifo size, don't bother with DMA */
Per Forlin58c7ccb2011-07-01 18:55:24 +0200450 if (data->blksz * data->blocks <= variant->fifosize)
Russell Kingc8ebae32011-01-11 19:35:53 +0000451 return -EINVAL;
452
453 device = chan->device;
Vinod Koul05f57992011-10-14 10:45:11 +0530454 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
Russell Kingc8ebae32011-01-11 19:35:53 +0000455 if (nr_sg == 0)
456 return -EINVAL;
457
458 dmaengine_slave_config(chan, &conf);
Alexandre Bounine16052822012-03-08 16:11:18 -0500459 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
Russell Kingc8ebae32011-01-11 19:35:53 +0000460 conf.direction, DMA_CTRL_ACK);
461 if (!desc)
462 goto unmap_exit;
463
Per Forlin58c7ccb2011-07-01 18:55:24 +0200464 if (next) {
465 next->dma_chan = chan;
466 next->dma_desc = desc;
467 } else {
468 host->dma_current = chan;
469 host->dma_desc_current = desc;
470 }
Russell Kingc8ebae32011-01-11 19:35:53 +0000471
Per Forlin58c7ccb2011-07-01 18:55:24 +0200472 return 0;
473
474 unmap_exit:
475 if (!next)
476 dmaengine_terminate_all(chan);
Vinod Koul05f57992011-10-14 10:45:11 +0530477 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200478 return -ENOMEM;
479}
480
481static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
482{
483 int ret;
484 struct mmc_data *data = host->data;
485
486 ret = mmci_dma_prep_data(host, host->data, NULL);
487 if (ret)
488 return ret;
489
490 /* Okay, go for it. */
Russell Kingc8ebae32011-01-11 19:35:53 +0000491 dev_vdbg(mmc_dev(host->mmc),
492 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
493 data->sg_len, data->blksz, data->blocks, data->flags);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200494 dmaengine_submit(host->dma_desc_current);
495 dma_async_issue_pending(host->dma_current);
Russell Kingc8ebae32011-01-11 19:35:53 +0000496
497 datactrl |= MCI_DPSM_DMAENABLE;
498
499 /* Trigger the DMA transfer */
500 writel(datactrl, host->base + MMCIDATACTRL);
501
502 /*
503 * Let the MMCI say when the data is ended and it's time
504 * to fire next DMA request. When that happens, MMCI will
505 * call mmci_data_end()
506 */
507 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
508 host->base + MMCIMASK0);
509 return 0;
Russell Kingc8ebae32011-01-11 19:35:53 +0000510}
Per Forlin58c7ccb2011-07-01 18:55:24 +0200511
512static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
513{
514 struct mmci_host_next *next = &host->next_data;
515
516 if (data->host_cookie && data->host_cookie != next->cookie) {
Girish K Sa3c76eb2011-10-11 11:44:09 +0530517 pr_warning("[%s] invalid cookie: data->host_cookie %d"
Per Forlin58c7ccb2011-07-01 18:55:24 +0200518 " host->next_data.cookie %d\n",
519 __func__, data->host_cookie, host->next_data.cookie);
520 data->host_cookie = 0;
521 }
522
523 if (!data->host_cookie)
524 return;
525
526 host->dma_desc_current = next->dma_desc;
527 host->dma_current = next->dma_chan;
528
529 next->dma_desc = NULL;
530 next->dma_chan = NULL;
531}
532
533static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
534 bool is_first_req)
535{
536 struct mmci_host *host = mmc_priv(mmc);
537 struct mmc_data *data = mrq->data;
538 struct mmci_host_next *nd = &host->next_data;
539
540 if (!data)
541 return;
542
543 if (data->host_cookie) {
544 data->host_cookie = 0;
545 return;
546 }
547
548 /* if config for dma */
549 if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) ||
550 ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) {
551 if (mmci_dma_prep_data(host, data, nd))
552 data->host_cookie = 0;
553 else
554 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
555 }
556}
557
558static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
559 int err)
560{
561 struct mmci_host *host = mmc_priv(mmc);
562 struct mmc_data *data = mrq->data;
563 struct dma_chan *chan;
564 enum dma_data_direction dir;
565
566 if (!data)
567 return;
568
569 if (data->flags & MMC_DATA_READ) {
570 dir = DMA_FROM_DEVICE;
571 chan = host->dma_rx_channel;
572 } else {
573 dir = DMA_TO_DEVICE;
574 chan = host->dma_tx_channel;
575 }
576
577
578 /* if config for dma */
579 if (chan) {
580 if (err)
581 dmaengine_terminate_all(chan);
Per Forlin8e3336b2011-08-29 15:35:59 +0200582 if (data->host_cookie)
Per Forlin58c7ccb2011-07-01 18:55:24 +0200583 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
584 data->sg_len, dir);
585 mrq->data->host_cookie = 0;
586 }
587}
588
Russell Kingc8ebae32011-01-11 19:35:53 +0000589#else
590/* Blank functions if the DMA engine is not available */
Per Forlin58c7ccb2011-07-01 18:55:24 +0200591static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
592{
593}
Russell Kingc8ebae32011-01-11 19:35:53 +0000594static inline void mmci_dma_setup(struct mmci_host *host)
595{
596}
597
598static inline void mmci_dma_release(struct mmci_host *host)
599{
600}
601
602static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
603{
604}
605
606static inline void mmci_dma_data_error(struct mmci_host *host)
607{
608}
609
610static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
611{
612 return -ENOSYS;
613}
Per Forlin58c7ccb2011-07-01 18:55:24 +0200614
615#define mmci_pre_request NULL
616#define mmci_post_request NULL
617
Russell Kingc8ebae32011-01-11 19:35:53 +0000618#endif
619
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
621{
Rabin Vincent8301bb62010-08-09 12:57:30 +0100622 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623 unsigned int datactrl, timeout, irqmask;
Russell King7b09cda2005-07-01 12:02:59 +0100624 unsigned long long clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625 void __iomem *base;
Russell King3bc87f22006-08-27 13:51:28 +0100626 int blksz_bits;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627
Linus Walleij64de0282010-02-19 01:09:10 +0100628 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
629 data->blksz, data->blocks, data->flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630
631 host->data = data;
Rabin Vincent528320d2010-07-21 12:49:49 +0100632 host->size = data->blksz * data->blocks;
Russell King51d43752011-01-27 10:56:52 +0000633 data->bytes_xfered = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634
Russell King7b09cda2005-07-01 12:02:59 +0100635 clks = (unsigned long long)data->timeout_ns * host->cclk;
636 do_div(clks, 1000000000UL);
637
638 timeout = data->timeout_clks + (unsigned int)clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639
640 base = host->base;
641 writel(timeout, base + MMCIDATATIMER);
642 writel(host->size, base + MMCIDATALENGTH);
643
Russell King3bc87f22006-08-27 13:51:28 +0100644 blksz_bits = ffs(data->blksz) - 1;
645 BUG_ON(1 << blksz_bits != data->blksz);
646
Philippe Langlais1784b152011-03-25 08:51:52 +0100647 if (variant->blksz_datactrl16)
648 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
649 else
650 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
Russell Kingc8ebae32011-01-11 19:35:53 +0000651
652 if (data->flags & MMC_DATA_READ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 datactrl |= MCI_DPSM_DIRECTION;
Russell Kingc8ebae32011-01-11 19:35:53 +0000654
Ulf Hansson7258db72011-12-13 17:05:28 +0100655 /* The ST Micro variants has a special bit to enable SDIO */
656 if (variant->sdio && host->mmc->card)
Ulf Hansson06c1a122012-10-12 14:01:50 +0100657 if (mmc_card_sdio(host->mmc->card)) {
658 /*
659 * The ST Micro variants has a special bit
660 * to enable SDIO.
661 */
662 u32 clk;
663
Ulf Hansson7258db72011-12-13 17:05:28 +0100664 datactrl |= MCI_ST_DPSM_SDIOEN;
665
Ulf Hansson06c1a122012-10-12 14:01:50 +0100666 /*
Ulf Hansson70ac0932012-10-12 14:07:36 +0100667 * The ST Micro variant for SDIO small write transfers
668 * needs to have clock H/W flow control disabled,
669 * otherwise the transfer will not start. The threshold
670 * depends on the rate of MCLK.
Ulf Hansson06c1a122012-10-12 14:01:50 +0100671 */
Ulf Hansson70ac0932012-10-12 14:07:36 +0100672 if (data->flags & MMC_DATA_WRITE &&
673 (host->size < 8 ||
674 (host->size <= 8 && host->mclk > 50000000)))
Ulf Hansson06c1a122012-10-12 14:01:50 +0100675 clk = host->clk_reg & ~variant->clkreg_enable;
676 else
677 clk = host->clk_reg | variant->clkreg_enable;
678
679 mmci_write_clkreg(host, clk);
680 }
681
Russell Kingc8ebae32011-01-11 19:35:53 +0000682 /*
683 * Attempt to use DMA operation mode, if this
684 * should fail, fall back to PIO mode
685 */
686 if (!mmci_dma_start_data(host, datactrl))
687 return;
688
689 /* IRQ mode, map the SG list for CPU reading/writing */
690 mmci_init_sg(host, data);
691
692 if (data->flags & MMC_DATA_READ) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693 irqmask = MCI_RXFIFOHALFFULLMASK;
Russell King0425a142006-02-16 16:48:31 +0000694
695 /*
Russell Kingc4d877c2011-01-27 09:50:13 +0000696 * If we have less than the fifo 'half-full' threshold to
697 * transfer, trigger a PIO interrupt as soon as any data
698 * is available.
Russell King0425a142006-02-16 16:48:31 +0000699 */
Russell Kingc4d877c2011-01-27 09:50:13 +0000700 if (host->size < variant->fifohalfsize)
Russell King0425a142006-02-16 16:48:31 +0000701 irqmask |= MCI_RXDATAAVLBLMASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 } else {
703 /*
704 * We don't actually need to include "FIFO empty" here
705 * since its implicit in "FIFO half empty".
706 */
707 irqmask = MCI_TXFIFOHALFEMPTYMASK;
708 }
709
710 writel(datactrl, base + MMCIDATACTRL);
711 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
Linus Walleij2686b4b2010-10-19 12:39:48 +0100712 mmci_set_mask1(host, irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713}
714
715static void
716mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
717{
718 void __iomem *base = host->base;
719
Linus Walleij64de0282010-02-19 01:09:10 +0100720 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721 cmd->opcode, cmd->arg, cmd->flags);
722
723 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
724 writel(0, base + MMCICOMMAND);
725 udelay(1);
726 }
727
728 c |= cmd->opcode | MCI_CPSM_ENABLE;
Russell Kinge9225172006-02-02 12:23:12 +0000729 if (cmd->flags & MMC_RSP_PRESENT) {
730 if (cmd->flags & MMC_RSP_136)
731 c |= MCI_CPSM_LONGRSP;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732 c |= MCI_CPSM_RESPONSE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733 }
734 if (/*interrupt*/0)
735 c |= MCI_CPSM_INTERRUPT;
736
737 host->cmd = cmd;
738
739 writel(cmd->arg, base + MMCIARGUMENT);
740 writel(c, base + MMCICOMMAND);
741}
742
743static void
744mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
745 unsigned int status)
746{
Linus Walleijf20f8f22010-10-19 13:41:24 +0100747 /* First check for errors */
Ulf Hanssonb63038d2011-12-13 16:51:04 +0100748 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
749 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
Linus Walleij8cb28152011-01-24 15:22:13 +0100750 u32 remain, success;
Linus Walleijf20f8f22010-10-19 13:41:24 +0100751
Russell Kingc8ebae32011-01-11 19:35:53 +0000752 /* Terminate the DMA transfer */
753 if (dma_inprogress(host))
754 mmci_dma_data_error(host);
755
Russell Kingc8afc9d2011-02-04 09:19:46 +0000756 /*
757 * Calculate how far we are into the transfer. Note that
758 * the data counter gives the number of bytes transferred
759 * on the MMC bus, not on the host side. On reads, this
760 * can be as much as a FIFO-worth of data ahead. This
761 * matters for FIFO overruns only.
762 */
Linus Walleijf5a106d2011-01-27 17:44:34 +0100763 remain = readl(host->base + MMCIDATACNT);
Linus Walleij8cb28152011-01-24 15:22:13 +0100764 success = data->blksz * data->blocks - remain;
765
Russell Kingc8afc9d2011-02-04 09:19:46 +0000766 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
767 status, success);
Linus Walleij8cb28152011-01-24 15:22:13 +0100768 if (status & MCI_DATACRCFAIL) {
769 /* Last block was not successful */
Russell Kingc8afc9d2011-02-04 09:19:46 +0000770 success -= 1;
Pierre Ossman17b04292007-07-22 22:18:46 +0200771 data->error = -EILSEQ;
Linus Walleij8cb28152011-01-24 15:22:13 +0100772 } else if (status & MCI_DATATIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200773 data->error = -ETIMEDOUT;
Linus Walleij757df742011-06-30 15:10:21 +0100774 } else if (status & MCI_STARTBITERR) {
775 data->error = -ECOMM;
Russell Kingc8afc9d2011-02-04 09:19:46 +0000776 } else if (status & MCI_TXUNDERRUN) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200777 data->error = -EIO;
Russell Kingc8afc9d2011-02-04 09:19:46 +0000778 } else if (status & MCI_RXOVERRUN) {
779 if (success > host->variant->fifosize)
780 success -= host->variant->fifosize;
781 else
782 success = 0;
Linus Walleij8cb28152011-01-24 15:22:13 +0100783 data->error = -EIO;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100784 }
Russell King51d43752011-01-27 10:56:52 +0000785 data->bytes_xfered = round_down(success, data->blksz);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 }
Linus Walleijf20f8f22010-10-19 13:41:24 +0100787
Linus Walleij8cb28152011-01-24 15:22:13 +0100788 if (status & MCI_DATABLOCKEND)
789 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
Linus Walleijf20f8f22010-10-19 13:41:24 +0100790
Russell Kingccff9b52011-01-30 21:03:50 +0000791 if (status & MCI_DATAEND || data->error) {
Russell Kingc8ebae32011-01-11 19:35:53 +0000792 if (dma_inprogress(host))
793 mmci_dma_unmap(host, data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 mmci_stop_data(host);
795
Linus Walleij8cb28152011-01-24 15:22:13 +0100796 if (!data->error)
797 /* The error clause is handled above, success! */
Russell King51d43752011-01-27 10:56:52 +0000798 data->bytes_xfered = data->blksz * data->blocks;
Linus Walleijf20f8f22010-10-19 13:41:24 +0100799
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800 if (!data->stop) {
801 mmci_request_end(host, data->mrq);
802 } else {
803 mmci_start_command(host, data->stop, 0);
804 }
805 }
806}
807
808static void
809mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
810 unsigned int status)
811{
812 void __iomem *base = host->base;
813
814 host->cmd = NULL;
815
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816 if (status & MCI_CMDTIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200817 cmd->error = -ETIMEDOUT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200819 cmd->error = -EILSEQ;
Russell King - ARM Linux9047b432011-01-11 16:35:56 +0000820 } else {
821 cmd->resp[0] = readl(base + MMCIRESPONSE0);
822 cmd->resp[1] = readl(base + MMCIRESPONSE1);
823 cmd->resp[2] = readl(base + MMCIRESPONSE2);
824 cmd->resp[3] = readl(base + MMCIRESPONSE3);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 }
826
Pierre Ossman17b04292007-07-22 22:18:46 +0200827 if (!cmd->data || cmd->error) {
Ulf Hansson3b6e3c72011-12-13 16:58:43 +0100828 if (host->data) {
829 /* Terminate the DMA transfer */
830 if (dma_inprogress(host))
831 mmci_dma_data_error(host);
Russell Kinge47c2222007-01-08 16:42:51 +0000832 mmci_stop_data(host);
Ulf Hansson3b6e3c72011-12-13 16:58:43 +0100833 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834 mmci_request_end(host, cmd->mrq);
835 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
836 mmci_start_data(host, cmd->data);
837 }
838}
839
840static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
841{
842 void __iomem *base = host->base;
843 char *ptr = buffer;
844 u32 status;
Linus Walleij26eed9a2008-04-26 23:39:44 +0100845 int host_remain = host->size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846
847 do {
Linus Walleij26eed9a2008-04-26 23:39:44 +0100848 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849
850 if (count > remain)
851 count = remain;
852
853 if (count <= 0)
854 break;
855
Ulf Hansson393e5e22011-12-13 17:08:04 +0100856 /*
857 * SDIO especially may want to send something that is
858 * not divisible by 4 (as opposed to card sectors
859 * etc). Therefore make sure to always read the last bytes
860 * while only doing full 32-bit reads towards the FIFO.
861 */
862 if (unlikely(count & 0x3)) {
863 if (count < 4) {
864 unsigned char buf[4];
865 readsl(base + MMCIFIFO, buf, 1);
866 memcpy(ptr, buf, count);
867 } else {
868 readsl(base + MMCIFIFO, ptr, count >> 2);
869 count &= ~0x3;
870 }
871 } else {
872 readsl(base + MMCIFIFO, ptr, count >> 2);
873 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874
875 ptr += count;
876 remain -= count;
Linus Walleij26eed9a2008-04-26 23:39:44 +0100877 host_remain -= count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878
879 if (remain == 0)
880 break;
881
882 status = readl(base + MMCISTATUS);
883 } while (status & MCI_RXDATAAVLBL);
884
885 return ptr - buffer;
886}
887
888static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
889{
Rabin Vincent8301bb62010-08-09 12:57:30 +0100890 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891 void __iomem *base = host->base;
892 char *ptr = buffer;
893
894 do {
895 unsigned int count, maxcnt;
896
Rabin Vincent8301bb62010-08-09 12:57:30 +0100897 maxcnt = status & MCI_TXFIFOEMPTY ?
898 variant->fifosize : variant->fifohalfsize;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899 count = min(remain, maxcnt);
900
Linus Walleij34177802010-10-19 12:43:58 +0100901 /*
Linus Walleij34177802010-10-19 12:43:58 +0100902 * SDIO especially may want to send something that is
903 * not divisible by 4 (as opposed to card sectors
904 * etc), and the FIFO only accept full 32-bit writes.
905 * So compensate by adding +3 on the count, a single
906 * byte become a 32bit write, 7 bytes will be two
907 * 32bit writes etc.
908 */
909 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910
911 ptr += count;
912 remain -= count;
913
914 if (remain == 0)
915 break;
916
917 status = readl(base + MMCISTATUS);
918 } while (status & MCI_TXFIFOHALFEMPTY);
919
920 return ptr - buffer;
921}
922
923/*
924 * PIO data transfer IRQ handler.
925 */
David Howells7d12e782006-10-05 14:55:46 +0100926static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927{
928 struct mmci_host *host = dev_id;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100929 struct sg_mapping_iter *sg_miter = &host->sg_miter;
Rabin Vincent8301bb62010-08-09 12:57:30 +0100930 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931 void __iomem *base = host->base;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100932 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 u32 status;
934
935 status = readl(base + MMCISTATUS);
936
Linus Walleij64de0282010-02-19 01:09:10 +0100937 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100939 local_irq_save(flags);
940
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941 do {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942 unsigned int remain, len;
943 char *buffer;
944
945 /*
946 * For write, we only need to test the half-empty flag
947 * here - if the FIFO is completely empty, then by
948 * definition it is more than half empty.
949 *
950 * For read, check for data available.
951 */
952 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
953 break;
954
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100955 if (!sg_miter_next(sg_miter))
956 break;
957
958 buffer = sg_miter->addr;
959 remain = sg_miter->length;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960
961 len = 0;
962 if (status & MCI_RXACTIVE)
963 len = mmci_pio_read(host, buffer, remain);
964 if (status & MCI_TXACTIVE)
965 len = mmci_pio_write(host, buffer, remain, status);
966
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100967 sg_miter->consumed = len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969 host->size -= len;
970 remain -= len;
971
972 if (remain)
973 break;
974
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975 status = readl(base + MMCISTATUS);
976 } while (1);
977
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100978 sg_miter_stop(sg_miter);
979
980 local_irq_restore(flags);
981
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 /*
Russell Kingc4d877c2011-01-27 09:50:13 +0000983 * If we have less than the fifo 'half-full' threshold to transfer,
984 * trigger a PIO interrupt as soon as any data is available.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985 */
Russell Kingc4d877c2011-01-27 09:50:13 +0000986 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
Linus Walleij2686b4b2010-10-19 12:39:48 +0100987 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988
989 /*
990 * If we run out of data, disable the data IRQs; this
991 * prevents a race where the FIFO becomes empty before
992 * the chip itself has disabled the data path, and
993 * stops us racing with our data end IRQ.
994 */
995 if (host->size == 0) {
Linus Walleij2686b4b2010-10-19 12:39:48 +0100996 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
998 }
999
1000 return IRQ_HANDLED;
1001}
1002
1003/*
1004 * Handle completion of command and data transfers.
1005 */
David Howells7d12e782006-10-05 14:55:46 +01001006static irqreturn_t mmci_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007{
1008 struct mmci_host *host = dev_id;
1009 u32 status;
1010 int ret = 0;
1011
1012 spin_lock(&host->lock);
1013
1014 do {
1015 struct mmc_command *cmd;
1016 struct mmc_data *data;
1017
1018 status = readl(host->base + MMCISTATUS);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001019
1020 if (host->singleirq) {
1021 if (status & readl(host->base + MMCIMASK1))
1022 mmci_pio_irq(irq, dev_id);
1023
1024 status &= ~MCI_IRQ1MASK;
1025 }
1026
Linus Torvalds1da177e2005-04-16 15:20:36 -07001027 status &= readl(host->base + MMCIMASK0);
1028 writel(status, host->base + MMCICLEAR);
1029
Linus Walleij64de0282010-02-19 01:09:10 +01001030 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031
1032 data = host->data;
Ulf Hanssonb63038d2011-12-13 16:51:04 +01001033 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1034 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1035 MCI_DATABLOCKEND) && data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036 mmci_data_irq(host, data, status);
1037
1038 cmd = host->cmd;
1039 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1040 mmci_cmd_irq(host, cmd, status);
1041
1042 ret = 1;
1043 } while (status);
1044
1045 spin_unlock(&host->lock);
1046
1047 return IRQ_RETVAL(ret);
1048}
1049
1050static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1051{
1052 struct mmci_host *host = mmc_priv(mmc);
Linus Walleij9e943022008-10-24 21:17:50 +01001053 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054
1055 WARN_ON(host->mrq != NULL);
1056
Nicolas Pitre019a5f52007-10-11 01:06:03 -04001057 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
Linus Walleij64de0282010-02-19 01:09:10 +01001058 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
1059 mrq->data->blksz);
Pierre Ossman255d01a2007-07-24 20:38:53 +02001060 mrq->cmd->error = -EINVAL;
1061 mmc_request_done(mmc, mrq);
1062 return;
1063 }
1064
Russell King1c3be362011-08-14 09:17:05 +01001065 pm_runtime_get_sync(mmc_dev(mmc));
1066
Linus Walleij9e943022008-10-24 21:17:50 +01001067 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068
1069 host->mrq = mrq;
1070
Per Forlin58c7ccb2011-07-01 18:55:24 +02001071 if (mrq->data)
1072 mmci_get_next_data(host, mrq->data);
1073
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1075 mmci_start_data(host, mrq->data);
1076
1077 mmci_start_command(host, mrq->cmd, 0);
1078
Linus Walleij9e943022008-10-24 21:17:50 +01001079 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080}
1081
1082static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1083{
1084 struct mmci_host *host = mmc_priv(mmc);
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001085 struct variant_data *variant = host->variant;
Linus Walleija6a64642009-09-14 12:56:14 +01001086 u32 pwr = 0;
1087 unsigned long flags;
Linus Walleij99fc5132010-09-29 01:08:27 -04001088 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001090 pm_runtime_get_sync(mmc_dev(mmc));
1091
Ulf Hanssonbc521812011-12-13 16:57:55 +01001092 if (host->plat->ios_handler &&
1093 host->plat->ios_handler(mmc_dev(mmc), ios))
1094 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1095
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096 switch (ios->power_mode) {
1097 case MMC_POWER_OFF:
Linus Walleij99fc5132010-09-29 01:08:27 -04001098 if (host->vcc)
1099 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100 break;
1101 case MMC_POWER_UP:
Linus Walleij99fc5132010-09-29 01:08:27 -04001102 if (host->vcc) {
1103 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
1104 if (ret) {
1105 dev_err(mmc_dev(mmc), "unable to set OCR\n");
1106 /*
1107 * The .set_ios() function in the mmc_host_ops
1108 * struct return void, and failing to set the
1109 * power should be rare so we print an error
1110 * and return here.
1111 */
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001112 goto out;
Linus Walleij99fc5132010-09-29 01:08:27 -04001113 }
1114 }
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001115 /*
1116 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1117 * and instead uses MCI_PWR_ON so apply whatever value is
1118 * configured in the variant data.
1119 */
1120 pwr |= variant->pwrreg_powerup;
1121
1122 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123 case MMC_POWER_ON:
1124 pwr |= MCI_PWR_ON;
1125 break;
1126 }
1127
Ulf Hansson4d1a3a02011-12-13 16:57:07 +01001128 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1129 /*
1130 * The ST Micro variant has some additional bits
1131 * indicating signal direction for the signals in
1132 * the SD/MMC bus and feedback-clock usage.
1133 */
1134 pwr |= host->plat->sigdir;
1135
1136 if (ios->bus_width == MMC_BUS_WIDTH_4)
1137 pwr &= ~MCI_ST_DATA74DIREN;
1138 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1139 pwr &= (~MCI_ST_DATA74DIREN &
1140 ~MCI_ST_DATA31DIREN &
1141 ~MCI_ST_DATA2DIREN);
1142 }
1143
Linus Walleijcc30d602009-01-04 15:18:54 +01001144 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
Linus Walleijf17a1f02009-08-04 01:01:02 +01001145 if (host->hw_designer != AMBA_VENDOR_ST)
Linus Walleijcc30d602009-01-04 15:18:54 +01001146 pwr |= MCI_ROD;
1147 else {
1148 /*
1149 * The ST Micro variant use the ROD bit for something
1150 * else and only has OD (Open Drain).
1151 */
1152 pwr |= MCI_OD;
1153 }
1154 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001155
Linus Walleija6a64642009-09-14 12:56:14 +01001156 spin_lock_irqsave(&host->lock, flags);
1157
1158 mmci_set_clkreg(host, ios->clock);
Ulf Hansson7437cfa2012-01-18 09:17:27 +01001159 mmci_write_pwrreg(host, pwr);
Linus Walleija6a64642009-09-14 12:56:14 +01001160
1161 spin_unlock_irqrestore(&host->lock, flags);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001162
1163 out:
1164 pm_runtime_mark_last_busy(mmc_dev(mmc));
1165 pm_runtime_put_autosuspend(mmc_dev(mmc));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166}
1167
Russell King89001442009-07-09 15:16:07 +01001168static int mmci_get_ro(struct mmc_host *mmc)
1169{
1170 struct mmci_host *host = mmc_priv(mmc);
1171
1172 if (host->gpio_wp == -ENOSYS)
1173 return -ENOSYS;
1174
Linus Walleij18a063012010-09-12 12:56:44 +01001175 return gpio_get_value_cansleep(host->gpio_wp);
Russell King89001442009-07-09 15:16:07 +01001176}
1177
1178static int mmci_get_cd(struct mmc_host *mmc)
1179{
1180 struct mmci_host *host = mmc_priv(mmc);
Rabin Vincent29719442010-08-09 12:54:43 +01001181 struct mmci_platform_data *plat = host->plat;
Russell King89001442009-07-09 15:16:07 +01001182 unsigned int status;
1183
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001184 if (host->gpio_cd == -ENOSYS) {
1185 if (!plat->status)
1186 return 1; /* Assume always present */
1187
Rabin Vincent29719442010-08-09 12:54:43 +01001188 status = plat->status(mmc_dev(host->mmc));
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001189 } else
Linus Walleij18a063012010-09-12 12:56:44 +01001190 status = !!gpio_get_value_cansleep(host->gpio_cd)
1191 ^ plat->cd_invert;
Russell King89001442009-07-09 15:16:07 +01001192
Russell King74bc8092010-07-29 15:58:59 +01001193 /*
1194 * Use positive logic throughout - status is zero for no card,
1195 * non-zero for card inserted.
1196 */
1197 return status;
Russell King89001442009-07-09 15:16:07 +01001198}
1199
Rabin Vincent148b8b32010-08-09 12:55:48 +01001200static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1201{
1202 struct mmci_host *host = dev_id;
1203
1204 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1205
1206 return IRQ_HANDLED;
1207}
1208
David Brownellab7aefd2006-11-12 17:55:30 -08001209static const struct mmc_host_ops mmci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210 .request = mmci_request,
Per Forlin58c7ccb2011-07-01 18:55:24 +02001211 .pre_req = mmci_pre_request,
1212 .post_req = mmci_post_request,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213 .set_ios = mmci_set_ios,
Russell King89001442009-07-09 15:16:07 +01001214 .get_ro = mmci_get_ro,
1215 .get_cd = mmci_get_cd,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216};
1217
Lee Jones000bc9d2012-04-16 10:18:43 +01001218#ifdef CONFIG_OF
1219static void mmci_dt_populate_generic_pdata(struct device_node *np,
1220 struct mmci_platform_data *pdata)
1221{
1222 int bus_width = 0;
1223
Lee Jones9a597012012-04-12 16:51:13 +01001224 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
Lee Jones9a597012012-04-12 16:51:13 +01001225 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
Lee Jones000bc9d2012-04-16 10:18:43 +01001226
1227 if (of_get_property(np, "cd-inverted", NULL))
1228 pdata->cd_invert = true;
1229 else
1230 pdata->cd_invert = false;
1231
1232 of_property_read_u32(np, "max-frequency", &pdata->f_max);
1233 if (!pdata->f_max)
1234 pr_warn("%s has no 'max-frequency' property\n", np->full_name);
1235
1236 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1237 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1238 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1239 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;
1240
1241 of_property_read_u32(np, "bus-width", &bus_width);
1242 switch (bus_width) {
1243 case 0 :
1244 /* No bus-width supplied. */
1245 break;
1246 case 4 :
1247 pdata->capabilities |= MMC_CAP_4_BIT_DATA;
1248 break;
1249 case 8 :
1250 pdata->capabilities |= MMC_CAP_8_BIT_DATA;
1251 break;
1252 default :
1253 pr_warn("%s: Unsupported bus width\n", np->full_name);
1254 }
1255}
Lee Jonesc0a120a2012-05-08 13:59:38 +01001256#else
1257static void mmci_dt_populate_generic_pdata(struct device_node *np,
1258 struct mmci_platform_data *pdata)
1259{
1260 return;
1261}
Lee Jones000bc9d2012-04-16 10:18:43 +01001262#endif
1263
Russell Kingaa25afa2011-02-19 15:55:00 +00001264static int __devinit mmci_probe(struct amba_device *dev,
1265 const struct amba_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001266{
Linus Walleij6ef297f2009-09-22 14:29:36 +01001267 struct mmci_platform_data *plat = dev->dev.platform_data;
Lee Jones000bc9d2012-04-16 10:18:43 +01001268 struct device_node *np = dev->dev.of_node;
Rabin Vincent4956e102010-07-21 12:54:40 +01001269 struct variant_data *variant = id->data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270 struct mmci_host *host;
1271 struct mmc_host *mmc;
1272 int ret;
1273
Lee Jones000bc9d2012-04-16 10:18:43 +01001274 /* Must have platform data or Device Tree. */
1275 if (!plat && !np) {
1276 dev_err(&dev->dev, "No plat data or DT found\n");
1277 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278 }
1279
Lee Jonesb9b52912012-06-12 10:49:51 +01001280 if (!plat) {
1281 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1282 if (!plat)
1283 return -ENOMEM;
1284 }
1285
Lee Jones000bc9d2012-04-16 10:18:43 +01001286 if (np)
1287 mmci_dt_populate_generic_pdata(np, plat);
1288
Linus Torvalds1da177e2005-04-16 15:20:36 -07001289 ret = amba_request_regions(dev, DRIVER_NAME);
1290 if (ret)
1291 goto out;
1292
1293 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1294 if (!mmc) {
1295 ret = -ENOMEM;
1296 goto rel_regions;
1297 }
1298
1299 host = mmc_priv(mmc);
Rabin Vincent4ea580f2009-04-17 08:44:19 +05301300 host->mmc = mmc;
Russell King012b7d32009-07-09 15:13:56 +01001301
Russell King89001442009-07-09 15:16:07 +01001302 host->gpio_wp = -ENOSYS;
1303 host->gpio_cd = -ENOSYS;
Rabin Vincent148b8b32010-08-09 12:55:48 +01001304 host->gpio_cd_irq = -1;
Russell King89001442009-07-09 15:16:07 +01001305
Russell King012b7d32009-07-09 15:13:56 +01001306 host->hw_designer = amba_manf(dev);
1307 host->hw_revision = amba_rev(dev);
Linus Walleij64de0282010-02-19 01:09:10 +01001308 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1309 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
Russell King012b7d32009-07-09 15:13:56 +01001310
Russell Kingee569c42008-11-30 17:38:14 +00001311 host->clk = clk_get(&dev->dev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001312 if (IS_ERR(host->clk)) {
1313 ret = PTR_ERR(host->clk);
1314 host->clk = NULL;
1315 goto host_free;
1316 }
1317
Julia Lawallac940932012-08-26 16:00:59 +00001318 ret = clk_prepare_enable(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319 if (ret)
Russell Kinga8d35842006-01-03 18:41:37 +00001320 goto clk_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321
1322 host->plat = plat;
Rabin Vincent4956e102010-07-21 12:54:40 +01001323 host->variant = variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324 host->mclk = clk_get_rate(host->clk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001325 /*
1326 * According to the spec, mclk is max 100 MHz,
1327 * so we try to adjust the clock down to this,
1328 * (if possible).
1329 */
1330 if (host->mclk > 100000000) {
1331 ret = clk_set_rate(host->clk, 100000000);
1332 if (ret < 0)
1333 goto clk_disable;
1334 host->mclk = clk_get_rate(host->clk);
Linus Walleij64de0282010-02-19 01:09:10 +01001335 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1336 host->mclk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001337 }
Russell Kingc8ebae32011-01-11 19:35:53 +00001338 host->phybase = dev->res.start;
Linus Walleijdc890c22009-06-07 23:27:31 +01001339 host->base = ioremap(dev->res.start, resource_size(&dev->res));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340 if (!host->base) {
1341 ret = -ENOMEM;
1342 goto clk_disable;
1343 }
1344
1345 mmc->ops = &mmci_ops;
Linus Walleij7f294e42011-07-08 09:57:15 +01001346 /*
1347 * The ARM and ST versions of the block have slightly different
1348 * clock divider equations which means that the minimum divider
1349 * differs too.
1350 */
1351 if (variant->st_clkdiv)
1352 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1353 else
1354 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
Linus Walleij808d97c2010-04-08 07:39:38 +01001355 /*
1356 * If the platform data supplies a maximum operating
1357 * frequency, this takes precedence. Else, we fall back
1358 * to using the module parameter, which has a (low)
1359 * default value in case it is not specified. Either
1360 * value must not exceed the clock rate into the block,
1361 * of course.
1362 */
1363 if (plat->f_max)
1364 mmc->f_max = min(host->mclk, plat->f_max);
1365 else
1366 mmc->f_max = min(host->mclk, fmax);
Linus Walleij64de0282010-02-19 01:09:10 +01001367 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1368
Linus Walleij34e84f32009-09-22 14:41:40 +01001369#ifdef CONFIG_REGULATOR
1370 /* If we're using the regulator framework, try to fetch a regulator */
1371 host->vcc = regulator_get(&dev->dev, "vmmc");
1372 if (IS_ERR(host->vcc))
1373 host->vcc = NULL;
1374 else {
1375 int mask = mmc_regulator_get_ocrmask(host->vcc);
1376
1377 if (mask < 0)
1378 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
1379 mask);
1380 else {
1381 host->mmc->ocr_avail = (u32) mask;
1382 if (plat->ocr_mask)
1383 dev_warn(&dev->dev,
1384 "Provided ocr_mask/setpower will not be used "
1385 "(using regulator instead)\n");
1386 }
1387 }
1388#endif
1389 /* Fall back to platform data if no regulator is found */
1390 if (host->vcc == NULL)
1391 mmc->ocr_avail = plat->ocr_mask;
Linus Walleij9e6c82c2009-09-14 12:57:11 +01001392 mmc->caps = plat->capabilities;
Per Forlin5a092622011-11-14 12:02:28 +01001393 mmc->caps2 = plat->capabilities2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394
1395 /*
1396 * We can do SGIO
1397 */
Martin K. Petersena36274e2010-09-10 01:33:59 -04001398 mmc->max_segs = NR_SG;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399
1400 /*
Rabin Vincent08458ef2010-07-21 12:55:59 +01001401 * Since only a certain number of bits are valid in the data length
1402 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1403 * single request.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001404 */
Rabin Vincent08458ef2010-07-21 12:55:59 +01001405 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001406
1407 /*
1408 * Set the maximum segment size. Since we aren't doing DMA
1409 * (yet) we are only limited by the data length register.
1410 */
Pierre Ossman55db8902006-11-21 17:55:45 +01001411 mmc->max_seg_size = mmc->max_req_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001412
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001413 /*
1414 * Block size can be up to 2048 bytes, but must be a power of two.
1415 */
Will Deacon8f7f6b72012-02-24 11:25:21 +00001416 mmc->max_blk_size = 1 << 11;
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001417
Pierre Ossman55db8902006-11-21 17:55:45 +01001418 /*
Will Deacon8f7f6b72012-02-24 11:25:21 +00001419 * Limit the number of blocks transferred so that we don't overflow
1420 * the maximum request size.
Pierre Ossman55db8902006-11-21 17:55:45 +01001421 */
Will Deacon8f7f6b72012-02-24 11:25:21 +00001422 mmc->max_blk_count = mmc->max_req_size >> 11;
Pierre Ossman55db8902006-11-21 17:55:45 +01001423
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424 spin_lock_init(&host->lock);
1425
1426 writel(0, host->base + MMCIMASK0);
1427 writel(0, host->base + MMCIMASK1);
1428 writel(0xfff, host->base + MMCICLEAR);
1429
Roland Stigge2805b9a2012-06-17 21:14:27 +01001430 if (plat->gpio_cd == -EPROBE_DEFER) {
1431 ret = -EPROBE_DEFER;
1432 goto err_gpio_cd;
1433 }
Russell King89001442009-07-09 15:16:07 +01001434 if (gpio_is_valid(plat->gpio_cd)) {
1435 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1436 if (ret == 0)
1437 ret = gpio_direction_input(plat->gpio_cd);
1438 if (ret == 0)
1439 host->gpio_cd = plat->gpio_cd;
1440 else if (ret != -ENOSYS)
1441 goto err_gpio_cd;
Rabin Vincent148b8b32010-08-09 12:55:48 +01001442
Linus Walleij17ee0832011-05-05 17:23:10 +01001443 /*
1444 * A gpio pin that will detect cards when inserted and removed
1445 * will most likely want to trigger on the edges if it is
1446 * 0 when ejected and 1 when inserted (or mutatis mutandis
1447 * for the inverted case) so we request triggers on both
1448 * edges.
1449 */
Rabin Vincent148b8b32010-08-09 12:55:48 +01001450 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
Linus Walleij17ee0832011-05-05 17:23:10 +01001451 mmci_cd_irq,
1452 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1453 DRIVER_NAME " (cd)", host);
Rabin Vincent148b8b32010-08-09 12:55:48 +01001454 if (ret >= 0)
1455 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
Russell King89001442009-07-09 15:16:07 +01001456 }
Roland Stigge2805b9a2012-06-17 21:14:27 +01001457 if (plat->gpio_wp == -EPROBE_DEFER) {
1458 ret = -EPROBE_DEFER;
1459 goto err_gpio_wp;
1460 }
Russell King89001442009-07-09 15:16:07 +01001461 if (gpio_is_valid(plat->gpio_wp)) {
1462 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1463 if (ret == 0)
1464 ret = gpio_direction_input(plat->gpio_wp);
1465 if (ret == 0)
1466 host->gpio_wp = plat->gpio_wp;
1467 else if (ret != -ENOSYS)
1468 goto err_gpio_wp;
1469 }
1470
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001471 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1472 && host->gpio_cd_irq < 0)
Rabin Vincent148b8b32010-08-09 12:55:48 +01001473 mmc->caps |= MMC_CAP_NEEDS_POLL;
1474
Thomas Gleixnerdace1452006-07-01 19:29:38 -07001475 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476 if (ret)
1477 goto unmap;
1478
Russell Kingdfb85182012-05-03 11:33:15 +01001479 if (!dev->irq[1])
Linus Walleij2686b4b2010-10-19 12:39:48 +01001480 host->singleirq = true;
1481 else {
1482 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1483 DRIVER_NAME " (pio)", host);
1484 if (ret)
1485 goto irq0_free;
1486 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487
Linus Walleij8cb28152011-01-24 15:22:13 +01001488 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001489
1490 amba_set_drvdata(dev, mmc);
1491
Russell Kingc8ebae32011-01-11 19:35:53 +00001492 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1493 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1494 amba_rev(dev), (unsigned long long)dev->res.start,
1495 dev->irq[0], dev->irq[1]);
1496
1497 mmci_dma_setup(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001499 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1500 pm_runtime_use_autosuspend(&dev->dev);
Russell King1c3be362011-08-14 09:17:05 +01001501 pm_runtime_put(&dev->dev);
1502
Russell King8c11a942010-12-28 19:40:40 +00001503 mmc_add_host(mmc);
1504
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505 return 0;
1506
1507 irq0_free:
1508 free_irq(dev->irq[0], host);
1509 unmap:
Russell King89001442009-07-09 15:16:07 +01001510 if (host->gpio_wp != -ENOSYS)
1511 gpio_free(host->gpio_wp);
1512 err_gpio_wp:
Rabin Vincent148b8b32010-08-09 12:55:48 +01001513 if (host->gpio_cd_irq >= 0)
1514 free_irq(host->gpio_cd_irq, host);
Russell King89001442009-07-09 15:16:07 +01001515 if (host->gpio_cd != -ENOSYS)
1516 gpio_free(host->gpio_cd);
1517 err_gpio_cd:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518 iounmap(host->base);
1519 clk_disable:
Julia Lawallac940932012-08-26 16:00:59 +00001520 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521 clk_free:
1522 clk_put(host->clk);
1523 host_free:
1524 mmc_free_host(mmc);
1525 rel_regions:
1526 amba_release_regions(dev);
1527 out:
1528 return ret;
1529}
1530
Linus Walleij6dc4a472009-03-07 00:23:52 +01001531static int __devexit mmci_remove(struct amba_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532{
1533 struct mmc_host *mmc = amba_get_drvdata(dev);
1534
1535 amba_set_drvdata(dev, NULL);
1536
1537 if (mmc) {
1538 struct mmci_host *host = mmc_priv(mmc);
1539
Russell King1c3be362011-08-14 09:17:05 +01001540 /*
1541 * Undo pm_runtime_put() in probe. We use the _sync
1542 * version here so that we can access the primecell.
1543 */
1544 pm_runtime_get_sync(&dev->dev);
1545
Linus Torvalds1da177e2005-04-16 15:20:36 -07001546 mmc_remove_host(mmc);
1547
1548 writel(0, host->base + MMCIMASK0);
1549 writel(0, host->base + MMCIMASK1);
1550
1551 writel(0, host->base + MMCICOMMAND);
1552 writel(0, host->base + MMCIDATACTRL);
1553
Russell Kingc8ebae32011-01-11 19:35:53 +00001554 mmci_dma_release(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001555 free_irq(dev->irq[0], host);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001556 if (!host->singleirq)
1557 free_irq(dev->irq[1], host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001558
Russell King89001442009-07-09 15:16:07 +01001559 if (host->gpio_wp != -ENOSYS)
1560 gpio_free(host->gpio_wp);
Rabin Vincent148b8b32010-08-09 12:55:48 +01001561 if (host->gpio_cd_irq >= 0)
1562 free_irq(host->gpio_cd_irq, host);
Russell King89001442009-07-09 15:16:07 +01001563 if (host->gpio_cd != -ENOSYS)
1564 gpio_free(host->gpio_cd);
1565
Linus Torvalds1da177e2005-04-16 15:20:36 -07001566 iounmap(host->base);
Julia Lawallac940932012-08-26 16:00:59 +00001567 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568 clk_put(host->clk);
1569
Linus Walleij99fc5132010-09-29 01:08:27 -04001570 if (host->vcc)
1571 mmc_regulator_set_ocr(mmc, host->vcc, 0);
Linus Walleij34e84f32009-09-22 14:41:40 +01001572 regulator_put(host->vcc);
1573
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574 mmc_free_host(mmc);
1575
1576 amba_release_regions(dev);
1577 }
1578
1579 return 0;
1580}
1581
Ulf Hansson48fa7002011-12-13 16:59:34 +01001582#ifdef CONFIG_SUSPEND
1583static int mmci_suspend(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584{
Ulf Hansson48fa7002011-12-13 16:59:34 +01001585 struct amba_device *adev = to_amba_device(dev);
1586 struct mmc_host *mmc = amba_get_drvdata(adev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001587 int ret = 0;
1588
1589 if (mmc) {
1590 struct mmci_host *host = mmc_priv(mmc);
1591
Matt Fleming1a13f8f2010-05-26 14:42:08 -07001592 ret = mmc_suspend_host(mmc);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001593 if (ret == 0) {
1594 pm_runtime_get_sync(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001595 writel(0, host->base + MMCIMASK0);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001596 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597 }
1598
1599 return ret;
1600}
1601
Ulf Hansson48fa7002011-12-13 16:59:34 +01001602static int mmci_resume(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603{
Ulf Hansson48fa7002011-12-13 16:59:34 +01001604 struct amba_device *adev = to_amba_device(dev);
1605 struct mmc_host *mmc = amba_get_drvdata(adev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606 int ret = 0;
1607
1608 if (mmc) {
1609 struct mmci_host *host = mmc_priv(mmc);
1610
1611 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001612 pm_runtime_put(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613
1614 ret = mmc_resume_host(mmc);
1615 }
1616
1617 return ret;
1618}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001619#endif
1620
Ulf Hansson48fa7002011-12-13 16:59:34 +01001621static const struct dev_pm_ops mmci_dev_pm_ops = {
1622 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
1623};
1624
Linus Torvalds1da177e2005-04-16 15:20:36 -07001625static struct amba_id mmci_ids[] = {
1626 {
1627 .id = 0x00041180,
Pawel Moll768fbc12011-03-11 17:18:07 +00001628 .mask = 0xff0fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001629 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630 },
1631 {
Pawel Moll768fbc12011-03-11 17:18:07 +00001632 .id = 0x01041180,
1633 .mask = 0xff0fffff,
1634 .data = &variant_arm_extended_fifo,
1635 },
1636 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001637 .id = 0x00041181,
1638 .mask = 0x000fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001639 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001640 },
Linus Walleijcc30d602009-01-04 15:18:54 +01001641 /* ST Micro variants */
1642 {
1643 .id = 0x00180180,
1644 .mask = 0x00ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001645 .data = &variant_u300,
Linus Walleijcc30d602009-01-04 15:18:54 +01001646 },
1647 {
Linus Walleij34fd4212012-04-10 17:43:59 +01001648 .id = 0x10180180,
1649 .mask = 0xf0ffffff,
1650 .data = &variant_nomadik,
1651 },
1652 {
Linus Walleijcc30d602009-01-04 15:18:54 +01001653 .id = 0x00280180,
1654 .mask = 0x00ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001655 .data = &variant_u300,
1656 },
1657 {
1658 .id = 0x00480180,
Philippe Langlais1784b152011-03-25 08:51:52 +01001659 .mask = 0xf0ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001660 .data = &variant_ux500,
Linus Walleijcc30d602009-01-04 15:18:54 +01001661 },
Philippe Langlais1784b152011-03-25 08:51:52 +01001662 {
1663 .id = 0x10480180,
1664 .mask = 0xf0ffffff,
1665 .data = &variant_ux500v2,
1666 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001667 { 0, 0 },
1668};
1669
Dave Martin9f998352011-10-05 15:15:21 +01001670MODULE_DEVICE_TABLE(amba, mmci_ids);
1671
Linus Torvalds1da177e2005-04-16 15:20:36 -07001672static struct amba_driver mmci_driver = {
1673 .drv = {
1674 .name = DRIVER_NAME,
Ulf Hansson48fa7002011-12-13 16:59:34 +01001675 .pm = &mmci_dev_pm_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001676 },
1677 .probe = mmci_probe,
Linus Walleij6dc4a472009-03-07 00:23:52 +01001678 .remove = __devexit_p(mmci_remove),
Linus Torvalds1da177e2005-04-16 15:20:36 -07001679 .id_table = mmci_ids,
1680};
1681
viresh kumar9e5ed092012-03-15 10:40:38 +01001682module_amba_driver(mmci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684module_param(fmax, uint, 0444);
1685
1686MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1687MODULE_LICENSE("GPL");