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Hugh Blemings6bbc5472007-12-21 15:39:28 +11001/*
2 * Device Tree Source for IBM/AMCC Taishan
3 *
4 * Copyright 2007 IBM Corp.
5 * Hugh Blemings <hugh@au.ibm.com> based off code by
6 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without
10 * any warranty of any kind, whether express or implied.
11 */
12
David Gibson71f34972008-05-15 16:46:39 +100013/dts-v1/;
14
Hugh Blemings6bbc5472007-12-21 15:39:28 +110015/ {
16 #address-cells = <2>;
17 #size-cells = <1>;
18 model = "amcc,taishan";
19 compatible = "amcc,taishan";
David Gibson71f34972008-05-15 16:46:39 +100020 dcr-parent = <&{/cpus/cpu@0}>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +110021
Stefan Roese8aaed982007-12-15 18:55:16 +110022 aliases {
23 ethernet0 = &EMAC2;
24 ethernet1 = &EMAC3;
25 serial0 = &UART0;
26 serial1 = &UART1;
27 };
28
Hugh Blemings6bbc5472007-12-21 15:39:28 +110029 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
Josh Boyer72fda112007-12-06 13:20:05 -060033 cpu@0 {
Hugh Blemings6bbc5472007-12-21 15:39:28 +110034 device_type = "cpu";
Josh Boyer72fda112007-12-06 13:20:05 -060035 model = "PowerPC,440GX";
David Gibson71f34972008-05-15 16:46:39 +100036 reg = <0x00000000>;
37 clock-frequency = <800000000>; // 800MHz
Hugh Blemings6bbc5472007-12-21 15:39:28 +110038 timebase-frequency = <0>; // Filled in by zImage
David Gibson71f34972008-05-15 16:46:39 +100039 i-cache-line-size = <50>;
40 d-cache-line-size = <50>;
41 i-cache-size = <32768>; /* 32 kB */
42 d-cache-size = <32768>; /* 32 kB */
Hugh Blemings6bbc5472007-12-21 15:39:28 +110043 dcr-controller;
44 dcr-access-method = "native";
45 };
46 };
47
48 memory {
49 device_type = "memory";
David Gibson71f34972008-05-15 16:46:39 +100050 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
Hugh Blemings6bbc5472007-12-21 15:39:28 +110051 };
52
53
54 UICB0: interrupt-controller-base {
55 compatible = "ibm,uic-440gx", "ibm,uic";
56 interrupt-controller;
57 cell-index = <3>;
David Gibson71f34972008-05-15 16:46:39 +100058 dcr-reg = <0x200 0x009>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +110059 #address-cells = <0>;
60 #size-cells = <0>;
61 #interrupt-cells = <2>;
62 };
63
64
65 UIC0: interrupt-controller0 {
66 compatible = "ibm,uic-440gx", "ibm,uic";
67 interrupt-controller;
68 cell-index = <0>;
David Gibson71f34972008-05-15 16:46:39 +100069 dcr-reg = <0x0c0 0x009>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +110070 #address-cells = <0>;
71 #size-cells = <0>;
72 #interrupt-cells = <2>;
David Gibson71f34972008-05-15 16:46:39 +100073 interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */
Hugh Blemings6bbc5472007-12-21 15:39:28 +110074 interrupt-parent = <&UICB0>;
75
76 };
77
78 UIC1: interrupt-controller1 {
79 compatible = "ibm,uic-440gx", "ibm,uic";
80 interrupt-controller;
81 cell-index = <1>;
David Gibson71f34972008-05-15 16:46:39 +100082 dcr-reg = <0x0d0 0x009>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +110083 #address-cells = <0>;
84 #size-cells = <0>;
85 #interrupt-cells = <2>;
David Gibson71f34972008-05-15 16:46:39 +100086 interrupts = <0x3 0x4 0x2 0x4>; /* cascade */
Hugh Blemings6bbc5472007-12-21 15:39:28 +110087 interrupt-parent = <&UICB0>;
88 };
89
90 UIC2: interrupt-controller2 {
91 compatible = "ibm,uic-440gx", "ibm,uic";
92 interrupt-controller;
93 cell-index = <2>; /* was 1 */
David Gibson71f34972008-05-15 16:46:39 +100094 dcr-reg = <0x210 0x009>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +110095 #address-cells = <0>;
96 #size-cells = <0>;
97 #interrupt-cells = <2>;
David Gibson71f34972008-05-15 16:46:39 +100098 interrupts = <0x5 0x4 0x4 0x4>; /* cascade */
Hugh Blemings6bbc5472007-12-21 15:39:28 +110099 interrupt-parent = <&UICB0>;
100 };
101
102
103 CPC0: cpc {
104 compatible = "ibm,cpc-440gp";
David Gibson71f34972008-05-15 16:46:39 +1000105 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100106 // FIXME: anything else?
107 };
108
Stefan Roese99d8be02008-03-26 22:42:55 +1100109 L2C0: l2c {
110 compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
David Gibson71f34972008-05-15 16:46:39 +1000111 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
112 0x030 0x008>; /* L2 cache DCR's */
113 cache-line-size = <32>; /* 32 bytes */
114 cache-size = <262144>; /* L2, 256K */
Stefan Roese99d8be02008-03-26 22:42:55 +1100115 interrupt-parent = <&UIC2>;
David Gibson71f34972008-05-15 16:46:39 +1000116 interrupts = <0x17 0x1>;
Stefan Roese99d8be02008-03-26 22:42:55 +1100117 };
118
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100119 plb {
120 compatible = "ibm,plb-440gx", "ibm,plb4";
121 #address-cells = <2>;
122 #size-cells = <1>;
123 ranges;
David Gibson71f34972008-05-15 16:46:39 +1000124 clock-frequency = <160000000>; // 160MHz
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100125
126 SDRAM0: memory-controller {
127 compatible = "ibm,sdram-440gp";
David Gibson71f34972008-05-15 16:46:39 +1000128 dcr-reg = <0x010 0x002>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100129 // FIXME: anything else?
130 };
131
132 SRAM0: sram {
133 compatible = "ibm,sram-440gp";
David Gibson71f34972008-05-15 16:46:39 +1000134 dcr-reg = <0x020 0x008 0x00a 0x001>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100135 };
136
137 DMA0: dma {
138 // FIXME: ???
139 compatible = "ibm,dma-440gp";
David Gibson71f34972008-05-15 16:46:39 +1000140 dcr-reg = <0x100 0x027>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100141 };
142
143 MAL0: mcmal {
144 compatible = "ibm,mcmal-440gx", "ibm,mcmal2";
David Gibson71f34972008-05-15 16:46:39 +1000145 dcr-reg = <0x180 0x062>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100146 num-tx-chans = <4>;
147 num-rx-chans = <4>;
148 interrupt-parent = <&MAL0>;
David Gibson71f34972008-05-15 16:46:39 +1000149 interrupts = <0x0 0x1 0x2 0x3 0x4>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100150 #interrupt-cells = <1>;
151 #address-cells = <0>;
152 #size-cells = <0>;
David Gibson71f34972008-05-15 16:46:39 +1000153 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
154 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
155 /*SERR*/ 0x2 &UIC1 0x0 0x4
156 /*TXDE*/ 0x3 &UIC1 0x1 0x4
157 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
158 interrupt-map-mask = <0xffffffff>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100159 };
160
161 POB0: opb {
162 compatible = "ibm,opb-440gx", "ibm,opb";
163 #address-cells = <1>;
164 #size-cells = <1>;
165 /* Wish there was a nicer way of specifying a full 32-bit
166 range */
David Gibson71f34972008-05-15 16:46:39 +1000167 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
168 0x80000000 0x00000001 0x80000000 0x80000000>;
169 dcr-reg = <0x090 0x00b>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100170 interrupt-parent = <&UIC1>;
David Gibson71f34972008-05-15 16:46:39 +1000171 interrupts = <0x7 0x4>;
172 clock-frequency = <80000000>; // 80MHz
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100173
174
175 EBC0: ebc {
176 compatible = "ibm,ebc-440gx", "ibm,ebc";
David Gibson71f34972008-05-15 16:46:39 +1000177 dcr-reg = <0x012 0x002>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100178 #address-cells = <2>;
179 #size-cells = <1>;
David Gibson71f34972008-05-15 16:46:39 +1000180 clock-frequency = <80000000>; // 80MHz
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100181
182 /* ranges property is supplied by zImage
183 * based on firmware's configuration of the
184 * EBC bridge */
185
David Gibson71f34972008-05-15 16:46:39 +1000186 interrupts = <0x5 0x4>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100187 interrupt-parent = <&UIC1>;
188
189 /* TODO: Add other EBC devices */
190 };
191
192
193
194 UART0: serial@40000200 {
195 device_type = "serial";
196 compatible = "ns16550";
David Gibson71f34972008-05-15 16:46:39 +1000197 reg = <0x40000200 0x00000008>;
198 virtual-reg = <0xe0000200>;
199 clock-frequency = <11059200>;
200 current-speed = <115200>; /* 115200 */
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100201 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000202 interrupts = <0x0 0x4>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100203 };
204
205 UART1: serial@40000300 {
206 device_type = "serial";
207 compatible = "ns16550";
David Gibson71f34972008-05-15 16:46:39 +1000208 reg = <0x40000300 0x00000008>;
209 virtual-reg = <0xe0000300>;
210 clock-frequency = <11059200>;
211 current-speed = <115200>; /* 115200 */
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100212 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000213 interrupts = <0x1 0x4>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100214 };
215
216 IIC0: i2c@40000400 {
217 /* FIXME */
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100218 compatible = "ibm,iic-440gp", "ibm,iic";
David Gibson71f34972008-05-15 16:46:39 +1000219 reg = <0x40000400 0x00000014>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100220 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000221 interrupts = <0x2 0x4>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100222 };
223 IIC1: i2c@40000500 {
224 /* FIXME */
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100225 compatible = "ibm,iic-440gp", "ibm,iic";
David Gibson71f34972008-05-15 16:46:39 +1000226 reg = <0x40000500 0x00000014>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100227 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000228 interrupts = <0x3 0x4>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100229 };
230
231 GPIO0: gpio@40000700 {
232 /* FIXME */
233 compatible = "ibm,gpio-440gp";
David Gibson71f34972008-05-15 16:46:39 +1000234 reg = <0x40000700 0x00000020>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100235 };
236
237 ZMII0: emac-zmii@40000780 {
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100238 compatible = "ibm,zmii-440gx", "ibm,zmii";
David Gibson71f34972008-05-15 16:46:39 +1000239 reg = <0x40000780 0x0000000c>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100240 };
241
242 RGMII0: emac-rgmii@40000790 {
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100243 compatible = "ibm,rgmii";
David Gibson71f34972008-05-15 16:46:39 +1000244 reg = <0x40000790 0x00000008>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100245 };
246
Stefan Roese78314262008-03-14 03:00:03 +1100247 TAH0: emac-tah@40000b50 {
248 compatible = "ibm,tah-440gx", "ibm,tah";
David Gibson71f34972008-05-15 16:46:39 +1000249 reg = <0x40000b50 0x00000030>;
Stefan Roese78314262008-03-14 03:00:03 +1100250 };
251
252 TAH1: emac-tah@40000d50 {
253 compatible = "ibm,tah-440gx", "ibm,tah";
David Gibson71f34972008-05-15 16:46:39 +1000254 reg = <0x40000d50 0x00000030>;
Stefan Roese78314262008-03-14 03:00:03 +1100255 };
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100256
257 EMAC0: ethernet@40000800 {
David Gibson71f34972008-05-15 16:46:39 +1000258 unused = <0x1>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100259 device_type = "network";
260 compatible = "ibm,emac-440gx", "ibm,emac4";
261 interrupt-parent = <&UIC1>;
David Gibson71f34972008-05-15 16:46:39 +1000262 interrupts = <0x1c 0x4 0x1d 0x4>;
263 reg = <0x40000800 0x00000070>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100264 local-mac-address = [000000000000]; // Filled in by zImage
265 mal-device = <&MAL0>;
266 mal-tx-channel = <0>;
267 mal-rx-channel = <0>;
268 cell-index = <0>;
David Gibson71f34972008-05-15 16:46:39 +1000269 max-frame-size = <1500>;
270 rx-fifo-size = <4096>;
271 tx-fifo-size = <2048>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100272 phy-mode = "rmii";
David Gibson71f34972008-05-15 16:46:39 +1000273 phy-map = <0x00000001>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100274 zmii-device = <&ZMII0>;
275 zmii-channel = <0>;
276 };
277 EMAC1: ethernet@40000900 {
David Gibson71f34972008-05-15 16:46:39 +1000278 unused = <0x1>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100279 device_type = "network";
280 compatible = "ibm,emac-440gx", "ibm,emac4";
281 interrupt-parent = <&UIC1>;
David Gibson71f34972008-05-15 16:46:39 +1000282 interrupts = <0x1e 0x4 0x1f 0x4>;
283 reg = <0x40000900 0x00000070>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100284 local-mac-address = [000000000000]; // Filled in by zImage
285 mal-device = <&MAL0>;
286 mal-tx-channel = <1>;
287 mal-rx-channel = <1>;
288 cell-index = <1>;
David Gibson71f34972008-05-15 16:46:39 +1000289 max-frame-size = <1500>;
290 rx-fifo-size = <4096>;
291 tx-fifo-size = <2048>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100292 phy-mode = "rmii";
David Gibson71f34972008-05-15 16:46:39 +1000293 phy-map = <0x00000001>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100294 zmii-device = <&ZMII0>;
295 zmii-channel = <1>;
296 };
297
298 EMAC2: ethernet@40000c00 {
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100299 device_type = "network";
300 compatible = "ibm,emac-440gx", "ibm,emac4";
301 interrupt-parent = <&UIC2>;
David Gibson71f34972008-05-15 16:46:39 +1000302 interrupts = <0x0 0x4 0x1 0x4>;
303 reg = <0x40000c00 0x00000070>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100304 local-mac-address = [000000000000]; // Filled in by zImage
305 mal-device = <&MAL0>;
306 mal-tx-channel = <2>;
307 mal-rx-channel = <2>;
308 cell-index = <2>;
David Gibson71f34972008-05-15 16:46:39 +1000309 max-frame-size = <9000>;
310 rx-fifo-size = <4096>;
311 tx-fifo-size = <2048>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100312 phy-mode = "rgmii";
David Gibson71f34972008-05-15 16:46:39 +1000313 phy-map = <0x00000001>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100314 rgmii-device = <&RGMII0>;
315 rgmii-channel = <0>;
316 zmii-device = <&ZMII0>;
317 zmii-channel = <2>;
Stefan Roese78314262008-03-14 03:00:03 +1100318 tah-device = <&TAH0>;
319 tah-channel = <0>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100320 };
321
322 EMAC3: ethernet@40000e00 {
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100323 device_type = "network";
324 compatible = "ibm,emac-440gx", "ibm,emac4";
325 interrupt-parent = <&UIC2>;
David Gibson71f34972008-05-15 16:46:39 +1000326 interrupts = <0x2 0x4 0x3 0x4>;
327 reg = <0x40000e00 0x00000070>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100328 local-mac-address = [000000000000]; // Filled in by zImage
329 mal-device = <&MAL0>;
330 mal-tx-channel = <3>;
331 mal-rx-channel = <3>;
332 cell-index = <3>;
David Gibson71f34972008-05-15 16:46:39 +1000333 max-frame-size = <9000>;
334 rx-fifo-size = <4096>;
335 tx-fifo-size = <2048>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100336 phy-mode = "rgmii";
David Gibson71f34972008-05-15 16:46:39 +1000337 phy-map = <0x00000003>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100338 rgmii-device = <&RGMII0>;
339 rgmii-channel = <1>;
340 zmii-device = <&ZMII0>;
341 zmii-channel = <3>;
Stefan Roese78314262008-03-14 03:00:03 +1100342 tah-device = <&TAH1>;
343 tah-channel = <0>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100344 };
345
346
347 GPT0: gpt@40000a00 {
348 /* FIXME */
David Gibson71f34972008-05-15 16:46:39 +1000349 reg = <0x40000a00 0x000000d4>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100350 interrupt-parent = <&UIC0>;
David Gibson71f34972008-05-15 16:46:39 +1000351 interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100352 };
353
354 };
355
356 PCIX0: pci@20ec00000 {
357 device_type = "pci";
358 #interrupt-cells = <1>;
359 #size-cells = <2>;
360 #address-cells = <3>;
361 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
362 primary;
363 large-inbound-windows;
364 enable-msi-hole;
David Gibson71f34972008-05-15 16:46:39 +1000365 reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
366 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
367 0x00000002 0x0ed00000 0x00000004 /* Special cycles */
368 0x00000002 0x0ec80000 0x00000100 /* Internal registers */
369 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100370
371 /* Outbound ranges, one memory and one IO,
372 * later cannot be changed
373 */
David Gibson71f34972008-05-15 16:46:39 +1000374 ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
375 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100376
377 /* Inbound 2GB range starting at 0 */
David Gibson71f34972008-05-15 16:46:39 +1000378 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100379
David Gibson71f34972008-05-15 16:46:39 +1000380 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100381 interrupt-map = <
382 /* IDSEL 1 */
David Gibson71f34972008-05-15 16:46:39 +1000383 0x800 0x0 0x0 0x1 &UIC0 0x17 0x8
384 0x800 0x0 0x0 0x2 &UIC0 0x18 0x8
385 0x800 0x0 0x0 0x3 &UIC0 0x19 0x8
386 0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100387
388 /* IDSEL 2 */
David Gibson71f34972008-05-15 16:46:39 +1000389 0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8
390 0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8
391 0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8
392 0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8
Hugh Blemings6bbc5472007-12-21 15:39:28 +1100393 >;
394 };
395 };
396
397 chosen {
398 linux,stdout-path = "/plb/opb/serial@40000300";
399 };
400};