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review.evervolv.com / android_kernel_oneplus_msm8996 / 73368ba0e168f28ec0b3e689bd428edc92505b62 / . / arch / arm / boot / dts / tegra20.dtsi
blob: b8effa1cbda7331078d9d85bcc3d7a9bf9a891d3 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]7 host1x {
8 compatible = "nvidia,tegra20-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame^]94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0x304>;
98 };
99
Joseph Lo5ab134a2012-10-29 18:25:45 +0800[diff] [blame]100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <5 5 2>;
104 arm,tag-latency = <4 4 2>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]109 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]110 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]111 reg = <0x50041000 0x1000
112 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]113 interrupt-controller;
114 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]115 };
116
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]117 timer@60005000 {
118 compatible = "nvidia,tegra20-timer";
119 reg = <0x60005000 0x60>;
120 interrupts = <0 0 0x04
121 0 1 0x04
122 0 41 0x04
123 0 42 0x04>;
124 };
125
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]126 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]127 compatible = "nvidia,tegra20-apbdma";
128 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]129 interrupts = <0 104 0x04
130 0 105 0x04
131 0 106 0x04
132 0 107 0x04
133 0 108 0x04
134 0 109 0x04
135 0 110 0x04
136 0 111 0x04
137 0 112 0x04
138 0 113 0x04
139 0 114 0x04
140 0 115 0x04
141 0 116 0x04
142 0 117 0x04
143 0 118 0x04
144 0 119 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]145 };
146
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]147 ahb {
148 compatible = "nvidia,tegra20-ahb";
149 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]150 };
151
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]152 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]153 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]154 reg = <0x6000d000 0x1000>;
155 interrupts = <0 32 0x04
156 0 33 0x04
157 0 34 0x04
158 0 35 0x04
159 0 55 0x04
160 0 87 0x04
161 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]162 #gpio-cells = <2>;
163 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]164 #interrupt-cells = <2>;
165 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]166 };
167
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]168 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]169 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]170 reg = <0x70000014 0x10 /* Tri-state registers */
171 0x70000080 0x20 /* Mux registers */
172 0x700000a0 0x14 /* Pull-up/down registers */
173 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]174 };
175
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]176 das {
177 compatible = "nvidia,tegra20-das";
178 reg = <0x70000c00 0x80>;
179 };
180
181 tegra_i2s1: i2s@70002800 {
182 compatible = "nvidia,tegra20-i2s";
183 reg = <0x70002800 0x200>;
184 interrupts = <0 13 0x04>;
185 nvidia,dma-request-selector = <&apbdma 2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]186 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]187 };
188
189 tegra_i2s2: i2s@70002a00 {
190 compatible = "nvidia,tegra20-i2s";
191 reg = <0x70002a00 0x200>;
192 interrupts = <0 3 0x04>;
193 nvidia,dma-request-selector = <&apbdma 1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]194 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]195 };
196
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]197 serial@70006000 {
198 compatible = "nvidia,tegra20-uart";
199 reg = <0x70006000 0x40>;
200 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]201 interrupts = <0 36 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]202 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]203 };
204
205 serial@70006040 {
206 compatible = "nvidia,tegra20-uart";
207 reg = <0x70006040 0x40>;
208 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]209 interrupts = <0 37 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]210 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]211 };
212
213 serial@70006200 {
214 compatible = "nvidia,tegra20-uart";
215 reg = <0x70006200 0x100>;
216 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]217 interrupts = <0 46 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]218 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]219 };
220
221 serial@70006300 {
222 compatible = "nvidia,tegra20-uart";
223 reg = <0x70006300 0x100>;
224 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]225 interrupts = <0 90 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]226 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]227 };
228
229 serial@70006400 {
230 compatible = "nvidia,tegra20-uart";
231 reg = <0x70006400 0x100>;
232 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]233 interrupts = <0 91 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]234 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]235 };
236
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]237 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]238 compatible = "nvidia,tegra20-pwm";
239 reg = <0x7000a000 0x100>;
240 #pwm-cells = <2>;
241 };
242
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]243 rtc {
244 compatible = "nvidia,tegra20-rtc";
245 reg = <0x7000e000 0x100>;
246 interrupts = <0 2 0x04>;
247 };
248
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]249 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]250 compatible = "nvidia,tegra20-i2c";
251 reg = <0x7000c000 0x100>;
252 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]253 #address-cells = <1>;
254 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]255 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]256 };
257
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]258 spi@7000c380 {
259 compatible = "nvidia,tegra20-sflash";
260 reg = <0x7000c380 0x80>;
261 interrupts = <0 39 0x04>;
262 nvidia,dma-request-selector = <&apbdma 11>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 status = "disabled";
266 };
267
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]268 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]269 compatible = "nvidia,tegra20-i2c";
270 reg = <0x7000c400 0x100>;
271 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]272 #address-cells = <1>;
273 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]274 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]275 };
276
277 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]278 compatible = "nvidia,tegra20-i2c";
279 reg = <0x7000c500 0x100>;
280 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]281 #address-cells = <1>;
282 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]283 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]284 };
285
286 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]287 compatible = "nvidia,tegra20-i2c-dvc";
288 reg = <0x7000d000 0x200>;
289 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]290 #address-cells = <1>;
291 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]292 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]293 };
294
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]295 spi@7000d400 {
296 compatible = "nvidia,tegra20-slink";
297 reg = <0x7000d400 0x200>;
298 interrupts = <0 59 0x04>;
299 nvidia,dma-request-selector = <&apbdma 15>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 status = "disabled";
303 };
304
305 spi@7000d600 {
306 compatible = "nvidia,tegra20-slink";
307 reg = <0x7000d600 0x200>;
308 interrupts = <0 82 0x04>;
309 nvidia,dma-request-selector = <&apbdma 16>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 status = "disabled";
313 };
314
315 spi@7000d800 {
316 compatible = "nvidia,tegra20-slink";
317 reg = <0x7000d480 0x200>;
318 interrupts = <0 83 0x04>;
319 nvidia,dma-request-selector = <&apbdma 17>;
320 #address-cells = <1>;
321 #size-cells = <0>;
322 status = "disabled";
323 };
324
325 spi@7000da00 {
326 compatible = "nvidia,tegra20-slink";
327 reg = <0x7000da00 0x200>;
328 interrupts = <0 93 0x04>;
329 nvidia,dma-request-selector = <&apbdma 18>;
330 #address-cells = <1>;
331 #size-cells = <0>;
332 status = "disabled";
333 };
334
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]335 pmc {
336 compatible = "nvidia,tegra20-pmc";
337 reg = <0x7000e400 0x400>;
338 };
339
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]340 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]341 compatible = "nvidia,tegra20-mc";
342 reg = <0x7000f000 0x024
343 0x7000f03c 0x3c4>;
344 interrupts = <0 77 0x04>;
345 };
346
347 gart {
348 compatible = "nvidia,tegra20-gart";
349 reg = <0x7000f024 0x00000018 /* controller registers */
350 0x58000000 0x02000000>; /* GART aperture */
351 };
352
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]353 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]354 compatible = "nvidia,tegra20-emc";
355 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]356 #address-cells = <1>;
357 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]358 };
359
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]360 usb@c5000000 {
361 compatible = "nvidia,tegra20-ehci", "usb-ehci";
362 reg = <0xc5000000 0x4000>;
363 interrupts = <0 20 0x04>;
364 phy_type = "utmi";
365 nvidia,has-legacy-mode;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]366 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]367 };
368
369 usb@c5004000 {
370 compatible = "nvidia,tegra20-ehci", "usb-ehci";
371 reg = <0xc5004000 0x4000>;
372 interrupts = <0 21 0x04>;
373 phy_type = "ulpi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]374 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]375 };
376
377 usb@c5008000 {
378 compatible = "nvidia,tegra20-ehci", "usb-ehci";
379 reg = <0xc5008000 0x4000>;
380 interrupts = <0 97 0x04>;
381 phy_type = "utmi";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]382 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]383 };
384
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]385 sdhci@c8000000 {
386 compatible = "nvidia,tegra20-sdhci";
387 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]388 interrupts = <0 14 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]389 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]390 };
391
392 sdhci@c8000200 {
393 compatible = "nvidia,tegra20-sdhci";
394 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]395 interrupts = <0 15 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]396 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]397 };
398
399 sdhci@c8000400 {
400 compatible = "nvidia,tegra20-sdhci";
401 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]402 interrupts = <0 19 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]403 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]404 };
405
406 sdhci@c8000600 {
407 compatible = "nvidia,tegra20-sdhci";
408 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]409 interrupts = <0 31 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]410 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]411 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]412
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]413 pmu {
414 compatible = "arm,cortex-a9-pmu";
415 interrupts = <0 56 0x04
416 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]417 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]418};