Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Low-Level PCI Support for the SH7780 |
| 3 | * |
| 4 | * Dustin McIntire (dustin@sensoria.com) |
| 5 | * Derived from arch/i386/kernel/pci-*.c which bore the message: |
| 6 | * (c) 1999--2000 Martin Mares <mj@ucw.cz> |
| 7 | * |
| 8 | * Ported to the new API by Paul Mundt <lethal@linux-sh.org> |
| 9 | * With cleanup by Paul van Gool <pvangool@mimotech.com> |
| 10 | * |
| 11 | * May be copied or modified under the terms of the GNU General Public |
| 12 | * License. See linux/COPYING for more information. |
| 13 | * |
| 14 | */ |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 15 | #undef DEBUG |
| 16 | |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 17 | #include <linux/types.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/pci.h> |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 21 | #include <linux/errno.h> |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 22 | #include <linux/delay.h> |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 23 | #include "pci-sh4.h" |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * Initialization. Try all known PCI access methods. Note that we support |
| 27 | * using both PCI BIOS and direct access: in such cases, we use I/O ports |
| 28 | * to access config space. |
| 29 | * |
| 30 | * Note that the platform specific initialization (BSC registers, and memory |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 31 | * space mapping) will be called via the platform defined function |
| 32 | * pcibios_init_platform(). |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 33 | */ |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 34 | static int __init sh7780_pci_init(void) |
| 35 | { |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 36 | unsigned int id; |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 37 | int ret; |
| 38 | |
| 39 | pr_debug("PCI: Starting intialization.\n"); |
| 40 | |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 41 | outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */ |
| 42 | |
| 43 | /* check for SH7780/SH7780R hardware */ |
| 44 | id = pci_read_reg(SH7780_PCIVID); |
| 45 | if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) && |
| 46 | (id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) { |
| 47 | printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id); |
| 48 | return -ENODEV; |
| 49 | } |
| 50 | |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 51 | /* Setup the INTC */ |
| 52 | ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */ |
| 53 | ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */ |
| 54 | ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */ |
| 55 | ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */ |
| 56 | ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */ |
| 57 | ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */ |
| 58 | |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 59 | if ((ret = sh4_pci_check_direct()) != 0) |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 60 | return ret; |
| 61 | |
| 62 | return pcibios_init_platform(); |
| 63 | } |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 64 | core_initcall(sh7780_pci_init); |
| 65 | |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 66 | int __init sh7780_pcic_init(struct sh4_pci_address_map *map) |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 67 | { |
| 68 | u32 word; |
| 69 | |
| 70 | /* |
| 71 | * This code is unused for some boards as it is done in the |
| 72 | * bootloader and doing it here means the MAC addresses loaded |
| 73 | * by the bootloader get lost. |
| 74 | */ |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 75 | if (!(map->flags & SH4_PCIC_NO_RESET)) { |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 76 | /* toggle PCI reset pin */ |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 77 | word = SH4_PCICR_PREFIX | SH4_PCICR_PRST; |
| 78 | pci_write_reg(word, SH4_PCICR); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 79 | /* Wait for a long time... not 1 sec. but long enough */ |
| 80 | mdelay(100); |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 81 | word = SH4_PCICR_PREFIX; |
| 82 | pci_write_reg(word, SH4_PCICR); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | /* set the command/status bits to: |
| 86 | * Wait Cycle Control + Parity Enable + Bus Master + |
| 87 | * Mem space enable |
| 88 | */ |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 89 | pci_write_reg(0x00000046, SH7780_PCICMD); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 90 | |
| 91 | /* define this host as the host bridge */ |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 92 | word = PCI_BASE_CLASS_BRIDGE << 24; |
| 93 | pci_write_reg(word, SH7780_PCIRID); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 94 | |
| 95 | /* Set IO and Mem windows to local address |
| 96 | * Make PCI and local address the same for easy 1 to 1 mapping |
| 97 | * Window0 = map->window0.size @ non-cached area base = SDRAM |
| 98 | * Window1 = map->window1.size @ cached area base = SDRAM |
| 99 | */ |
| 100 | word = ((map->window0.size - 1) & 0x1ff00001) | 0x01; |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 101 | pci_write_reg(0x07f00001, SH4_PCILSR0); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 102 | word = ((map->window1.size - 1) & 0x1ff00001) | 0x01; |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 103 | pci_write_reg(0x00000001, SH4_PCILSR1); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 104 | /* Set the values on window 0 PCI config registers */ |
| 105 | word = P2SEGADDR(map->window0.base); |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 106 | pci_write_reg(0xa8000000, SH4_PCILAR0); |
| 107 | pci_write_reg(0x08000000, SH7780_PCIMBAR0); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 108 | /* Set the values on window 1 PCI config registers */ |
| 109 | word = P2SEGADDR(map->window1.base); |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 110 | pci_write_reg(0x00000000, SH4_PCILAR1); |
| 111 | pci_write_reg(0x00000000, SH7780_PCIMBAR1); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 112 | |
| 113 | /* Map IO space into PCI IO window |
| 114 | * The IO window is 64K-PCIBIOS_MIN_IO in size |
| 115 | * IO addresses will be translated to the |
| 116 | * PCI IO window base address |
| 117 | */ |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 118 | pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", |
| 119 | PCIBIOS_MIN_IO, (64 << 10), |
| 120 | SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 121 | |
| 122 | /* NOTE: I'm ignoring the PCI error IRQs for now.. |
| 123 | * TODO: add support for the internal error interrupts and |
| 124 | * DMA interrupts... |
| 125 | */ |
| 126 | |
| 127 | #ifdef CONFIG_SH_R7780RP |
| 128 | pci_fixup_pcic(); |
| 129 | #endif |
| 130 | |
| 131 | /* SH7780 init done, set central function init complete */ |
| 132 | /* use round robin mode to stop a device starving/overruning */ |
Paul Mundt | 959f85f | 2006-09-27 16:43:28 +0900 | [diff] [blame] | 133 | word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO; |
| 134 | pci_write_reg(word, SH4_PCICR); |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 135 | |
| 136 | return 1; |
| 137 | } |