| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| Uwe Zeisberger | f30c226 | 2006-10-03 23:01:26 +0200 | [diff] [blame] | 2 | * linux/include/asm-arm26/assembler.h |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * This file contains arm architecture specific defines |
| 5 | * for the different processors. |
| 6 | * |
| 7 | * Do not include any C declarations in this file - it is included by |
| 8 | * assembler source. |
| 9 | */ |
| 10 | #ifndef __ASSEMBLY__ |
| 11 | #error "Only include this from assembly code" |
| 12 | #endif |
| 13 | |
| 14 | /* |
| 15 | * Endian independent macros for shifting bytes within registers. |
| 16 | */ |
| 17 | #define pull lsr |
| 18 | #define push lsl |
| 19 | #define byte(x) (x*8) |
| 20 | |
| 21 | #ifdef __STDC__ |
| 22 | #define LOADREGS(cond, base, reglist...)\ |
| 23 | ldm##cond base,reglist^ |
| 24 | |
| 25 | #define RETINSTR(instr, regs...)\ |
| 26 | instr##s regs |
| 27 | #else |
| 28 | #define LOADREGS(cond, base, reglist...)\ |
| 29 | ldm/**/cond base,reglist^ |
| 30 | |
| 31 | #define RETINSTR(instr, regs...)\ |
| 32 | instr/**/s regs |
| 33 | #endif |
| 34 | |
| 35 | #define MODENOP\ |
| 36 | mov r0, r0 |
| 37 | |
| 38 | #define MODE(savereg,tmpreg,mode) \ |
| 39 | mov savereg, pc; \ |
| 40 | bic tmpreg, savereg, $0x0c000003; \ |
| 41 | orr tmpreg, tmpreg, $mode; \ |
| 42 | teqp tmpreg, $0 |
| 43 | |
| 44 | #define RESTOREMODE(savereg) \ |
| 45 | teqp savereg, $0 |
| 46 | |
| 47 | #define SAVEIRQS(tmpreg) |
| 48 | |
| 49 | #define RESTOREIRQS(tmpreg) |
| 50 | |
| 51 | #define DISABLEIRQS(tmpreg)\ |
| 52 | teqp pc, $0x08000003 |
| 53 | |
| 54 | #define ENABLEIRQS(tmpreg)\ |
| 55 | teqp pc, $0x00000003 |
| 56 | |
| 57 | #define USERMODE(tmpreg)\ |
| 58 | teqp pc, $0x00000000;\ |
| 59 | mov r0, r0 |
| 60 | |
| 61 | #define SVCMODE(tmpreg)\ |
| 62 | teqp pc, $0x00000003;\ |
| 63 | mov r0, r0 |
| 64 | |
| 65 | |
| 66 | /* |
| 67 | * Save the current IRQ state and disable IRQs |
| 68 | * Note that this macro assumes FIQs are enabled, and |
| 69 | * that the processor is in SVC mode. |
| 70 | */ |
| 71 | .macro save_and_disable_irqs, oldcpsr, temp |
| 72 | mov \oldcpsr, pc |
| 73 | orr \temp, \oldcpsr, #0x08000000 |
| 74 | teqp \temp, #0 |
| 75 | .endm |
| 76 | |
| 77 | /* |
| 78 | * Restore interrupt state previously stored in |
| 79 | * a register |
| 80 | * ** Actually do nothing on Arc - hope that the caller uses a MOVS PC soon |
| 81 | * after! |
| 82 | */ |
| 83 | .macro restore_irqs, oldcpsr |
| 84 | @ This be restore_irqs |
| 85 | .endm |
| 86 | |
| 87 | /* |
| 88 | * These two are used to save LR/restore PC over a user-based access. |
| 89 | * The old 26-bit architecture requires that we save lr (R14) |
| 90 | */ |
| 91 | .macro save_lr |
| 92 | str lr, [sp, #-4]! |
| 93 | .endm |
| 94 | |
| 95 | .macro restore_pc |
| 96 | ldmfd sp!, {pc}^ |
| 97 | .endm |
| 98 | |
| 99 | #define USER(x...) \ |
| 100 | 9999: x; \ |
| 101 | .section __ex_table,"a"; \ |
| 102 | .align 3; \ |
| 103 | .long 9999b,9001f; \ |
| 104 | .previous |
| 105 | |
| 106 | |