Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_oneplus_msm8996 / 7697daaa894ca2bc5cd652269c316bcdc3ec441b / . / arch / sparc64 / kernel / rtrap.S
blob: ecf6753b204a07d2da8b5a9c1bad0bbc35995218 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* $Id: rtrap.S,v 1.61 2002/02/09 19:49:31 davem Exp $
2 * rtrap.S: Preparing for return from trap on Sparc V9.
3 *
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 */
7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]8
9#include <asm/asi.h>
10#include <asm/pstate.h>
11#include <asm/ptrace.h>
12#include <asm/spitfire.h>
13#include <asm/head.h>
14#include <asm/visasm.h>
15#include <asm/processor.h>
16
17#define RTRAP_PSTATE (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
18#define RTRAP_PSTATE_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
19#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
20
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]21 .text
22 .align 32
23__handle_softirq:
24 call do_softirq
25 nop
26 ba,a,pt %xcc, __handle_softirq_continue
27 nop
28__handle_preemption:
29 call schedule
30 wrpr %g0, RTRAP_PSTATE, %pstate
31 ba,pt %xcc, __handle_preemption_continue
32 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
33
34__handle_user_windows:
35 call fault_in_user_windows
36 wrpr %g0, RTRAP_PSTATE, %pstate
37 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
38 /* Redo sched+sig checks */
39 ldx [%g6 + TI_FLAGS], %l0
40 andcc %l0, _TIF_NEED_RESCHED, %g0
41
42 be,pt %xcc, 1f
43 nop
44 call schedule
45 wrpr %g0, RTRAP_PSTATE, %pstate
46 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
47 ldx [%g6 + TI_FLAGS], %l0
48
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]491: andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]50 be,pt %xcc, __handle_user_windows_continue
51 nop
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]52 mov %l5, %o1
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]53 add %sp, PTREGS_OFF, %o0
David S. Miller7697daa2008-04-24 03:15:22 -0700[diff] [blame^]54 mov %l0, %o2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]55
56 call do_notify_resume
57 wrpr %g0, RTRAP_PSTATE, %pstate
58 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]59 /* Signal delivery can modify pt_regs tstate, so we must
60 * reload it.
61 */
62 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
63 sethi %hi(0xf << 20), %l4
64 and %l1, %l4, %l4
65 ba,pt %xcc, __handle_user_windows_continue
66
67 andn %l1, %l4, %l1
68__handle_perfctrs:
69 call update_perfctrs
70 wrpr %g0, RTRAP_PSTATE, %pstate
71 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
72 ldub [%g6 + TI_WSAVED], %o2
73 brz,pt %o2, 1f
74 nop
75 /* Redo userwin+sched+sig checks */
76 call fault_in_user_windows
77
78 wrpr %g0, RTRAP_PSTATE, %pstate
79 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
80 ldx [%g6 + TI_FLAGS], %l0
81 andcc %l0, _TIF_NEED_RESCHED, %g0
82 be,pt %xcc, 1f
83
84 nop
85 call schedule
86 wrpr %g0, RTRAP_PSTATE, %pstate
87 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
88 ldx [%g6 + TI_FLAGS], %l0
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]891: andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]90
91 be,pt %xcc, __handle_perfctrs_continue
92 sethi %hi(TSTATE_PEF), %o0
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]93 mov %l5, %o1
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]94 add %sp, PTREGS_OFF, %o0
David S. Miller7697daa2008-04-24 03:15:22 -0700[diff] [blame^]95 mov %l0, %o2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]96 call do_notify_resume
97
98 wrpr %g0, RTRAP_PSTATE, %pstate
99 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]100 /* Signal delivery can modify pt_regs tstate, so we must
101 * reload it.
102 */
103 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
104 sethi %hi(0xf << 20), %l4
105 and %l1, %l4, %l4
106 andn %l1, %l4, %l1
107 ba,pt %xcc, __handle_perfctrs_continue
108
109 sethi %hi(TSTATE_PEF), %o0
110__handle_userfpu:
111 rd %fprs, %l5
112 andcc %l5, FPRS_FEF, %g0
113 sethi %hi(TSTATE_PEF), %o0
114 be,a,pn %icc, __handle_userfpu_continue
115 andn %l1, %o0, %l1
116 ba,a,pt %xcc, __handle_userfpu_continue
117
118__handle_signal:
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]119 mov %l5, %o1
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]120 add %sp, PTREGS_OFF, %o0
David S. Miller7697daa2008-04-24 03:15:22 -0700[diff] [blame^]121 mov %l0, %o2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]122 call do_notify_resume
123 wrpr %g0, RTRAP_PSTATE, %pstate
124 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]125
126 /* Signal delivery can modify pt_regs tstate, so we must
127 * reload it.
128 */
129 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
130 sethi %hi(0xf << 20), %l4
131 and %l1, %l4, %l4
132 ba,pt %xcc, __handle_signal_continue
133 andn %l1, %l4, %l1
134
135 .align 64
David S. Miller7697daa2008-04-24 03:15:22 -0700[diff] [blame^]136 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]137rtrap_irq:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]138rtrap:
David S. Millerd7ce78f2005-08-29 22:46:43 -0700[diff] [blame]139#ifndef CONFIG_SMP
140 sethi %hi(per_cpu____cpu_data), %l0
141 lduw [%l0 + %lo(per_cpu____cpu_data)], %l1
142#else
143 sethi %hi(per_cpu____cpu_data), %l0
144 or %l0, %lo(per_cpu____cpu_data), %l0
145 lduw [%l0 + %g5], %l1
146#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]147 cmp %l1, 0
148
149 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
150 bne,pn %icc, __handle_softirq
151 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
152__handle_softirq_continue:
153rtrap_xcall:
154 sethi %hi(0xf << 20), %l4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]155 and %l1, %l4, %l4
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]156 andn %l1, %l4, %l1
157 srl %l4, 20, %l4
158#ifdef CONFIG_TRACE_IRQFLAGS
159 brnz,pn %l4, rtrap_no_irq_enable
160 nop
161 call trace_hardirqs_on
162 nop
163 wrpr %l4, %pil
164rtrap_no_irq_enable:
165#endif
166 andcc %l1, TSTATE_PRIV, %l3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]167 bne,pn %icc, to_kernel
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]168 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]169
170 /* We must hold IRQs off and atomically test schedule+signal
171 * state, then hold them off all the way back to userspace.
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]172 * If we are returning to kernel, none of this matters. Note
173 * that we are disabling interrupts via PSTATE_IE, not using
174 * %pil.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]175 *
176 * If we do not do this, there is a window where we would do
177 * the tests, later the signal/resched event arrives but we do
178 * not process it since we are still in kernel mode. It would
179 * take until the next local IRQ before the signal/resched
180 * event would be handled.
181 *
182 * This also means that if we have to deal with performance
183 * counters or user windows, we have to redo all of these
184 * sched+signal checks with IRQs disabled.
185 */
186to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
187 wrpr 0, %pil
188__handle_preemption_continue:
189 ldx [%g6 + TI_FLAGS], %l0
190 sethi %hi(_TIF_USER_WORK_MASK), %o0
191 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
192 andcc %l0, %o0, %g0
193 sethi %hi(TSTATE_PEF), %o0
194 be,pt %xcc, user_nowork
195 andcc %l1, %o0, %g0
196 andcc %l0, _TIF_NEED_RESCHED, %g0
197 bne,pn %xcc, __handle_preemption
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]198 andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]199 bne,pn %xcc, __handle_signal
200__handle_signal_continue:
201 ldub [%g6 + TI_WSAVED], %o2
202 brnz,pn %o2, __handle_user_windows
203 nop
204__handle_user_windows_continue:
205 ldx [%g6 + TI_FLAGS], %l5
206 andcc %l5, _TIF_PERFCTR, %g0
207 sethi %hi(TSTATE_PEF), %o0
208 bne,pn %xcc, __handle_perfctrs
209__handle_perfctrs_continue:
210 andcc %l1, %o0, %g0
211
212 /* This fpdepth clear is necessary for non-syscall rtraps only */
213user_nowork:
214 bne,pn %xcc, __handle_userfpu
215 stb %g0, [%g6 + TI_FPDEPTH]
216__handle_userfpu_continue:
217
218rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
219 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
220
221 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
222 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
223 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]224 brz,pt %l3, 1f
David S. Miller314981a2006-02-05 21:59:03 -0800[diff] [blame]225 mov %g6, %l2
226
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]227 /* Must do this before thread reg is clobbered below. */
David S. Millerffe483d2006-02-02 21:55:10 -0800[diff] [blame]228 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]2291:
230 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]231 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]232
233 /* Normal globals are restored, go to trap globals. */
234661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
David S. Milleraf02bec2006-02-16 16:23:45 -0800[diff] [blame]235 nop
236 .section .sun4v_2insn_patch, "ax"
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]237 .word 661b
David S. Milleraf02bec2006-02-16 16:23:45 -0800[diff] [blame]238 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]239 SET_GL(1)
240 .previous
241
David S. Miller314981a2006-02-05 21:59:03 -0800[diff] [blame]242 mov %l2, %g6
243
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]244 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
245 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
246
247 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
248 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
249 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
250 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
251 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
252 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
253 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
254 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
255
256 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
257 wr %o3, %g0, %y
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]258 wrpr %l4, 0x0, %pil
259 wrpr %g0, 0x1, %tl
260 wrpr %l1, %g0, %tstate
261 wrpr %l2, %g0, %tpc
262 wrpr %o2, %g0, %tnpc
263
264 brnz,pn %l3, kern_rtt
265 mov PRIMARY_CONTEXT, %l7
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]266
267661: ldxa [%l7 + %l7] ASI_DMMU, %l0
268 .section .sun4v_1insn_patch, "ax"
269 .word 661b
270 ldxa [%l7 + %l7] ASI_MMU, %l0
271 .previous
272
David S. Miller0835ae02005-10-04 15:23:20 -0700[diff] [blame]273 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
274 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]275 or %l0, %l1, %l0
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]276
277661: stxa %l0, [%l7] ASI_DMMU
278 .section .sun4v_1insn_patch, "ax"
279 .word 661b
280 stxa %l0, [%l7] ASI_MMU
281 .previous
282
David S. Miller4da808c2006-01-31 18:33:00 -0800[diff] [blame]283 sethi %hi(KERNBASE), %l7
284 flush %l7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]285 rdpr %wstate, %l1
286 rdpr %otherwin, %l2
287 srl %l1, 3, %l1
288
289 wrpr %l2, %g0, %canrestore
290 wrpr %l1, %g0, %wstate
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]291 brnz,pt %l2, user_rtt_restore
292 wrpr %g0, %g0, %otherwin
293
294 ldx [%g6 + TI_FLAGS], %g3
295 wr %g0, ASI_AIUP, %asi
296 rdpr %cwp, %g1
297 andcc %g3, _TIF_32BIT, %g0
298 sub %g1, 1, %g1
299 bne,pt %xcc, user_rtt_fill_32bit
300 wrpr %g1, %cwp
301 ba,a,pt %xcc, user_rtt_fill_64bit
302
303user_rtt_fill_fixup:
304 rdpr %cwp, %g1
305 add %g1, 1, %g1
306 wrpr %g1, 0x0, %cwp
307
308 rdpr %wstate, %g2
309 sll %g2, 3, %g2
310 wrpr %g2, 0x0, %wstate
311
312 /* We know %canrestore and %otherwin are both zero. */
313
314 sethi %hi(sparc64_kern_pri_context), %g2
315 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
316 mov PRIMARY_CONTEXT, %g1
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]317
318661: stxa %g2, [%g1] ASI_DMMU
319 .section .sun4v_1insn_patch, "ax"
320 .word 661b
321 stxa %g2, [%g1] ASI_MMU
322 .previous
323
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]324 sethi %hi(KERNBASE), %g1
325 flush %g1
326
327 or %g4, FAULT_CODE_WINFIXUP, %g4
328 stb %g4, [%g6 + TI_FAULT_CODE]
329 stx %g5, [%g6 + TI_FAULT_ADDR]
330
331 mov %g6, %l1
332 wrpr %g0, 0x0, %tl
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]333
334661: nop
David S. Millerdf7d6ae2006-02-07 00:00:16 -0800[diff] [blame]335 .section .sun4v_1insn_patch, "ax"
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]336 .word 661b
337 SET_GL(0)
338 .previous
339
David S. Millerfc504922006-02-22 16:15:45 -0800[diff] [blame]340 wrpr %g0, RTRAP_PSTATE, %pstate
341
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]342 mov %l1, %g6
343 ldx [%g6 + TI_TASK], %g4
344 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
345 call do_sparc64_fault
346 add %sp, PTREGS_OFF, %o0
347 ba,pt %xcc, rtrap
348 nop
349
350user_rtt_pre_restore:
351 add %g1, 1, %g1
352 wrpr %g1, 0x0, %cwp
353
354user_rtt_restore:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]355 restore
356 rdpr %canrestore, %g1
357 wrpr %g1, 0x0, %cleanwin
358 retry
359 nop
360
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]361kern_rtt: rdpr %canrestore, %g1
362 brz,pn %g1, kern_rtt_fill
363 nop
364kern_rtt_restore:
365 restore
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]366 retry
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]367
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]368to_kernel:
369#ifdef CONFIG_PREEMPT
370 ldsw [%g6 + TI_PRE_COUNT], %l5
371 brnz %l5, kern_fpucheck
372 ldx [%g6 + TI_FLAGS], %l5
373 andcc %l5, _TIF_NEED_RESCHED, %g0
374 be,pt %xcc, kern_fpucheck
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]375 nop
376 cmp %l4, 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]377 bne,pn %xcc, kern_fpucheck
378 sethi %hi(PREEMPT_ACTIVE), %l6
379 stw %l6, [%g6 + TI_PRE_COUNT]
380 call schedule
381 nop
382 ba,pt %xcc, rtrap
383 stw %g0, [%g6 + TI_PRE_COUNT]
384#endif
385kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
386 brz,pt %l5, rt_continue
387 srl %l5, 1, %o0
388 add %g6, TI_FPSAVED, %l6
389 ldub [%l6 + %o0], %l2
390 sub %l5, 2, %l5
391
392 add %g6, TI_GSR, %o1
393 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
394 be,pt %icc, 2f
395 and %l2, FPRS_DL, %l6
396 andcc %l2, FPRS_FEF, %g0
397 be,pn %icc, 5f
398 sll %o0, 3, %o5
399 rd %fprs, %g1
400
401 wr %g1, FPRS_FEF, %fprs
402 ldx [%o1 + %o5], %g1
403 add %g6, TI_XFSR, %o1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]404 sll %o0, 8, %o2
405 add %g6, TI_FPREGS, %o3
406 brz,pn %l6, 1f
407 add %g6, TI_FPREGS+0x40, %o4
408
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]409 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]410 ldda [%o3 + %o2] ASI_BLK_P, %f0
411 ldda [%o4 + %o2] ASI_BLK_P, %f16
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]412 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4131: andcc %l2, FPRS_DU, %g0
414 be,pn %icc, 1f
415 wr %g1, 0, %gsr
416 add %o2, 0x80, %o2
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]417 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]418 ldda [%o3 + %o2] ASI_BLK_P, %f32
419 ldda [%o4 + %o2] ASI_BLK_P, %f48
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4201: membar #Sync
421 ldx [%o1 + %o5], %fsr
4222: stb %l5, [%g6 + TI_FPDEPTH]
423 ba,pt %xcc, rt_continue
424 nop
4255: wr %g0, FPRS_FEF, %fprs
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]426 sll %o0, 8, %o2
427
428 add %g6, TI_FPREGS+0x80, %o3
429 add %g6, TI_FPREGS+0xc0, %o4
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]430 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]431 ldda [%o3 + %o2] ASI_BLK_P, %f32
432 ldda [%o4 + %o2] ASI_BLK_P, %f48
433 membar #Sync
434 wr %g0, FPRS_DU, %fprs
435 ba,pt %xcc, rt_continue
436 stb %l5, [%g6 + TI_FPDEPTH]