| David Howells | 607ca46 | 2012-10-13 10:46:48 +0100 | [diff] [blame] | 1 | /* $Id: scc.h,v 1.29 1997/04/02 14:56:45 jreuter Exp jreuter $ */ |
| 2 | |
| 3 | #ifndef _UAPI_SCC_H |
| 4 | #define _UAPI_SCC_H |
| 5 | |
| 6 | |
| 7 | /* selection of hardware types */ |
| 8 | |
| 9 | #define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */ |
| 10 | #define EAGLE 0x01 /* hardware type for EAGLE card */ |
| 11 | #define PC100 0x02 /* hardware type for PC100 card */ |
| 12 | #define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */ |
| 13 | #define DRSI 0x08 /* hardware type for DRSI PC*Packet card */ |
| 14 | #define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */ |
| 15 | |
| 16 | /* DEV ioctl() commands */ |
| 17 | |
| 18 | enum SCC_ioctl_cmds { |
| 19 | SIOCSCCRESERVED = SIOCDEVPRIVATE, |
| 20 | SIOCSCCCFG, |
| 21 | SIOCSCCINI, |
| 22 | SIOCSCCCHANINI, |
| 23 | SIOCSCCSMEM, |
| 24 | SIOCSCCGKISS, |
| 25 | SIOCSCCSKISS, |
| 26 | SIOCSCCGSTAT, |
| 27 | SIOCSCCCAL |
| 28 | }; |
| 29 | |
| 30 | /* Device parameter control (from WAMPES) */ |
| 31 | |
| 32 | enum L1_params { |
| 33 | PARAM_DATA, |
| 34 | PARAM_TXDELAY, |
| 35 | PARAM_PERSIST, |
| 36 | PARAM_SLOTTIME, |
| 37 | PARAM_TXTAIL, |
| 38 | PARAM_FULLDUP, |
| 39 | PARAM_SOFTDCD, /* was: PARAM_HW */ |
| 40 | PARAM_MUTE, /* ??? */ |
| 41 | PARAM_DTR, |
| 42 | PARAM_RTS, |
| 43 | PARAM_SPEED, |
| 44 | PARAM_ENDDELAY, /* ??? */ |
| 45 | PARAM_GROUP, |
| 46 | PARAM_IDLE, |
| 47 | PARAM_MIN, |
| 48 | PARAM_MAXKEY, |
| 49 | PARAM_WAIT, |
| 50 | PARAM_MAXDEFER, |
| 51 | PARAM_TX, |
| 52 | PARAM_HWEVENT = 31, |
| 53 | PARAM_RETURN = 255 /* reset kiss mode */ |
| 54 | }; |
| 55 | |
| 56 | /* fulldup parameter */ |
| 57 | |
| 58 | enum FULLDUP_modes { |
| 59 | KISS_DUPLEX_HALF, /* normal CSMA operation */ |
| 60 | KISS_DUPLEX_FULL, /* fullduplex, key down trx after transmission */ |
| 61 | KISS_DUPLEX_LINK, /* fullduplex, key down trx after 'idletime' sec */ |
| 62 | KISS_DUPLEX_OPTIMA /* fullduplex, let the protocol layer control the hw */ |
| 63 | }; |
| 64 | |
| 65 | /* misc. parameters */ |
| 66 | |
| 67 | #define TIMER_OFF 65535U /* to switch off timers */ |
| 68 | #define NO_SUCH_PARAM 65534U /* param not implemented */ |
| 69 | |
| 70 | /* HWEVENT parameter */ |
| 71 | |
| 72 | enum HWEVENT_opts { |
| 73 | HWEV_DCD_ON, |
| 74 | HWEV_DCD_OFF, |
| 75 | HWEV_ALL_SENT |
| 76 | }; |
| 77 | |
| 78 | /* channel grouping */ |
| 79 | |
| 80 | #define RXGROUP 0100 /* if set, only tx when all channels clear */ |
| 81 | #define TXGROUP 0200 /* if set, don't transmit simultaneously */ |
| 82 | |
| 83 | /* Tx/Rx clock sources */ |
| 84 | |
| 85 | enum CLOCK_sources { |
| 86 | CLK_DPLL, /* normal halfduplex operation */ |
| 87 | CLK_EXTERNAL, /* external clocking (G3RUH/DF9IC modems) */ |
| 88 | CLK_DIVIDER, /* Rx = DPLL, Tx = divider (fullduplex with */ |
| 89 | /* modems without clock regeneration */ |
| 90 | CLK_BRG /* experimental fullduplex mode with DPLL/BRG for */ |
| 91 | /* MODEMs without clock recovery */ |
| 92 | }; |
| 93 | |
| 94 | /* Tx state */ |
| 95 | |
| 96 | enum TX_state { |
| 97 | TXS_IDLE, /* Transmitter off, no data pending */ |
| 98 | TXS_BUSY, /* waiting for permission to send / tailtime */ |
| 99 | TXS_ACTIVE, /* Transmitter on, sending data */ |
| 100 | TXS_NEWFRAME, /* reset CRC and send (next) frame */ |
| 101 | TXS_IDLE2, /* Transmitter on, no data pending */ |
| 102 | TXS_WAIT, /* Waiting for Mintime to expire */ |
| 103 | TXS_TIMEOUT /* We had a transmission timeout */ |
| 104 | }; |
| 105 | |
| 106 | typedef unsigned long io_port; /* type definition for an 'io port address' */ |
| 107 | |
| 108 | /* SCC statistical information */ |
| 109 | |
| 110 | struct scc_stat { |
| 111 | long rxints; /* Receiver interrupts */ |
| 112 | long txints; /* Transmitter interrupts */ |
| 113 | long exints; /* External/status interrupts */ |
| 114 | long spints; /* Special receiver interrupts */ |
| 115 | |
| 116 | long txframes; /* Packets sent */ |
| 117 | long rxframes; /* Number of Frames Actually Received */ |
| 118 | long rxerrs; /* CRC Errors */ |
| 119 | long txerrs; /* KISS errors */ |
| 120 | |
| 121 | unsigned int nospace; /* "Out of buffers" */ |
| 122 | unsigned int rx_over; /* Receiver Overruns */ |
| 123 | unsigned int tx_under; /* Transmitter Underruns */ |
| 124 | |
| 125 | unsigned int tx_state; /* Transmitter state */ |
| 126 | int tx_queued; /* tx frames enqueued */ |
| 127 | |
| 128 | unsigned int maxqueue; /* allocated tx_buffers */ |
| 129 | unsigned int bufsize; /* used buffersize */ |
| 130 | }; |
| 131 | |
| 132 | struct scc_modem { |
| 133 | long speed; /* Line speed, bps */ |
| 134 | char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */ |
| 135 | char nrz; /* NRZ instead of NRZI */ |
| 136 | }; |
| 137 | |
| 138 | struct scc_kiss_cmd { |
| 139 | int command; /* one of the KISS-Commands defined above */ |
| 140 | unsigned param; /* KISS-Param */ |
| 141 | }; |
| 142 | |
| 143 | struct scc_hw_config { |
| 144 | io_port data_a; /* data port channel A */ |
| 145 | io_port ctrl_a; /* control port channel A */ |
| 146 | io_port data_b; /* data port channel B */ |
| 147 | io_port ctrl_b; /* control port channel B */ |
| 148 | io_port vector_latch; /* INTACK-Latch (#) */ |
| 149 | io_port special; /* special function port */ |
| 150 | |
| 151 | int irq; /* irq */ |
| 152 | long clock; /* clock */ |
| 153 | char option; /* command for function port */ |
| 154 | |
| 155 | char brand; /* hardware type */ |
| 156 | char escc; /* use ext. features of a 8580/85180/85280 */ |
| 157 | }; |
| 158 | |
| 159 | /* (#) only one INTACK latch allowed. */ |
| 160 | |
| 161 | |
| 162 | struct scc_mem_config { |
| 163 | unsigned int dummy; |
| 164 | unsigned int bufsize; |
| 165 | }; |
| 166 | |
| 167 | struct scc_calibrate { |
| 168 | unsigned int time; |
| 169 | unsigned char pattern; |
| 170 | }; |
| 171 | |
| 172 | #endif /* _UAPI_SCC_H */ |