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Jayachandran C65040e22011-11-16 00:21:28 +00001/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36#include <linux/kernel.h>
37#include <linux/threads.h>
38
39#include <asm/asm.h>
40#include <asm/asm-offsets.h>
41#include <asm/mipsregs.h>
42#include <asm/addrspace.h>
43#include <asm/string.h>
44
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47#include <asm/netlogic/mips-extns.h>
48
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/pic.h>
51#include <asm/netlogic/xlp-hal/xlp.h>
52#include <asm/netlogic/xlp-hal/sys.h>
53
Jayachandran C2a37b1a2012-10-31 12:01:37 +000054static int xlp_wakeup_core(uint64_t sysbase, int core)
Jayachandran C65040e22011-11-16 00:21:28 +000055{
Jayachandran C2a37b1a2012-10-31 12:01:37 +000056 uint32_t coremask, value;
Jayachandran C66d29982011-11-16 00:21:29 +000057 int count;
58
Jayachandran C2a37b1a2012-10-31 12:01:37 +000059 coremask = (1 << core);
Jayachandran C66d29982011-11-16 00:21:29 +000060
Jayachandran C2a37b1a2012-10-31 12:01:37 +000061 /* Enable CPU clock */
62 value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
63 value &= ~coremask;
64 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
Jayachandran C65040e22011-11-16 00:21:28 +000065
Jayachandran C2a37b1a2012-10-31 12:01:37 +000066 /* Remove CPU Reset */
67 value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
68 value &= ~coremask;
69 nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value);
Jayachandran C65040e22011-11-16 00:21:28 +000070
Jayachandran C2a37b1a2012-10-31 12:01:37 +000071 /* Poll for CPU to mark itself coherent */
72 count = 100000;
73 do {
74 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
75 } while ((value & coremask) != 0 && --count > 0);
Jayachandran C65040e22011-11-16 00:21:28 +000076
Jayachandran C2a37b1a2012-10-31 12:01:37 +000077 return count != 0;
78}
Jayachandran C65040e22011-11-16 00:21:28 +000079
Jayachandran C2a37b1a2012-10-31 12:01:37 +000080static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
81{
Jayachandran C77ae7982012-10-31 12:01:39 +000082 struct nlm_soc_info *nodep;
83 uint64_t syspcibase;
Jayachandran C2a37b1a2012-10-31 12:01:37 +000084 uint32_t syscoremask;
Jayachandran C77ae7982012-10-31 12:01:39 +000085 int core, n, cpu;
Jayachandran C66d29982011-11-16 00:21:29 +000086
Jayachandran C77ae7982012-10-31 12:01:39 +000087 for (n = 0; n < NLM_NR_NODES; n++) {
Jayachandran C2a37b1a2012-10-31 12:01:37 +000088 syspcibase = nlm_get_sys_pcibase(n);
89 if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
90 break;
91
92 /* read cores in reset from SYS and account for boot cpu */
Jayachandran C77ae7982012-10-31 12:01:39 +000093 nlm_node_init(n);
94 nodep = nlm_get_node(n);
95 syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET);
Jayachandran C2a37b1a2012-10-31 12:01:37 +000096 if (n == 0)
97 syscoremask |= 1;
98
Jayachandran C77ae7982012-10-31 12:01:39 +000099 for (core = 0; core < NLM_CORES_PER_NODE; core++) {
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000100 /* see if the core exists */
101 if ((syscoremask & (1 << core)) == 0)
102 continue;
103
104 /* see if at least the first thread is enabled */
Jayachandran C77ae7982012-10-31 12:01:39 +0000105 cpu = (n * NLM_CORES_PER_NODE + core)
106 * NLM_THREADS_PER_CORE;
107 if (!cpumask_test_cpu(cpu, wakeup_mask))
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000108 continue;
109
110 /* wake up the core */
Jayachandran C77ae7982012-10-31 12:01:39 +0000111 if (xlp_wakeup_core(nodep->sysbase, core))
112 nodep->coremask |= 1u << core;
113 else
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000114 pr_err("Failed to enable core %d\n", core);
115 }
Jayachandran C65040e22011-11-16 00:21:28 +0000116 }
117}
118
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000119void xlp_wakeup_secondary_cpus()
Jayachandran C65040e22011-11-16 00:21:28 +0000120{
Jayachandran C66d29982011-11-16 00:21:29 +0000121 /*
122 * In case of u-boot, the secondaries are in reset
123 * first wakeup core 0 threads
124 */
125 xlp_boot_core0_siblings();
Jayachandran C65040e22011-11-16 00:21:28 +0000126
Jayachandran C66d29982011-11-16 00:21:29 +0000127 /* now get other cores out of reset */
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000128 xlp_enable_secondary_cores(&nlm_cpumask);
Jayachandran C65040e22011-11-16 00:21:28 +0000129}