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review.evervolv.com / android_kernel_oneplus_msm8996 / 7925e89f54fc49bcd1e73f0a65c4a3eb35b9cfb1 / . / arch / arm / boot / dts / imx6dl.dtsi
blob: 62dc78126795fbc03d3ad339fedc2406a2edc624 [file] [log] [blame]
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]11#include "imx6qdl.dtsi"
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]12#include "imx6dl-pinfunc.h"
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame^]21 device_type = "cpu";
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]22 reg = <0>;
23 next-level-cache = <&L2>;
24 };
25
26 cpu@1 {
27 compatible = "arm,cortex-a9";
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame^]28 device_type = "cpu";
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]29 reg = <1>;
30 next-level-cache = <&L2>;
31 };
32 };
33
34 soc {
35 aips1: aips-bus@02000000 {
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]36 iomuxc: iomuxc@020e0000 {
37 compatible = "fsl,imx6dl-iomuxc";
38 reg = <0x020e0000 0x4000>;
39
40 enet {
41 pinctrl_enet_1: enetgrp-1 {
42 fsl,pins = <
43 MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
44 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
45 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
46 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
47 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
48 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
49 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
50 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
51 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
52 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
53 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
54 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
55 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
56 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
57 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
58 MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
59 >;
60 };
Shawn Guo1aa8b3e2013-04-02 14:38:11 +0800[diff] [blame]61
62 pinctrl_enet_2: enetgrp-2 {
63 fsl,pins = <
64 MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
65 MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
66 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
67 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
68 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
69 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
70 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
71 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
72 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
73 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
74 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
75 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
76 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
77 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
78 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
79 >;
80 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]81 };
82
83 uart1 {
84 pinctrl_uart1_1: uart1grp-1 {
85 fsl,pins = <
86 MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
87 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
88 >;
89 };
90 };
91
Shawn Guo1aa8b3e2013-04-02 14:38:11 +0800[diff] [blame]92 uart4 {
93 pinctrl_uart4_1: uart4grp-1 {
94 fsl,pins = <
95 MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
96 MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
97 >;
98 };
99 };
100
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]101 usbotg {
102 pinctrl_usbotg_2: usbotggrp-2 {
103 fsl,pins = <
104 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
105 >;
106 };
107 };
108
109 usdhc2 {
110 pinctrl_usdhc2_1: usdhc2grp-1 {
111 fsl,pins = <
112 MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
113 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
114 MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
115 MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
116 MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
117 MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
118 MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
119 MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
120 MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
121 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
122 >;
123 };
124 };
125
126 usdhc3 {
127 pinctrl_usdhc3_1: usdhc3grp-1 {
128 fsl,pins = <
129 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
130 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
131 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
132 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
133 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
134 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
135 MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
136 MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
137 MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
138 MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
139 >;
140 };
Fabio Estevam89b82912013-04-03 09:29:16 -0300[diff] [blame]141
142 pinctrl_usdhc3_2: usdhc3grp_2 {
143 fsl,pins = <
144 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
145 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
146 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
147 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
148 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
149 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
150 >;
151 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]152 };
153
154
155 };
156
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]157 pxp: pxp@020f0000 {
158 reg = <0x020f0000 0x4000>;
159 interrupts = <0 98 0x04>;
160 };
161
162 epdc: epdc@020f4000 {
163 reg = <0x020f4000 0x4000>;
164 interrupts = <0 97 0x04>;
165 };
166
167 lcdif: lcdif@020f8000 {
168 reg = <0x020f8000 0x4000>;
169 interrupts = <0 39 0x04>;
170 };
171 };
172
173 aips2: aips-bus@02100000 {
174 i2c4: i2c@021f8000 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx1-i2c";
178 reg = <0x021f8000 0x4000>;
179 interrupts = <0 35 0x04>;
180 status = "disabled";
181 };
182 };
183 };
184};