| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* | 
|  | 2 | * linux/kernel/irq/chip.c | 
|  | 3 | * | 
|  | 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | 
|  | 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | 
|  | 6 | * | 
|  | 7 | * This file contains the core interrupt handling code, for irq-chip | 
|  | 8 | * based architectures. | 
|  | 9 | * | 
|  | 10 | * Detailed information is available in Documentation/DocBook/genericirq | 
|  | 11 | */ | 
|  | 12 |  | 
|  | 13 | #include <linux/irq.h> | 
| Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> | 
|  | 16 | #include <linux/interrupt.h> | 
|  | 17 | #include <linux/kernel_stat.h> | 
|  | 18 |  | 
|  | 19 | #include "internals.h" | 
|  | 20 |  | 
| Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 21 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 22 | *	irq_set_chip - set the irq chip for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 23 | *	@irq:	irq number | 
|  | 24 | *	@chip:	pointer to irq chip description structure | 
|  | 25 | */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 27 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 28 | unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 29 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 30 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 31 | if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 32 | return -EINVAL; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 33 |  | 
|  | 34 | if (!chip) | 
|  | 35 | chip = &no_irq_chip; | 
|  | 36 |  | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 37 | desc->irq_data.chip = chip; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 38 | irq_put_desc_unlock(desc, flags); | 
| David Daney | d72274e | 2011-03-25 12:38:48 -0700 | [diff] [blame] | 39 | /* | 
|  | 40 | * For !CONFIG_SPARSE_IRQ make the irq show up in | 
|  | 41 | * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is | 
|  | 42 | * already marked, and this call is harmless. | 
|  | 43 | */ | 
|  | 44 | irq_reserve_irq(irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 45 | return 0; | 
|  | 46 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 47 | EXPORT_SYMBOL(irq_set_chip); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 48 |  | 
|  | 49 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 50 | *	irq_set_type - set the irq trigger type for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 51 | *	@irq:	irq number | 
| David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 52 | *	@type:	IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 53 | */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 54 | int irq_set_irq_type(unsigned int irq, unsigned int type) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 55 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 56 | unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 57 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); | 
|  | 58 | int ret = 0; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 59 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 60 | if (!desc) | 
|  | 61 | return -EINVAL; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 62 |  | 
| David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 63 | type &= IRQ_TYPE_SENSE_MASK; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 64 | if (type != IRQ_TYPE_NONE) | 
|  | 65 | ret = __irq_set_trigger(desc, irq, type); | 
|  | 66 | irq_put_desc_busunlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 67 | return ret; | 
|  | 68 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 69 | EXPORT_SYMBOL(irq_set_irq_type); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 70 |  | 
|  | 71 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 72 | *	irq_set_handler_data - set irq handler data for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 73 | *	@irq:	Interrupt number | 
|  | 74 | *	@data:	Pointer to interrupt specific data | 
|  | 75 | * | 
|  | 76 | *	Set the hardware irq controller data for an irq | 
|  | 77 | */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 78 | int irq_set_handler_data(unsigned int irq, void *data) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 79 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 80 | unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 81 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 82 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 83 | if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 84 | return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 85 | desc->irq_data.handler_data = data; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 86 | irq_put_desc_unlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 87 | return 0; | 
|  | 88 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 89 | EXPORT_SYMBOL(irq_set_handler_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 90 |  | 
|  | 91 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 92 | *	irq_set_msi_desc - set MSI descriptor data for an irq | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 93 | *	@irq:	Interrupt number | 
| Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 94 | *	@entry:	Pointer to MSI descriptor data | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 95 | * | 
| Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 96 | *	Set the MSI descriptor entry for an irq | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 97 | */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 98 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 99 | { | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 100 | unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 101 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 102 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 103 | if (!desc) | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 104 | return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 105 | desc->irq_data.msi_desc = entry; | 
| Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 106 | if (entry) | 
|  | 107 | entry->irq = irq; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 108 | irq_put_desc_unlock(desc, flags); | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 109 | return 0; | 
|  | 110 | } | 
|  | 111 |  | 
|  | 112 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 113 | *	irq_set_chip_data - set irq chip data for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 114 | *	@irq:	Interrupt number | 
|  | 115 | *	@data:	Pointer to chip specific data | 
|  | 116 | * | 
|  | 117 | *	Set the hardware irq chip data for an irq | 
|  | 118 | */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 119 | int irq_set_chip_data(unsigned int irq, void *data) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 120 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 121 | unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 122 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 123 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 124 | if (!desc) | 
| Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 125 | return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 126 | desc->irq_data.chip_data = data; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 127 | irq_put_desc_unlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 128 | return 0; | 
|  | 129 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 130 | EXPORT_SYMBOL(irq_set_chip_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 131 |  | 
| Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 132 | struct irq_data *irq_get_irq_data(unsigned int irq) | 
|  | 133 | { | 
|  | 134 | struct irq_desc *desc = irq_to_desc(irq); | 
|  | 135 |  | 
|  | 136 | return desc ? &desc->irq_data : NULL; | 
|  | 137 | } | 
|  | 138 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | 
|  | 139 |  | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 140 | static void irq_state_clr_disabled(struct irq_desc *desc) | 
|  | 141 | { | 
| Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 142 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 143 | } | 
|  | 144 |  | 
|  | 145 | static void irq_state_set_disabled(struct irq_desc *desc) | 
|  | 146 | { | 
| Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 147 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 148 | } | 
|  | 149 |  | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 150 | static void irq_state_clr_masked(struct irq_desc *desc) | 
|  | 151 | { | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 152 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 153 | } | 
|  | 154 |  | 
|  | 155 | static void irq_state_set_masked(struct irq_desc *desc) | 
|  | 156 | { | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 157 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 158 | } | 
|  | 159 |  | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 160 | int irq_startup(struct irq_desc *desc) | 
|  | 161 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 162 | irq_state_clr_disabled(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 163 | desc->depth = 0; | 
|  | 164 |  | 
| Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 165 | if (desc->irq_data.chip->irq_startup) { | 
|  | 166 | int ret = desc->irq_data.chip->irq_startup(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 167 | irq_state_clr_masked(desc); | 
| Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 168 | return ret; | 
|  | 169 | } | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 170 |  | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 171 | irq_enable(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 172 | return 0; | 
|  | 173 | } | 
|  | 174 |  | 
|  | 175 | void irq_shutdown(struct irq_desc *desc) | 
|  | 176 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 177 | irq_state_set_disabled(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 178 | desc->depth = 1; | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 179 | if (desc->irq_data.chip->irq_shutdown) | 
|  | 180 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | 
|  | 181 | if (desc->irq_data.chip->irq_disable) | 
|  | 182 | desc->irq_data.chip->irq_disable(&desc->irq_data); | 
|  | 183 | else | 
|  | 184 | desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 185 | irq_state_set_masked(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 186 | } | 
|  | 187 |  | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 188 | void irq_enable(struct irq_desc *desc) | 
|  | 189 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 190 | irq_state_clr_disabled(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 191 | if (desc->irq_data.chip->irq_enable) | 
|  | 192 | desc->irq_data.chip->irq_enable(&desc->irq_data); | 
|  | 193 | else | 
|  | 194 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 195 | irq_state_clr_masked(desc); | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 196 | } | 
|  | 197 |  | 
|  | 198 | void irq_disable(struct irq_desc *desc) | 
|  | 199 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 200 | irq_state_set_disabled(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 201 | if (desc->irq_data.chip->irq_disable) { | 
|  | 202 | desc->irq_data.chip->irq_disable(&desc->irq_data); | 
| Thomas Gleixner | a61d825 | 2011-02-21 12:54:34 +0100 | [diff] [blame] | 203 | irq_state_set_masked(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 204 | } | 
| Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 205 | } | 
|  | 206 |  | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 207 | static inline void mask_ack_irq(struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 208 | { | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 209 | if (desc->irq_data.chip->irq_mask_ack) | 
|  | 210 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 211 | else { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 212 | desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 213 | if (desc->irq_data.chip->irq_ack) | 
|  | 214 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 215 | } | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 216 | irq_state_set_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 217 | } | 
|  | 218 |  | 
| Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 219 | void mask_irq(struct irq_desc *desc) | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 220 | { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 221 | if (desc->irq_data.chip->irq_mask) { | 
|  | 222 | desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 223 | irq_state_set_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 224 | } | 
|  | 225 | } | 
|  | 226 |  | 
| Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 227 | void unmask_irq(struct irq_desc *desc) | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 228 | { | 
| Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 229 | if (desc->irq_data.chip->irq_unmask) { | 
|  | 230 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 231 | irq_state_clr_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 232 | } | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 233 | } | 
|  | 234 |  | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 235 | /* | 
|  | 236 | *	handle_nested_irq - Handle a nested irq from a irq thread | 
|  | 237 | *	@irq:	the interrupt number | 
|  | 238 | * | 
|  | 239 | *	Handle interrupts which are nested into a threaded interrupt | 
|  | 240 | *	handler. The handler function is called inside the calling | 
|  | 241 | *	threads context. | 
|  | 242 | */ | 
|  | 243 | void handle_nested_irq(unsigned int irq) | 
|  | 244 | { | 
|  | 245 | struct irq_desc *desc = irq_to_desc(irq); | 
|  | 246 | struct irqaction *action; | 
|  | 247 | irqreturn_t action_ret; | 
|  | 248 |  | 
|  | 249 | might_sleep(); | 
|  | 250 |  | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 251 | raw_spin_lock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 252 |  | 
|  | 253 | kstat_incr_irqs_this_cpu(irq, desc); | 
|  | 254 |  | 
|  | 255 | action = desc->action; | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 256 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 257 | goto out_unlock; | 
|  | 258 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 259 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 260 | raw_spin_unlock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 261 |  | 
|  | 262 | action_ret = action->thread_fn(action->irq, action->dev_id); | 
|  | 263 | if (!noirqdebug) | 
|  | 264 | note_interrupt(irq, desc, action_ret); | 
|  | 265 |  | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 266 | raw_spin_lock_irq(&desc->lock); | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 267 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 268 |  | 
|  | 269 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 270 | raw_spin_unlock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 271 | } | 
|  | 272 | EXPORT_SYMBOL_GPL(handle_nested_irq); | 
|  | 273 |  | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 274 | static bool irq_check_poll(struct irq_desc *desc) | 
|  | 275 | { | 
| Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 276 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 277 | return false; | 
|  | 278 | return irq_wait_for_poll(desc); | 
|  | 279 | } | 
|  | 280 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 281 | /** | 
|  | 282 | *	handle_simple_irq - Simple and software-decoded IRQs. | 
|  | 283 | *	@irq:	the interrupt number | 
|  | 284 | *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 285 | * | 
|  | 286 | *	Simple interrupts are either sent from a demultiplexing interrupt | 
|  | 287 | *	handler or come from hardware, where no interrupt hardware control | 
|  | 288 | *	is necessary. | 
|  | 289 | * | 
|  | 290 | *	Note: The caller is expected to handle the ack, clear, mask and | 
|  | 291 | *	unmask issues if necessary. | 
|  | 292 | */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 293 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 294 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 295 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 296 | raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 297 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 298 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 299 | if (!irq_check_poll(desc)) | 
|  | 300 | goto out_unlock; | 
|  | 301 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 302 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 303 | kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 304 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 305 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 306 | goto out_unlock; | 
|  | 307 |  | 
| Thomas Gleixner | 107781e | 2011-02-07 01:21:02 +0100 | [diff] [blame] | 308 | handle_irq_event(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 309 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 310 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 311 | raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 312 | } | 
|  | 313 |  | 
|  | 314 | /** | 
|  | 315 | *	handle_level_irq - Level type irq handler | 
|  | 316 | *	@irq:	the interrupt number | 
|  | 317 | *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 318 | * | 
|  | 319 | *	Level type interrupts are active as long as the hardware line has | 
|  | 320 | *	the active level. This may require to mask the interrupt and unmask | 
|  | 321 | *	it after the associated handler has acknowledged the device, so the | 
|  | 322 | *	interrupt line is back to inactive. | 
|  | 323 | */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 324 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 325 | handle_level_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 326 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 327 | raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 328 | mask_ack_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 329 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 330 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 331 | if (!irq_check_poll(desc)) | 
|  | 332 | goto out_unlock; | 
|  | 333 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 334 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 335 | kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 336 |  | 
|  | 337 | /* | 
|  | 338 | * If its disabled or no action available | 
|  | 339 | * keep it masked and get out of here | 
|  | 340 | */ | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 341 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) | 
| Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 342 | goto out_unlock; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 343 |  | 
| Thomas Gleixner | 1529866 | 2011-02-07 01:22:17 +0100 | [diff] [blame] | 344 | handle_irq_event(desc); | 
| Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 345 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 346 | if (!irqd_irq_disabled(&desc->irq_data) && !(desc->istate & IRQS_ONESHOT)) | 
| Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 347 | unmask_irq(desc); | 
| Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 348 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 349 | raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 350 | } | 
| Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 351 | EXPORT_SYMBOL_GPL(handle_level_irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 352 |  | 
| Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 353 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI | 
|  | 354 | static inline void preflow_handler(struct irq_desc *desc) | 
|  | 355 | { | 
|  | 356 | if (desc->preflow_handler) | 
|  | 357 | desc->preflow_handler(&desc->irq_data); | 
|  | 358 | } | 
|  | 359 | #else | 
|  | 360 | static inline void preflow_handler(struct irq_desc *desc) { } | 
|  | 361 | #endif | 
|  | 362 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 363 | /** | 
| Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 364 | *	handle_fasteoi_irq - irq handler for transparent controllers | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 365 | *	@irq:	the interrupt number | 
|  | 366 | *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 367 | * | 
| Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 368 | *	Only a single callback will be issued to the chip: an ->eoi() | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 369 | *	call when the interrupt has been serviced. This enables support | 
|  | 370 | *	for modern forms of interrupt handlers, which handle the flow | 
|  | 371 | *	details in hardware, transparently. | 
|  | 372 | */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 373 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 374 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 375 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 376 | raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 377 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 378 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 379 | if (!irq_check_poll(desc)) | 
|  | 380 | goto out; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 381 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 382 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 383 | kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 384 |  | 
|  | 385 | /* | 
|  | 386 | * If its disabled or no action available | 
| Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 387 | * then mask it and get out of here: | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 388 | */ | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 389 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 390 | desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 391 | mask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 392 | goto out; | 
| Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 393 | } | 
| Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 394 |  | 
|  | 395 | if (desc->istate & IRQS_ONESHOT) | 
|  | 396 | mask_irq(desc); | 
|  | 397 |  | 
| Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 398 | preflow_handler(desc); | 
| Thomas Gleixner | a7ae4de | 2011-02-07 01:23:07 +0100 | [diff] [blame] | 399 | handle_irq_event(desc); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 400 |  | 
|  | 401 | out_eoi: | 
| Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 402 | desc->irq_data.chip->irq_eoi(&desc->irq_data); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 403 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 404 | raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 405 | return; | 
|  | 406 | out: | 
|  | 407 | if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED)) | 
|  | 408 | goto out_eoi; | 
|  | 409 | goto out_unlock; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 410 | } | 
|  | 411 |  | 
|  | 412 | /** | 
|  | 413 | *	handle_edge_irq - edge type IRQ handler | 
|  | 414 | *	@irq:	the interrupt number | 
|  | 415 | *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 416 | * | 
|  | 417 | *	Interrupt occures on the falling and/or rising edge of a hardware | 
| Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 418 | *	signal. The occurrence is latched into the irq controller hardware | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 419 | *	and must be acked in order to be reenabled. After the ack another | 
|  | 420 | *	interrupt can happen on the same source even before the first one | 
| Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 421 | *	is handled by the associated event handler. If this happens it | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 422 | *	might be necessary to disable (mask) the interrupt depending on the | 
|  | 423 | *	controller hardware. This requires to reenable the interrupt inside | 
|  | 424 | *	of the loop which handles the interrupts which have arrived while | 
|  | 425 | *	the handler was running. If all pending interrupts are handled, the | 
|  | 426 | *	loop is left. | 
|  | 427 | */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 428 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 429 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 430 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 431 | raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 432 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 433 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 434 | /* | 
|  | 435 | * If we're currently running this IRQ, or its disabled, | 
|  | 436 | * we shouldn't process the IRQ. Mark it pending, handle | 
|  | 437 | * the necessary masking and go out | 
|  | 438 | */ | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 439 | if (unlikely(irqd_irq_disabled(&desc->irq_data) || | 
|  | 440 | irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 441 | if (!irq_check_poll(desc)) { | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 442 | desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 443 | mask_ack_irq(desc); | 
|  | 444 | goto out_unlock; | 
|  | 445 | } | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 446 | } | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 447 | kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 448 |  | 
|  | 449 | /* Start handling the irq */ | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 450 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 451 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 452 | do { | 
| Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 453 | if (unlikely(!desc->action)) { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 454 | mask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 455 | goto out_unlock; | 
|  | 456 | } | 
|  | 457 |  | 
|  | 458 | /* | 
|  | 459 | * When another irq arrived while we were handling | 
|  | 460 | * one, we could have masked the irq. | 
|  | 461 | * Renable it, if it was not disabled in meantime. | 
|  | 462 | */ | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 463 | if (unlikely(desc->istate & IRQS_PENDING)) { | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 464 | if (!irqd_irq_disabled(&desc->irq_data) && | 
|  | 465 | irqd_irq_masked(&desc->irq_data)) | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 466 | unmask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 467 | } | 
|  | 468 |  | 
| Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 469 | handle_irq_event(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 470 |  | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 471 | } while ((desc->istate & IRQS_PENDING) && | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 472 | !irqd_irq_disabled(&desc->irq_data)); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 473 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 474 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 475 | raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 476 | } | 
|  | 477 |  | 
| Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 478 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER | 
|  | 479 | /** | 
|  | 480 | *	handle_edge_eoi_irq - edge eoi type IRQ handler | 
|  | 481 | *	@irq:	the interrupt number | 
|  | 482 | *	@desc:	the interrupt description structure for this irq | 
|  | 483 | * | 
|  | 484 | * Similar as the above handle_edge_irq, but using eoi and w/o the | 
|  | 485 | * mask/unmask logic. | 
|  | 486 | */ | 
|  | 487 | void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc) | 
|  | 488 | { | 
|  | 489 | struct irq_chip *chip = irq_desc_get_chip(desc); | 
|  | 490 |  | 
|  | 491 | raw_spin_lock(&desc->lock); | 
|  | 492 |  | 
|  | 493 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
|  | 494 | /* | 
|  | 495 | * If we're currently running this IRQ, or its disabled, | 
|  | 496 | * we shouldn't process the IRQ. Mark it pending, handle | 
|  | 497 | * the necessary masking and go out | 
|  | 498 | */ | 
|  | 499 | if (unlikely(irqd_irq_disabled(&desc->irq_data) || | 
|  | 500 | irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | 
|  | 501 | if (!irq_check_poll(desc)) { | 
|  | 502 | desc->istate |= IRQS_PENDING; | 
|  | 503 | goto out_eoi; | 
|  | 504 | } | 
|  | 505 | } | 
|  | 506 | kstat_incr_irqs_this_cpu(irq, desc); | 
|  | 507 |  | 
|  | 508 | do { | 
|  | 509 | if (unlikely(!desc->action)) | 
|  | 510 | goto out_eoi; | 
|  | 511 |  | 
|  | 512 | handle_irq_event(desc); | 
|  | 513 |  | 
|  | 514 | } while ((desc->istate & IRQS_PENDING) && | 
|  | 515 | !irqd_irq_disabled(&desc->irq_data)); | 
|  | 516 |  | 
| Stephen Rothwell | ac0e044 | 2011-03-30 10:55:12 +1100 | [diff] [blame] | 517 | out_eoi: | 
| Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 518 | chip->irq_eoi(&desc->irq_data); | 
|  | 519 | raw_spin_unlock(&desc->lock); | 
|  | 520 | } | 
|  | 521 | #endif | 
|  | 522 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 523 | /** | 
| Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 524 | *	handle_percpu_irq - Per CPU local irq handler | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 525 | *	@irq:	the interrupt number | 
|  | 526 | *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 527 | * | 
|  | 528 | *	Per CPU interrupts on SMP machines without locking requirements | 
|  | 529 | */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 530 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 531 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 532 | { | 
| Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 533 | struct irq_chip *chip = irq_desc_get_chip(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 534 |  | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 535 | kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 536 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 537 | if (chip->irq_ack) | 
|  | 538 | chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 539 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 540 | handle_irq_event_percpu(desc, desc->action); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 541 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 542 | if (chip->irq_eoi) | 
|  | 543 | chip->irq_eoi(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 544 | } | 
|  | 545 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 546 | void | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 547 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 548 | const char *name) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 549 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 550 | unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 551 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 552 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 553 | if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 554 | return; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 555 |  | 
| Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 556 | if (!handle) { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 557 | handle = handle_bad_irq; | 
| Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 558 | } else { | 
|  | 559 | if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 560 | goto out; | 
| Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 561 | } | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 562 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 563 | /* Uninstall? */ | 
|  | 564 | if (handle == handle_bad_irq) { | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 565 | if (desc->irq_data.chip != &no_irq_chip) | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 566 | mask_ack_irq(desc); | 
| Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 567 | irq_state_set_disabled(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 568 | desc->depth = 1; | 
|  | 569 | } | 
|  | 570 | desc->handle_irq = handle; | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 571 | desc->name = name; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 572 |  | 
|  | 573 | if (handle != handle_bad_irq && is_chained) { | 
| Thomas Gleixner | 1ccb4e6 | 2011-02-09 14:44:17 +0100 | [diff] [blame] | 574 | irq_settings_set_noprobe(desc); | 
|  | 575 | irq_settings_set_norequest(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 576 | irq_startup(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 577 | } | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 578 | out: | 
|  | 579 | irq_put_desc_busunlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 580 | } | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 581 | EXPORT_SYMBOL_GPL(__irq_set_handler); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 582 |  | 
|  | 583 | void | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 584 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 585 | irq_flow_handler_t handle, const char *name) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 586 | { | 
| Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 587 | irq_set_chip(irq, chip); | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 588 | __irq_set_handler(irq, handle, 0, name); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 589 | } | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 590 |  | 
| Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 591 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 592 | { | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 593 | unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 594 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 595 |  | 
| Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 596 | if (!desc) | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 597 | return; | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 598 | irq_settings_clr_and_set(desc, clr, set); | 
|  | 599 |  | 
| Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 600 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | | 
| Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 601 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 602 | if (irq_settings_has_no_balance_set(desc)) | 
|  | 603 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | 
|  | 604 | if (irq_settings_is_per_cpu(desc)) | 
|  | 605 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | 
| Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 606 | if (irq_settings_can_move_pcntxt(desc)) | 
|  | 607 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | 
| Thomas Gleixner | 0ef5ca1 | 2011-03-28 21:59:37 +0200 | [diff] [blame] | 608 | if (irq_settings_is_level(desc)) | 
|  | 609 | irqd_set(&desc->irq_data, IRQD_LEVEL); | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 610 |  | 
| Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 611 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); | 
|  | 612 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 613 | irq_put_desc_unlock(desc, flags); | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 614 | } | 
| David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 615 |  | 
|  | 616 | /** | 
|  | 617 | *	irq_cpu_online - Invoke all irq_cpu_online functions. | 
|  | 618 | * | 
|  | 619 | *	Iterate through all irqs and invoke the chip.irq_cpu_online() | 
|  | 620 | *	for each. | 
|  | 621 | */ | 
|  | 622 | void irq_cpu_online(void) | 
|  | 623 | { | 
|  | 624 | struct irq_desc *desc; | 
|  | 625 | struct irq_chip *chip; | 
|  | 626 | unsigned long flags; | 
|  | 627 | unsigned int irq; | 
|  | 628 |  | 
|  | 629 | for_each_active_irq(irq) { | 
|  | 630 | desc = irq_to_desc(irq); | 
|  | 631 | if (!desc) | 
|  | 632 | continue; | 
|  | 633 |  | 
|  | 634 | raw_spin_lock_irqsave(&desc->lock, flags); | 
|  | 635 |  | 
|  | 636 | chip = irq_data_get_irq_chip(&desc->irq_data); | 
| Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 637 | if (chip && chip->irq_cpu_online && | 
|  | 638 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 639 | !irqd_irq_disabled(&desc->irq_data))) | 
| David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 640 | chip->irq_cpu_online(&desc->irq_data); | 
|  | 641 |  | 
|  | 642 | raw_spin_unlock_irqrestore(&desc->lock, flags); | 
|  | 643 | } | 
|  | 644 | } | 
|  | 645 |  | 
|  | 646 | /** | 
|  | 647 | *	irq_cpu_offline - Invoke all irq_cpu_offline functions. | 
|  | 648 | * | 
|  | 649 | *	Iterate through all irqs and invoke the chip.irq_cpu_offline() | 
|  | 650 | *	for each. | 
|  | 651 | */ | 
|  | 652 | void irq_cpu_offline(void) | 
|  | 653 | { | 
|  | 654 | struct irq_desc *desc; | 
|  | 655 | struct irq_chip *chip; | 
|  | 656 | unsigned long flags; | 
|  | 657 | unsigned int irq; | 
|  | 658 |  | 
|  | 659 | for_each_active_irq(irq) { | 
|  | 660 | desc = irq_to_desc(irq); | 
|  | 661 | if (!desc) | 
|  | 662 | continue; | 
|  | 663 |  | 
|  | 664 | raw_spin_lock_irqsave(&desc->lock, flags); | 
|  | 665 |  | 
|  | 666 | chip = irq_data_get_irq_chip(&desc->irq_data); | 
| Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 667 | if (chip && chip->irq_cpu_offline && | 
|  | 668 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 669 | !irqd_irq_disabled(&desc->irq_data))) | 
| David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 670 | chip->irq_cpu_offline(&desc->irq_data); | 
|  | 671 |  | 
|  | 672 | raw_spin_unlock_irqrestore(&desc->lock, flags); | 
|  | 673 | } | 
|  | 674 | } |