blob: 802b1c41ff6a2982ab3ec88d376b2f26e613bab7 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
Ralf Baechle41943182005-05-05 16:45:59 +000011 * Copyright (C) 2003, 2004 Maciej W. Rozycki
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/config.h>
17#include <linux/linkage.h>
18#include <asm/hazards.h>
19
20/*
21 * The following macros are especially useful for __asm__
22 * inline assembler.
23 */
24#ifndef __STR
25#define __STR(x) #x
26#endif
27#ifndef STR
28#define STR(x) __STR(x)
29#endif
30
31/*
32 * Configure language
33 */
34#ifdef __ASSEMBLY__
35#define _ULCAST_
36#else
37#define _ULCAST_ (unsigned long)
38#endif
39
40/*
41 * Coprocessor 0 register names
42 */
43#define CP0_INDEX $0
44#define CP0_RANDOM $1
45#define CP0_ENTRYLO0 $2
46#define CP0_ENTRYLO1 $3
47#define CP0_CONF $3
48#define CP0_CONTEXT $4
49#define CP0_PAGEMASK $5
50#define CP0_WIRED $6
51#define CP0_INFO $7
52#define CP0_BADVADDR $8
53#define CP0_COUNT $9
54#define CP0_ENTRYHI $10
55#define CP0_COMPARE $11
56#define CP0_STATUS $12
57#define CP0_CAUSE $13
58#define CP0_EPC $14
59#define CP0_PRID $15
60#define CP0_CONFIG $16
61#define CP0_LLADDR $17
62#define CP0_WATCHLO $18
63#define CP0_WATCHHI $19
64#define CP0_XCONTEXT $20
65#define CP0_FRAMEMASK $21
66#define CP0_DIAGNOSTIC $22
67#define CP0_DEBUG $23
68#define CP0_DEPC $24
69#define CP0_PERFORMANCE $25
70#define CP0_ECC $26
71#define CP0_CACHEERR $27
72#define CP0_TAGLO $28
73#define CP0_TAGHI $29
74#define CP0_ERROREPC $30
75#define CP0_DESAVE $31
76
77/*
78 * R4640/R4650 cp0 register names. These registers are listed
79 * here only for completeness; without MMU these CPUs are not useable
80 * by Linux. A future ELKS port might take make Linux run on them
81 * though ...
82 */
83#define CP0_IBASE $0
84#define CP0_IBOUND $1
85#define CP0_DBASE $2
86#define CP0_DBOUND $3
87#define CP0_CALG $17
88#define CP0_IWATCH $18
89#define CP0_DWATCH $19
90
91/*
92 * Coprocessor 0 Set 1 register names
93 */
94#define CP0_S1_DERRADDR0 $26
95#define CP0_S1_DERRADDR1 $27
96#define CP0_S1_INTCONTROL $20
97
98/*
Ralf Baechle7a0fc582005-07-13 19:47:28 +000099 * Coprocessor 0 Set 2 register names
100 */
101#define CP0_S2_SRSCTL $12 /* MIPSR2 */
102
103/*
104 * Coprocessor 0 Set 3 register names
105 */
106#define CP0_S3_SRSMAP $12 /* MIPSR2 */
107
108/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 * TX39 Series
110 */
111#define CP0_TX39_CACHE $7
112
113/*
114 * Coprocessor 1 (FPU) register names
115 */
116#define CP1_REVISION $0
117#define CP1_STATUS $31
118
119/*
120 * FPU Status Register Values
121 */
122/*
123 * Status Register Values
124 */
125
126#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
127#define FPU_CSR_COND 0x00800000 /* $fcc0 */
128#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
129#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
130#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
131#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
132#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
133#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
134#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
135#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
136
137/*
138 * X the exception cause indicator
139 * E the exception enable
140 * S the sticky/flag bit
141*/
142#define FPU_CSR_ALL_X 0x0003f000
143#define FPU_CSR_UNI_X 0x00020000
144#define FPU_CSR_INV_X 0x00010000
145#define FPU_CSR_DIV_X 0x00008000
146#define FPU_CSR_OVF_X 0x00004000
147#define FPU_CSR_UDF_X 0x00002000
148#define FPU_CSR_INE_X 0x00001000
149
150#define FPU_CSR_ALL_E 0x00000f80
151#define FPU_CSR_INV_E 0x00000800
152#define FPU_CSR_DIV_E 0x00000400
153#define FPU_CSR_OVF_E 0x00000200
154#define FPU_CSR_UDF_E 0x00000100
155#define FPU_CSR_INE_E 0x00000080
156
157#define FPU_CSR_ALL_S 0x0000007c
158#define FPU_CSR_INV_S 0x00000040
159#define FPU_CSR_DIV_S 0x00000020
160#define FPU_CSR_OVF_S 0x00000010
161#define FPU_CSR_UDF_S 0x00000008
162#define FPU_CSR_INE_S 0x00000004
163
164/* rounding mode */
165#define FPU_CSR_RN 0x0 /* nearest */
166#define FPU_CSR_RZ 0x1 /* towards zero */
167#define FPU_CSR_RU 0x2 /* towards +Infinity */
168#define FPU_CSR_RD 0x3 /* towards -Infinity */
169
170
171/*
172 * Values for PageMask register
173 */
174#ifdef CONFIG_CPU_VR41XX
175
176/* Why doesn't stupidity hurt ... */
177
178#define PM_1K 0x00000000
179#define PM_4K 0x00001800
180#define PM_16K 0x00007800
181#define PM_64K 0x0001f800
182#define PM_256K 0x0007f800
183
184#else
185
186#define PM_4K 0x00000000
187#define PM_16K 0x00006000
188#define PM_64K 0x0001e000
189#define PM_256K 0x0007e000
190#define PM_1M 0x001fe000
191#define PM_4M 0x007fe000
192#define PM_16M 0x01ffe000
193#define PM_64M 0x07ffe000
194#define PM_256M 0x1fffe000
195
196#endif
197
198/*
199 * Default page size for a given kernel configuration
200 */
201#ifdef CONFIG_PAGE_SIZE_4KB
202#define PM_DEFAULT_MASK PM_4K
203#elif defined(CONFIG_PAGE_SIZE_16KB)
204#define PM_DEFAULT_MASK PM_16K
205#elif defined(CONFIG_PAGE_SIZE_64KB)
206#define PM_DEFAULT_MASK PM_64K
207#else
208#error Bad page size configuration!
209#endif
210
211
212/*
213 * Values used for computation of new tlb entries
214 */
215#define PL_4K 12
216#define PL_16K 14
217#define PL_64K 16
218#define PL_256K 18
219#define PL_1M 20
220#define PL_4M 22
221#define PL_16M 24
222#define PL_64M 26
223#define PL_256M 28
224
225/*
226 * R4x00 interrupt enable / cause bits
227 */
228#define IE_SW0 (_ULCAST_(1) << 8)
229#define IE_SW1 (_ULCAST_(1) << 9)
230#define IE_IRQ0 (_ULCAST_(1) << 10)
231#define IE_IRQ1 (_ULCAST_(1) << 11)
232#define IE_IRQ2 (_ULCAST_(1) << 12)
233#define IE_IRQ3 (_ULCAST_(1) << 13)
234#define IE_IRQ4 (_ULCAST_(1) << 14)
235#define IE_IRQ5 (_ULCAST_(1) << 15)
236
237/*
238 * R4x00 interrupt cause bits
239 */
240#define C_SW0 (_ULCAST_(1) << 8)
241#define C_SW1 (_ULCAST_(1) << 9)
242#define C_IRQ0 (_ULCAST_(1) << 10)
243#define C_IRQ1 (_ULCAST_(1) << 11)
244#define C_IRQ2 (_ULCAST_(1) << 12)
245#define C_IRQ3 (_ULCAST_(1) << 13)
246#define C_IRQ4 (_ULCAST_(1) << 14)
247#define C_IRQ5 (_ULCAST_(1) << 15)
248
249/*
250 * Bitfields in the R4xx0 cp0 status register
251 */
252#define ST0_IE 0x00000001
253#define ST0_EXL 0x00000002
254#define ST0_ERL 0x00000004
255#define ST0_KSU 0x00000018
256# define KSU_USER 0x00000010
257# define KSU_SUPERVISOR 0x00000008
258# define KSU_KERNEL 0x00000000
259#define ST0_UX 0x00000020
260#define ST0_SX 0x00000040
261#define ST0_KX 0x00000080
262#define ST0_DE 0x00010000
263#define ST0_CE 0x00020000
264
265/*
266 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
267 * cacheops in userspace. This bit exists only on RM7000 and RM9000
268 * processors.
269 */
270#define ST0_CO 0x08000000
271
272/*
273 * Bitfields in the R[23]000 cp0 status register.
274 */
275#define ST0_IEC 0x00000001
276#define ST0_KUC 0x00000002
277#define ST0_IEP 0x00000004
278#define ST0_KUP 0x00000008
279#define ST0_IEO 0x00000010
280#define ST0_KUO 0x00000020
281/* bits 6 & 7 are reserved on R[23]000 */
282#define ST0_ISC 0x00010000
283#define ST0_SWC 0x00020000
284#define ST0_CM 0x00080000
285
286/*
287 * Bits specific to the R4640/R4650
288 */
289#define ST0_UM (_ULCAST_(1) << 4)
290#define ST0_IL (_ULCAST_(1) << 23)
291#define ST0_DL (_ULCAST_(1) << 24)
292
293/*
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +0000294 * Enable the MIPS DSP ASE
295 */
296#define ST0_MX 0x01000000
297
298/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 * Bitfields in the TX39 family CP0 Configuration Register 3
300 */
301#define TX39_CONF_ICS_SHIFT 19
302#define TX39_CONF_ICS_MASK 0x00380000
303#define TX39_CONF_ICS_1KB 0x00000000
304#define TX39_CONF_ICS_2KB 0x00080000
305#define TX39_CONF_ICS_4KB 0x00100000
306#define TX39_CONF_ICS_8KB 0x00180000
307#define TX39_CONF_ICS_16KB 0x00200000
308
309#define TX39_CONF_DCS_SHIFT 16
310#define TX39_CONF_DCS_MASK 0x00070000
311#define TX39_CONF_DCS_1KB 0x00000000
312#define TX39_CONF_DCS_2KB 0x00010000
313#define TX39_CONF_DCS_4KB 0x00020000
314#define TX39_CONF_DCS_8KB 0x00030000
315#define TX39_CONF_DCS_16KB 0x00040000
316
317#define TX39_CONF_CWFON 0x00004000
318#define TX39_CONF_WBON 0x00002000
319#define TX39_CONF_RF_SHIFT 10
320#define TX39_CONF_RF_MASK 0x00000c00
321#define TX39_CONF_DOZE 0x00000200
322#define TX39_CONF_HALT 0x00000100
323#define TX39_CONF_LOCK 0x00000080
324#define TX39_CONF_ICE 0x00000020
325#define TX39_CONF_DCE 0x00000010
326#define TX39_CONF_IRSIZE_SHIFT 2
327#define TX39_CONF_IRSIZE_MASK 0x0000000c
328#define TX39_CONF_DRSIZE_SHIFT 0
329#define TX39_CONF_DRSIZE_MASK 0x00000003
330
331/*
332 * Status register bits available in all MIPS CPUs.
333 */
334#define ST0_IM 0x0000ff00
335#define STATUSB_IP0 8
336#define STATUSF_IP0 (_ULCAST_(1) << 8)
337#define STATUSB_IP1 9
338#define STATUSF_IP1 (_ULCAST_(1) << 9)
339#define STATUSB_IP2 10
340#define STATUSF_IP2 (_ULCAST_(1) << 10)
341#define STATUSB_IP3 11
342#define STATUSF_IP3 (_ULCAST_(1) << 11)
343#define STATUSB_IP4 12
344#define STATUSF_IP4 (_ULCAST_(1) << 12)
345#define STATUSB_IP5 13
346#define STATUSF_IP5 (_ULCAST_(1) << 13)
347#define STATUSB_IP6 14
348#define STATUSF_IP6 (_ULCAST_(1) << 14)
349#define STATUSB_IP7 15
350#define STATUSF_IP7 (_ULCAST_(1) << 15)
351#define STATUSB_IP8 0
352#define STATUSF_IP8 (_ULCAST_(1) << 0)
353#define STATUSB_IP9 1
354#define STATUSF_IP9 (_ULCAST_(1) << 1)
355#define STATUSB_IP10 2
356#define STATUSF_IP10 (_ULCAST_(1) << 2)
357#define STATUSB_IP11 3
358#define STATUSF_IP11 (_ULCAST_(1) << 3)
359#define STATUSB_IP12 4
360#define STATUSF_IP12 (_ULCAST_(1) << 4)
361#define STATUSB_IP13 5
362#define STATUSF_IP13 (_ULCAST_(1) << 5)
363#define STATUSB_IP14 6
364#define STATUSF_IP14 (_ULCAST_(1) << 6)
365#define STATUSB_IP15 7
366#define STATUSF_IP15 (_ULCAST_(1) << 7)
367#define ST0_CH 0x00040000
368#define ST0_SR 0x00100000
369#define ST0_TS 0x00200000
370#define ST0_BEV 0x00400000
371#define ST0_RE 0x02000000
372#define ST0_FR 0x04000000
373#define ST0_CU 0xf0000000
374#define ST0_CU0 0x10000000
375#define ST0_CU1 0x20000000
376#define ST0_CU2 0x40000000
377#define ST0_CU3 0x80000000
378#define ST0_XX 0x80000000 /* MIPS IV naming */
379
380/*
381 * Bitfields and bit numbers in the coprocessor 0 cause register.
382 *
383 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
384 */
385#define CAUSEB_EXCCODE 2
386#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
387#define CAUSEB_IP 8
388#define CAUSEF_IP (_ULCAST_(255) << 8)
389#define CAUSEB_IP0 8
390#define CAUSEF_IP0 (_ULCAST_(1) << 8)
391#define CAUSEB_IP1 9
392#define CAUSEF_IP1 (_ULCAST_(1) << 9)
393#define CAUSEB_IP2 10
394#define CAUSEF_IP2 (_ULCAST_(1) << 10)
395#define CAUSEB_IP3 11
396#define CAUSEF_IP3 (_ULCAST_(1) << 11)
397#define CAUSEB_IP4 12
398#define CAUSEF_IP4 (_ULCAST_(1) << 12)
399#define CAUSEB_IP5 13
400#define CAUSEF_IP5 (_ULCAST_(1) << 13)
401#define CAUSEB_IP6 14
402#define CAUSEF_IP6 (_ULCAST_(1) << 14)
403#define CAUSEB_IP7 15
404#define CAUSEF_IP7 (_ULCAST_(1) << 15)
405#define CAUSEB_IV 23
406#define CAUSEF_IV (_ULCAST_(1) << 23)
407#define CAUSEB_CE 28
408#define CAUSEF_CE (_ULCAST_(3) << 28)
409#define CAUSEB_BD 31
410#define CAUSEF_BD (_ULCAST_(1) << 31)
411
412/*
413 * Bits in the coprocessor 0 config register.
414 */
415/* Generic bits. */
416#define CONF_CM_CACHABLE_NO_WA 0
417#define CONF_CM_CACHABLE_WA 1
418#define CONF_CM_UNCACHED 2
419#define CONF_CM_CACHABLE_NONCOHERENT 3
420#define CONF_CM_CACHABLE_CE 4
421#define CONF_CM_CACHABLE_COW 5
422#define CONF_CM_CACHABLE_CUW 6
423#define CONF_CM_CACHABLE_ACCELERATED 7
424#define CONF_CM_CMASK 7
425#define CONF_BE (_ULCAST_(1) << 15)
426
427/* Bits common to various processors. */
428#define CONF_CU (_ULCAST_(1) << 3)
429#define CONF_DB (_ULCAST_(1) << 4)
430#define CONF_IB (_ULCAST_(1) << 5)
431#define CONF_DC (_ULCAST_(7) << 6)
432#define CONF_IC (_ULCAST_(7) << 9)
433#define CONF_EB (_ULCAST_(1) << 13)
434#define CONF_EM (_ULCAST_(1) << 14)
435#define CONF_SM (_ULCAST_(1) << 16)
436#define CONF_SC (_ULCAST_(1) << 17)
437#define CONF_EW (_ULCAST_(3) << 18)
438#define CONF_EP (_ULCAST_(15)<< 24)
439#define CONF_EC (_ULCAST_(7) << 28)
440#define CONF_CM (_ULCAST_(1) << 31)
441
442/* Bits specific to the R4xx0. */
443#define R4K_CONF_SW (_ULCAST_(1) << 20)
444#define R4K_CONF_SS (_ULCAST_(1) << 21)
Ralf Baechlee20368d2005-06-21 13:52:33 +0000445#define R4K_CONF_SB (_ULCAST_(3) << 22)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446
447/* Bits specific to the R5000. */
448#define R5K_CONF_SE (_ULCAST_(1) << 12)
449#define R5K_CONF_SS (_ULCAST_(3) << 20)
450
Thiemo Seuferba5187d2005-04-25 16:36:23 +0000451/* Bits specific to the RM7000. */
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000452#define RM7K_CONF_SE (_ULCAST_(1) << 3)
453#define RM7K_CONF_TE (_ULCAST_(1) << 12)
454#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
455#define RM7K_CONF_TC (_ULCAST_(1) << 17)
456#define RM7K_CONF_SI (_ULCAST_(3) << 20)
457#define RM7K_CONF_SC (_ULCAST_(1) << 31)
Thiemo Seuferba5187d2005-04-25 16:36:23 +0000458
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459/* Bits specific to the R10000. */
460#define R10K_CONF_DN (_ULCAST_(3) << 3)
461#define R10K_CONF_CT (_ULCAST_(1) << 5)
462#define R10K_CONF_PE (_ULCAST_(1) << 6)
463#define R10K_CONF_PM (_ULCAST_(3) << 7)
464#define R10K_CONF_EC (_ULCAST_(15)<< 9)
465#define R10K_CONF_SB (_ULCAST_(1) << 13)
466#define R10K_CONF_SK (_ULCAST_(1) << 14)
467#define R10K_CONF_SS (_ULCAST_(7) << 16)
468#define R10K_CONF_SC (_ULCAST_(7) << 19)
469#define R10K_CONF_DC (_ULCAST_(7) << 26)
470#define R10K_CONF_IC (_ULCAST_(7) << 29)
471
472/* Bits specific to the VR41xx. */
473#define VR41_CONF_CS (_ULCAST_(1) << 12)
474#define VR41_CONF_M16 (_ULCAST_(1) << 20)
475#define VR41_CONF_AD (_ULCAST_(1) << 23)
476
477/* Bits specific to the R30xx. */
478#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
479#define R30XX_CONF_REV (_ULCAST_(1) << 22)
480#define R30XX_CONF_AC (_ULCAST_(1) << 23)
481#define R30XX_CONF_RF (_ULCAST_(1) << 24)
482#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
483#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
484#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
485#define R30XX_CONF_SB (_ULCAST_(1) << 30)
486#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
487
488/* Bits specific to the TX49. */
489#define TX49_CONF_DC (_ULCAST_(1) << 16)
490#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
491#define TX49_CONF_HALT (_ULCAST_(1) << 18)
492#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
493
494/* Bits specific to the MIPS32/64 PRA. */
495#define MIPS_CONF_MT (_ULCAST_(7) << 7)
496#define MIPS_CONF_AR (_ULCAST_(7) << 10)
497#define MIPS_CONF_AT (_ULCAST_(3) << 13)
498#define MIPS_CONF_M (_ULCAST_(1) << 31)
499
500/*
Ralf Baechle41943182005-05-05 16:45:59 +0000501 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
502 */
503#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
504#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
505#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
506#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
507#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
508#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
509#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
510#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
511#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
512#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
513#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
514#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
515#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
516#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
517
518#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
519#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
520#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
521#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
522#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
523#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
524#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
525#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
526
527#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
528#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
529#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
530#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
531#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
532#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +0000533#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
Ralf Baechle41943182005-05-05 16:45:59 +0000534
535/*
536 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
537 */
538#define MIPS_FPIR_S (_ULCAST_(1) << 16)
539#define MIPS_FPIR_D (_ULCAST_(1) << 17)
540#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
541#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
542#define MIPS_FPIR_W (_ULCAST_(1) << 20)
543#define MIPS_FPIR_L (_ULCAST_(1) << 21)
544#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
545
546/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 * R10000 performance counter definitions.
548 *
549 * FIXME: The R10000 performance counter opens a nice way to implement CPU
550 * time accounting with a precission of one cycle. I don't have
551 * R10000 silicon but just a manual, so ...
552 */
553
554/*
555 * Events counted by counter #0
556 */
557#define CE0_CYCLES 0
558#define CE0_INSN_ISSUED 1
559#define CE0_LPSC_ISSUED 2
560#define CE0_S_ISSUED 3
561#define CE0_SC_ISSUED 4
562#define CE0_SC_FAILED 5
563#define CE0_BRANCH_DECODED 6
564#define CE0_QW_WB_SECONDARY 7
565#define CE0_CORRECTED_ECC_ERRORS 8
566#define CE0_ICACHE_MISSES 9
567#define CE0_SCACHE_I_MISSES 10
568#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
569#define CE0_EXT_INTERVENTIONS_REQ 12
570#define CE0_EXT_INVALIDATE_REQ 13
571#define CE0_VIRTUAL_COHERENCY_COND 14
572#define CE0_INSN_GRADUATED 15
573
574/*
575 * Events counted by counter #1
576 */
577#define CE1_CYCLES 0
578#define CE1_INSN_GRADUATED 1
579#define CE1_LPSC_GRADUATED 2
580#define CE1_S_GRADUATED 3
581#define CE1_SC_GRADUATED 4
582#define CE1_FP_INSN_GRADUATED 5
583#define CE1_QW_WB_PRIMARY 6
584#define CE1_TLB_REFILL 7
585#define CE1_BRANCH_MISSPREDICTED 8
586#define CE1_DCACHE_MISS 9
587#define CE1_SCACHE_D_MISSES 10
588#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
589#define CE1_EXT_INTERVENTION_HITS 12
590#define CE1_EXT_INVALIDATE_REQ 13
591#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
592#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
593
594/*
595 * These flags define in which privilege mode the counters count events
596 */
597#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
598#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
599#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
600#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
601
602#ifndef __ASSEMBLY__
603
604/*
605 * Functions to access the R10000 performance counters. These are basically
606 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
607 * performance counter number encoded into bits 1 ... 5 of the instruction.
608 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
609 * disassembler these will look like an access to sel 0 or 1.
610 */
611#define read_r10k_perf_cntr(counter) \
612({ \
613 unsigned int __res; \
614 __asm__ __volatile__( \
615 "mfpc\t%0, %1" \
616 : "=r" (__res) \
617 : "i" (counter)); \
618 \
619 __res; \
620})
621
622#define write_r10k_perf_cntr(counter,val) \
623do { \
624 __asm__ __volatile__( \
625 "mtpc\t%0, %1" \
626 : \
627 : "r" (val), "i" (counter)); \
628} while (0)
629
630#define read_r10k_perf_event(counter) \
631({ \
632 unsigned int __res; \
633 __asm__ __volatile__( \
634 "mfps\t%0, %1" \
635 : "=r" (__res) \
636 : "i" (counter)); \
637 \
638 __res; \
639})
640
641#define write_r10k_perf_cntl(counter,val) \
642do { \
643 __asm__ __volatile__( \
644 "mtps\t%0, %1" \
645 : \
646 : "r" (val), "i" (counter)); \
647} while (0)
648
649
650/*
651 * Macros to access the system control coprocessor
652 */
653
654#define __read_32bit_c0_register(source, sel) \
655({ int __res; \
656 if (sel == 0) \
657 __asm__ __volatile__( \
658 "mfc0\t%0, " #source "\n\t" \
659 : "=r" (__res)); \
660 else \
661 __asm__ __volatile__( \
662 ".set\tmips32\n\t" \
663 "mfc0\t%0, " #source ", " #sel "\n\t" \
664 ".set\tmips0\n\t" \
665 : "=r" (__res)); \
666 __res; \
667})
668
669#define __read_64bit_c0_register(source, sel) \
670({ unsigned long long __res; \
671 if (sizeof(unsigned long) == 4) \
672 __res = __read_64bit_c0_split(source, sel); \
673 else if (sel == 0) \
674 __asm__ __volatile__( \
675 ".set\tmips3\n\t" \
676 "dmfc0\t%0, " #source "\n\t" \
677 ".set\tmips0" \
678 : "=r" (__res)); \
679 else \
680 __asm__ __volatile__( \
681 ".set\tmips64\n\t" \
682 "dmfc0\t%0, " #source ", " #sel "\n\t" \
683 ".set\tmips0" \
684 : "=r" (__res)); \
685 __res; \
686})
687
688#define __write_32bit_c0_register(register, sel, value) \
689do { \
690 if (sel == 0) \
691 __asm__ __volatile__( \
692 "mtc0\t%z0, " #register "\n\t" \
693 : : "Jr" ((unsigned int)value)); \
694 else \
695 __asm__ __volatile__( \
696 ".set\tmips32\n\t" \
697 "mtc0\t%z0, " #register ", " #sel "\n\t" \
698 ".set\tmips0" \
699 : : "Jr" ((unsigned int)value)); \
700} while (0)
701
702#define __write_64bit_c0_register(register, sel, value) \
703do { \
704 if (sizeof(unsigned long) == 4) \
705 __write_64bit_c0_split(register, sel, value); \
706 else if (sel == 0) \
707 __asm__ __volatile__( \
708 ".set\tmips3\n\t" \
709 "dmtc0\t%z0, " #register "\n\t" \
710 ".set\tmips0" \
711 : : "Jr" (value)); \
712 else \
713 __asm__ __volatile__( \
714 ".set\tmips64\n\t" \
715 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
716 ".set\tmips0" \
717 : : "Jr" (value)); \
718} while (0)
719
720#define __read_ulong_c0_register(reg, sel) \
721 ((sizeof(unsigned long) == 4) ? \
722 (unsigned long) __read_32bit_c0_register(reg, sel) : \
723 (unsigned long) __read_64bit_c0_register(reg, sel))
724
725#define __write_ulong_c0_register(reg, sel, val) \
726do { \
727 if (sizeof(unsigned long) == 4) \
728 __write_32bit_c0_register(reg, sel, val); \
729 else \
730 __write_64bit_c0_register(reg, sel, val); \
731} while (0)
732
733/*
734 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
735 */
736#define __read_32bit_c0_ctrl_register(source) \
737({ int __res; \
738 __asm__ __volatile__( \
739 "cfc0\t%0, " #source "\n\t" \
740 : "=r" (__res)); \
741 __res; \
742})
743
744#define __write_32bit_c0_ctrl_register(register, value) \
745do { \
746 __asm__ __volatile__( \
747 "ctc0\t%z0, " #register "\n\t" \
748 : : "Jr" ((unsigned int)value)); \
749} while (0)
750
751/*
752 * These versions are only needed for systems with more than 38 bits of
753 * physical address space running the 32-bit kernel. That's none atm :-)
754 */
755#define __read_64bit_c0_split(source, sel) \
756({ \
757 unsigned long long val; \
758 unsigned long flags; \
759 \
760 local_irq_save(flags); \
761 if (sel == 0) \
762 __asm__ __volatile__( \
763 ".set\tmips64\n\t" \
764 "dmfc0\t%M0, " #source "\n\t" \
765 "dsll\t%L0, %M0, 32\n\t" \
766 "dsrl\t%M0, %M0, 32\n\t" \
767 "dsrl\t%L0, %L0, 32\n\t" \
768 ".set\tmips0" \
769 : "=r" (val)); \
770 else \
771 __asm__ __volatile__( \
772 ".set\tmips64\n\t" \
773 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
774 "dsll\t%L0, %M0, 32\n\t" \
775 "dsrl\t%M0, %M0, 32\n\t" \
776 "dsrl\t%L0, %L0, 32\n\t" \
777 ".set\tmips0" \
778 : "=r" (val)); \
779 local_irq_restore(flags); \
780 \
781 val; \
782})
783
784#define __write_64bit_c0_split(source, sel, val) \
785do { \
786 unsigned long flags; \
787 \
788 local_irq_save(flags); \
789 if (sel == 0) \
790 __asm__ __volatile__( \
791 ".set\tmips64\n\t" \
792 "dsll\t%L0, %L0, 32\n\t" \
793 "dsrl\t%L0, %L0, 32\n\t" \
794 "dsll\t%M0, %M0, 32\n\t" \
795 "or\t%L0, %L0, %M0\n\t" \
796 "dmtc0\t%L0, " #source "\n\t" \
797 ".set\tmips0" \
798 : : "r" (val)); \
799 else \
800 __asm__ __volatile__( \
801 ".set\tmips64\n\t" \
802 "dsll\t%L0, %L0, 32\n\t" \
803 "dsrl\t%L0, %L0, 32\n\t" \
804 "dsll\t%M0, %M0, 32\n\t" \
805 "or\t%L0, %L0, %M0\n\t" \
806 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
807 ".set\tmips0" \
808 : : "r" (val)); \
809 local_irq_restore(flags); \
810} while (0)
811
812#define read_c0_index() __read_32bit_c0_register($0, 0)
813#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
814
815#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
816#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
817
818#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
819#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
820
821#define read_c0_conf() __read_32bit_c0_register($3, 0)
822#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
823
824#define read_c0_context() __read_ulong_c0_register($4, 0)
825#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
826
827#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
828#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
829
830#define read_c0_wired() __read_32bit_c0_register($6, 0)
831#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
832
833#define read_c0_info() __read_32bit_c0_register($7, 0)
834
835#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
836#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
837
838#define read_c0_count() __read_32bit_c0_register($9, 0)
839#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
840
841#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
842#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
843
844#define read_c0_compare() __read_32bit_c0_register($11, 0)
845#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
846
847#define read_c0_status() __read_32bit_c0_register($12, 0)
848#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
849
850#define read_c0_cause() __read_32bit_c0_register($13, 0)
851#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
852
853#define read_c0_epc() __read_ulong_c0_register($14, 0)
854#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
855
856#define read_c0_prid() __read_32bit_c0_register($15, 0)
857
858#define read_c0_config() __read_32bit_c0_register($16, 0)
859#define read_c0_config1() __read_32bit_c0_register($16, 1)
860#define read_c0_config2() __read_32bit_c0_register($16, 2)
861#define read_c0_config3() __read_32bit_c0_register($16, 3)
Ralf Baechle0efe2762005-02-06 21:24:55 +0000862#define read_c0_config4() __read_32bit_c0_register($16, 4)
863#define read_c0_config5() __read_32bit_c0_register($16, 5)
864#define read_c0_config6() __read_32bit_c0_register($16, 6)
865#define read_c0_config7() __read_32bit_c0_register($16, 7)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
867#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
868#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
869#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
Ralf Baechle0efe2762005-02-06 21:24:55 +0000870#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
871#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
872#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
873#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874
875/*
876 * The WatchLo register. There may be upto 8 of them.
877 */
878#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
879#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
880#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
881#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
882#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
883#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
884#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
885#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
886#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
887#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
888#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
889#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
890#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
891#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
892#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
893#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
894
895/*
896 * The WatchHi register. There may be upto 8 of them.
897 */
898#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
899#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
900#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
901#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
902#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
903#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
904#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
905#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
906
907#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
908#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
909#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
910#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
911#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
912#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
913#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
914#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
915
916#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
917#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
918
919#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
920#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
921
922#define read_c0_framemask() __read_32bit_c0_register($21, 0)
923#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
924
925/* RM9000 PerfControl performance counter control register */
926#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
927#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
928
929#define read_c0_diag() __read_32bit_c0_register($22, 0)
930#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
931
932#define read_c0_diag1() __read_32bit_c0_register($22, 1)
933#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
934
935#define read_c0_diag2() __read_32bit_c0_register($22, 2)
936#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
937
938#define read_c0_diag3() __read_32bit_c0_register($22, 3)
939#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
940
941#define read_c0_diag4() __read_32bit_c0_register($22, 4)
942#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
943
944#define read_c0_diag5() __read_32bit_c0_register($22, 5)
945#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
946
947#define read_c0_debug() __read_32bit_c0_register($23, 0)
948#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
949
950#define read_c0_depc() __read_ulong_c0_register($24, 0)
951#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
952
953/*
954 * MIPS32 / MIPS64 performance counters
955 */
956#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
957#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
958#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
959#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
960#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
961#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
962#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
963#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
964#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
965#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
966#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
967#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
968#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
969#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
970#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
971#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
972
973/* RM9000 PerfCount performance counter register */
974#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
975#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
976
977#define read_c0_ecc() __read_32bit_c0_register($26, 0)
978#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
979
980#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
981#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
982
983#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
984
985#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
986#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
987
988#define read_c0_taglo() __read_32bit_c0_register($28, 0)
989#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
990
991#define read_c0_taghi() __read_32bit_c0_register($29, 0)
992#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
993
994#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
995#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
996
Ralf Baechle7a0fc582005-07-13 19:47:28 +0000997/* MIPSR2 */
998#define read_c0_hwrena() __read_32bit_c0_register($7,0)
999#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1000
1001#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1002#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1003
1004#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1005#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1006
1007#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1008#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1009
1010#define read_c0_ebase() __read_32bit_c0_register($15,1)
1011#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1012
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013/*
1014 * Macros to access the floating point coprocessor control registers
1015 */
1016#define read_32bit_cp1_register(source) \
1017({ int __res; \
1018 __asm__ __volatile__( \
1019 ".set\tpush\n\t" \
1020 ".set\treorder\n\t" \
1021 "cfc1\t%0,"STR(source)"\n\t" \
1022 ".set\tpop" \
1023 : "=r" (__res)); \
1024 __res;})
1025
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001026#define rddsp(mask) \
1027({ \
1028 unsigned int __res; \
1029 \
1030 __asm__ __volatile__( \
1031 " .set push \n" \
1032 " .set noat \n" \
1033 " # rddsp $1, %x1 \n" \
1034 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1035 " move %0, $1 \n" \
1036 " .set pop \n" \
1037 : "=r" (__res) \
1038 : "i" (mask)); \
1039 __res; \
1040})
1041
1042#define wrdsp(val, mask) \
1043do { \
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001044 __asm__ __volatile__( \
1045 " .set push \n" \
1046 " .set noat \n" \
1047 " move $1, %0 \n" \
1048 " # wrdsp $1, %x1 \n" \
1049 " .word 0x7c2004f8 | (%x1 << 15) \n" \
1050 " .set pop \n" \
1051 : \
1052 : "r" (val), "i" (mask)); \
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001053} while (0)
1054
1055#if 0 /* Need DSP ASE capable assembler ... */
1056#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1057#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1058#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1059#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1060
1061#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1062#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1063#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1064#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1065
1066#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1067#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1068#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1069#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1070
1071#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1072#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1073#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1074#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1075
1076#else
1077
1078#define mfhi0() \
1079({ \
1080 unsigned long __treg; \
1081 \
1082 __asm__ __volatile__( \
1083 " .set push \n" \
1084 " .set noat \n" \
1085 " # mfhi %0, $ac0 \n" \
1086 " .word 0x00000810 \n" \
1087 " move %0, $1 \n" \
1088 " .set pop \n" \
1089 : "=r" (__treg)); \
1090 __treg; \
1091})
1092
1093#define mfhi1() \
1094({ \
1095 unsigned long __treg; \
1096 \
1097 __asm__ __volatile__( \
1098 " .set push \n" \
1099 " .set noat \n" \
1100 " # mfhi %0, $ac1 \n" \
1101 " .word 0x00200810 \n" \
1102 " move %0, $1 \n" \
1103 " .set pop \n" \
1104 : "=r" (__treg)); \
1105 __treg; \
1106})
1107
1108#define mfhi2() \
1109({ \
1110 unsigned long __treg; \
1111 \
1112 __asm__ __volatile__( \
1113 " .set push \n" \
1114 " .set noat \n" \
1115 " # mfhi %0, $ac2 \n" \
1116 " .word 0x00400810 \n" \
1117 " move %0, $1 \n" \
1118 " .set pop \n" \
1119 : "=r" (__treg)); \
1120 __treg; \
1121})
1122
1123#define mfhi3() \
1124({ \
1125 unsigned long __treg; \
1126 \
1127 __asm__ __volatile__( \
1128 " .set push \n" \
1129 " .set noat \n" \
1130 " # mfhi %0, $ac3 \n" \
1131 " .word 0x00600810 \n" \
1132 " move %0, $1 \n" \
1133 " .set pop \n" \
1134 : "=r" (__treg)); \
1135 __treg; \
1136})
1137
1138#define mflo0() \
1139({ \
1140 unsigned long __treg; \
1141 \
1142 __asm__ __volatile__( \
1143 " .set push \n" \
1144 " .set noat \n" \
1145 " # mflo %0, $ac0 \n" \
1146 " .word 0x00000812 \n" \
1147 " move %0, $1 \n" \
1148 " .set pop \n" \
1149 : "=r" (__treg)); \
1150 __treg; \
1151})
1152
1153#define mflo1() \
1154({ \
1155 unsigned long __treg; \
1156 \
1157 __asm__ __volatile__( \
1158 " .set push \n" \
1159 " .set noat \n" \
1160 " # mflo %0, $ac1 \n" \
1161 " .word 0x00200812 \n" \
1162 " move %0, $1 \n" \
1163 " .set pop \n" \
1164 : "=r" (__treg)); \
1165 __treg; \
1166})
1167
1168#define mflo2() \
1169({ \
1170 unsigned long __treg; \
1171 \
1172 __asm__ __volatile__( \
1173 " .set push \n" \
1174 " .set noat \n" \
1175 " # mflo %0, $ac2 \n" \
1176 " .word 0x00400812 \n" \
1177 " move %0, $1 \n" \
1178 " .set pop \n" \
1179 : "=r" (__treg)); \
1180 __treg; \
1181})
1182
1183#define mflo3() \
1184({ \
1185 unsigned long __treg; \
1186 \
1187 __asm__ __volatile__( \
1188 " .set push \n" \
1189 " .set noat \n" \
1190 " # mflo %0, $ac3 \n" \
1191 " .word 0x00600812 \n" \
1192 " move %0, $1 \n" \
1193 " .set pop \n" \
1194 : "=r" (__treg)); \
1195 __treg; \
1196})
1197
1198#define mthi0(x) \
1199do { \
1200 __asm__ __volatile__( \
1201 " .set push \n" \
1202 " .set noat \n" \
1203 " move $1, %0 \n" \
1204 " # mthi $1, $ac0 \n" \
1205 " .word 0x00200011 \n" \
1206 " .set pop \n" \
1207 : \
1208 : "r" (x)); \
1209} while (0)
1210
1211#define mthi1(x) \
1212do { \
1213 __asm__ __volatile__( \
1214 " .set push \n" \
1215 " .set noat \n" \
1216 " move $1, %0 \n" \
1217 " # mthi $1, $ac1 \n" \
1218 " .word 0x00200811 \n" \
1219 " .set pop \n" \
1220 : \
1221 : "r" (x)); \
1222} while (0)
1223
1224#define mthi2(x) \
1225do { \
1226 __asm__ __volatile__( \
1227 " .set push \n" \
1228 " .set noat \n" \
1229 " move $1, %0 \n" \
1230 " # mthi $1, $ac2 \n" \
1231 " .word 0x00201011 \n" \
1232 " .set pop \n" \
1233 : \
1234 : "r" (x)); \
1235} while (0)
1236
1237#define mthi3(x) \
1238do { \
1239 __asm__ __volatile__( \
1240 " .set push \n" \
1241 " .set noat \n" \
1242 " move $1, %0 \n" \
1243 " # mthi $1, $ac3 \n" \
1244 " .word 0x00201811 \n" \
1245 " .set pop \n" \
1246 : \
1247 : "r" (x)); \
1248} while (0)
1249
1250#define mtlo0(x) \
1251do { \
1252 __asm__ __volatile__( \
1253 " .set push \n" \
1254 " .set noat \n" \
1255 " move $1, %0 \n" \
1256 " # mtlo $1, $ac0 \n" \
1257 " .word 0x00200013 \n" \
1258 " .set pop \n" \
1259 : \
1260 : "r" (x)); \
1261} while (0)
1262
1263#define mtlo1(x) \
1264do { \
1265 __asm__ __volatile__( \
1266 " .set push \n" \
1267 " .set noat \n" \
1268 " move $1, %0 \n" \
1269 " # mtlo $1, $ac1 \n" \
1270 " .word 0x00200813 \n" \
1271 " .set pop \n" \
1272 : \
1273 : "r" (x)); \
1274} while (0)
1275
1276#define mtlo2(x) \
1277do { \
1278 __asm__ __volatile__( \
1279 " .set push \n" \
1280 " .set noat \n" \
1281 " move $1, %0 \n" \
1282 " # mtlo $1, $ac2 \n" \
1283 " .word 0x00201013 \n" \
1284 " .set pop \n" \
1285 : \
1286 : "r" (x)); \
1287} while (0)
1288
1289#define mtlo3(x) \
1290do { \
1291 __asm__ __volatile__( \
1292 " .set push \n" \
1293 " .set noat \n" \
1294 " move $1, %0 \n" \
1295 " # mtlo $1, $ac3 \n" \
1296 " .word 0x00201813 \n" \
1297 " .set pop \n" \
1298 : \
1299 : "r" (x)); \
1300} while (0)
1301
1302#endif
1303
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304/*
1305 * TLB operations.
1306 *
1307 * It is responsibility of the caller to take care of any TLB hazards.
1308 */
1309static inline void tlb_probe(void)
1310{
1311 __asm__ __volatile__(
1312 ".set noreorder\n\t"
1313 "tlbp\n\t"
1314 ".set reorder");
1315}
1316
1317static inline void tlb_read(void)
1318{
1319 __asm__ __volatile__(
1320 ".set noreorder\n\t"
1321 "tlbr\n\t"
1322 ".set reorder");
1323}
1324
1325static inline void tlb_write_indexed(void)
1326{
1327 __asm__ __volatile__(
1328 ".set noreorder\n\t"
1329 "tlbwi\n\t"
1330 ".set reorder");
1331}
1332
1333static inline void tlb_write_random(void)
1334{
1335 __asm__ __volatile__(
1336 ".set noreorder\n\t"
1337 "tlbwr\n\t"
1338 ".set reorder");
1339}
1340
1341/*
1342 * Manipulate bits in a c0 register.
1343 */
1344#define __BUILD_SET_C0(name) \
1345static inline unsigned int \
1346set_c0_##name(unsigned int set) \
1347{ \
1348 unsigned int res; \
1349 \
1350 res = read_c0_##name(); \
1351 res |= set; \
1352 write_c0_##name(res); \
1353 \
1354 return res; \
1355} \
1356 \
1357static inline unsigned int \
1358clear_c0_##name(unsigned int clear) \
1359{ \
1360 unsigned int res; \
1361 \
1362 res = read_c0_##name(); \
1363 res &= ~clear; \
1364 write_c0_##name(res); \
1365 \
1366 return res; \
1367} \
1368 \
1369static inline unsigned int \
1370change_c0_##name(unsigned int change, unsigned int new) \
1371{ \
1372 unsigned int res; \
1373 \
1374 res = read_c0_##name(); \
1375 res &= ~change; \
1376 res |= (new & change); \
1377 write_c0_##name(res); \
1378 \
1379 return res; \
1380}
1381
1382__BUILD_SET_C0(status)
1383__BUILD_SET_C0(cause)
1384__BUILD_SET_C0(config)
1385__BUILD_SET_C0(intcontrol)
Ralf Baechle7a0fc582005-07-13 19:47:28 +00001386__BUILD_SET_C0(intctl)
1387__BUILD_SET_C0(srsmap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388
1389#endif /* !__ASSEMBLY__ */
1390
1391#endif /* _ASM_MIPSREGS_H */