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Jamie Iles1b8873a2010-02-02 20:25:44 +01001#undef DEBUG
2
3/*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
Will Deacon43eab872010-11-13 19:04:32 +00007 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
Jean PIHET796d1292010-01-26 18:51:05 +01008 *
Jamie Iles1b8873a2010-02-02 20:25:44 +01009 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
11 * code.
12 */
13#define pr_fmt(fmt) "hw perfevents: " fmt
14
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
Will Deacon181193f2010-04-30 11:32:44 +010017#include <linux/module.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010018#include <linux/perf_event.h>
Will Deacon49c006b2010-04-29 17:13:24 +010019#include <linux/platform_device.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010020#include <linux/spinlock.h>
21#include <linux/uaccess.h>
22
23#include <asm/cputype.h>
24#include <asm/irq.h>
25#include <asm/irq_regs.h>
26#include <asm/pmu.h>
27#include <asm/stacktrace.h>
28
Will Deacon49c006b2010-04-29 17:13:24 +010029static struct platform_device *pmu_device;
Jamie Iles1b8873a2010-02-02 20:25:44 +010030
31/*
32 * Hardware lock to serialize accesses to PMU registers. Needed for the
33 * read/modify/write sequences.
34 */
Will Deacon961ec6da2010-12-02 18:01:49 +010035static DEFINE_RAW_SPINLOCK(pmu_lock);
Jamie Iles1b8873a2010-02-02 20:25:44 +010036
37/*
Will Deaconecf5a892011-07-19 22:43:28 +010038 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
Jamie Iles1b8873a2010-02-02 20:25:44 +010039 * another platform that supports more, we need to increase this to be the
40 * largest of all platforms.
Jean PIHET796d1292010-01-26 18:51:05 +010041 *
42 * ARMv7 supports up to 32 events:
43 * cycle counter CCNT + 31 events counters CNT0..30.
44 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
Jamie Iles1b8873a2010-02-02 20:25:44 +010045 */
Will Deaconecf5a892011-07-19 22:43:28 +010046#define ARMPMU_MAX_HWEVENTS 32
Jamie Iles1b8873a2010-02-02 20:25:44 +010047
48/* The events for a given CPU. */
49struct cpu_hw_events {
50 /*
Will Deaconecf5a892011-07-19 22:43:28 +010051 * The events that are active on the CPU for the given index.
Jamie Iles1b8873a2010-02-02 20:25:44 +010052 */
53 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
54
55 /*
56 * A 1 bit for an index indicates that the counter is being used for
57 * an event. A 0 means that the counter can be used.
58 */
59 unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
60
61 /*
62 * A 1 bit for an index indicates that the counter is actively being
63 * used.
64 */
65 unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
66};
Will Deacon4d6b7a72010-11-30 18:15:53 +010067static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
Will Deacon181193f2010-04-30 11:32:44 +010068
Jamie Iles1b8873a2010-02-02 20:25:44 +010069struct arm_pmu {
Will Deacon181193f2010-04-30 11:32:44 +010070 enum arm_perf_pmu_ids id;
Will Deacon0b390e22011-07-27 15:18:59 +010071 cpumask_t active_irqs;
Will Deacon62994832010-11-13 18:45:27 +000072 const char *name;
Jamie Iles1b8873a2010-02-02 20:25:44 +010073 irqreturn_t (*handle_irq)(int irq_num, void *dev);
74 void (*enable)(struct hw_perf_event *evt, int idx);
75 void (*disable)(struct hw_perf_event *evt, int idx);
Jamie Iles1b8873a2010-02-02 20:25:44 +010076 int (*get_event_idx)(struct cpu_hw_events *cpuc,
77 struct hw_perf_event *hwc);
Will Deacon05d22fd2011-07-19 11:57:30 +010078 int (*set_event_filter)(struct hw_perf_event *evt,
79 struct perf_event_attr *attr);
Jamie Iles1b8873a2010-02-02 20:25:44 +010080 u32 (*read_counter)(int idx);
81 void (*write_counter)(int idx, u32 val);
82 void (*start)(void);
83 void (*stop)(void);
Will Deacon574b69c2011-03-25 13:13:34 +010084 void (*reset)(void *);
Will Deacon84fee972010-11-13 17:13:56 +000085 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
86 [PERF_COUNT_HW_CACHE_OP_MAX]
87 [PERF_COUNT_HW_CACHE_RESULT_MAX];
88 const unsigned (*event_map)[PERF_COUNT_HW_MAX];
89 u32 raw_event_mask;
Jamie Iles1b8873a2010-02-02 20:25:44 +010090 int num_events;
91 u64 max_period;
92};
93
94/* Set at runtime when we know what CPU type we are. */
Mark Rutlanda6c93af2011-04-15 11:14:38 +010095static struct arm_pmu *armpmu;
Jamie Iles1b8873a2010-02-02 20:25:44 +010096
Will Deacon181193f2010-04-30 11:32:44 +010097enum arm_perf_pmu_ids
98armpmu_get_pmu_id(void)
99{
100 int id = -ENODEV;
101
102 if (armpmu != NULL)
103 id = armpmu->id;
104
105 return id;
106}
107EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
108
Will Deacon929f5192010-04-30 11:34:26 +0100109int
110armpmu_get_max_events(void)
111{
112 int max_events = 0;
113
114 if (armpmu != NULL)
115 max_events = armpmu->num_events;
116
117 return max_events;
118}
119EXPORT_SYMBOL_GPL(armpmu_get_max_events);
120
Matt Fleming3bf101b2010-09-27 20:22:24 +0100121int perf_num_counters(void)
122{
123 return armpmu_get_max_events();
124}
125EXPORT_SYMBOL_GPL(perf_num_counters);
126
Jamie Iles1b8873a2010-02-02 20:25:44 +0100127#define HW_OP_UNSUPPORTED 0xFFFF
128
129#define C(_x) \
130 PERF_COUNT_HW_CACHE_##_x
131
132#define CACHE_OP_UNSUPPORTED 0xFFFF
133
Jamie Iles1b8873a2010-02-02 20:25:44 +0100134static int
135armpmu_map_cache_event(u64 config)
136{
137 unsigned int cache_type, cache_op, cache_result, ret;
138
139 cache_type = (config >> 0) & 0xff;
140 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
141 return -EINVAL;
142
143 cache_op = (config >> 8) & 0xff;
144 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
145 return -EINVAL;
146
147 cache_result = (config >> 16) & 0xff;
148 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
149 return -EINVAL;
150
Will Deacon84fee972010-11-13 17:13:56 +0000151 ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
Jamie Iles1b8873a2010-02-02 20:25:44 +0100152
153 if (ret == CACHE_OP_UNSUPPORTED)
154 return -ENOENT;
155
156 return ret;
157}
158
159static int
Will Deacon84fee972010-11-13 17:13:56 +0000160armpmu_map_event(u64 config)
161{
162 int mapping = (*armpmu->event_map)[config];
163 return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
164}
165
166static int
167armpmu_map_raw_event(u64 config)
168{
169 return (int)(config & armpmu->raw_event_mask);
170}
171
172static int
Jamie Iles1b8873a2010-02-02 20:25:44 +0100173armpmu_event_set_period(struct perf_event *event,
174 struct hw_perf_event *hwc,
175 int idx)
176{
Peter Zijlstrae7850592010-05-21 14:43:08 +0200177 s64 left = local64_read(&hwc->period_left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100178 s64 period = hwc->sample_period;
179 int ret = 0;
180
181 if (unlikely(left <= -period)) {
182 left = period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200183 local64_set(&hwc->period_left, left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100184 hwc->last_period = period;
185 ret = 1;
186 }
187
188 if (unlikely(left <= 0)) {
189 left += period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200190 local64_set(&hwc->period_left, left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100191 hwc->last_period = period;
192 ret = 1;
193 }
194
195 if (left > (s64)armpmu->max_period)
196 left = armpmu->max_period;
197
Peter Zijlstrae7850592010-05-21 14:43:08 +0200198 local64_set(&hwc->prev_count, (u64)-left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100199
200 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
201
202 perf_event_update_userpage(event);
203
204 return ret;
205}
206
207static u64
208armpmu_event_update(struct perf_event *event,
209 struct hw_perf_event *hwc,
Will Deacona7378232011-03-25 17:12:37 +0100210 int idx, int overflow)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100211{
Will Deacona7378232011-03-25 17:12:37 +0100212 u64 delta, prev_raw_count, new_raw_count;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100213
214again:
Peter Zijlstrae7850592010-05-21 14:43:08 +0200215 prev_raw_count = local64_read(&hwc->prev_count);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100216 new_raw_count = armpmu->read_counter(idx);
217
Peter Zijlstrae7850592010-05-21 14:43:08 +0200218 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
Jamie Iles1b8873a2010-02-02 20:25:44 +0100219 new_raw_count) != prev_raw_count)
220 goto again;
221
Will Deacona7378232011-03-25 17:12:37 +0100222 new_raw_count &= armpmu->max_period;
223 prev_raw_count &= armpmu->max_period;
224
225 if (overflow)
Will Deacon67597882011-04-05 14:01:24 +0100226 delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
Will Deacona7378232011-03-25 17:12:37 +0100227 else
228 delta = new_raw_count - prev_raw_count;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100229
Peter Zijlstrae7850592010-05-21 14:43:08 +0200230 local64_add(delta, &event->count);
231 local64_sub(delta, &hwc->period_left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100232
233 return new_raw_count;
234}
235
236static void
Jamie Iles1b8873a2010-02-02 20:25:44 +0100237armpmu_read(struct perf_event *event)
238{
239 struct hw_perf_event *hwc = &event->hw;
240
241 /* Don't read disabled counters! */
242 if (hwc->idx < 0)
243 return;
244
Will Deacona7378232011-03-25 17:12:37 +0100245 armpmu_event_update(event, hwc, hwc->idx, 0);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100246}
247
248static void
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200249armpmu_stop(struct perf_event *event, int flags)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100250{
251 struct hw_perf_event *hwc = &event->hw;
252
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200253 /*
254 * ARM pmu always has to update the counter, so ignore
255 * PERF_EF_UPDATE, see comments in armpmu_start().
256 */
257 if (!(hwc->state & PERF_HES_STOPPED)) {
258 armpmu->disable(hwc, hwc->idx);
259 barrier(); /* why? */
Will Deacona7378232011-03-25 17:12:37 +0100260 armpmu_event_update(event, hwc, hwc->idx, 0);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200261 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
262 }
263}
264
265static void
266armpmu_start(struct perf_event *event, int flags)
267{
268 struct hw_perf_event *hwc = &event->hw;
269
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200270 /*
271 * ARM pmu always has to reprogram the period, so ignore
272 * PERF_EF_RELOAD, see the comment below.
273 */
274 if (flags & PERF_EF_RELOAD)
275 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
276
277 hwc->state = 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100278 /*
279 * Set the period again. Some counters can't be stopped, so when we
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200280 * were stopped we simply disabled the IRQ source and the counter
Jamie Iles1b8873a2010-02-02 20:25:44 +0100281 * may have been left counting. If we don't do this step then we may
282 * get an interrupt too soon or *way* too late if the overflow has
283 * happened since disabling.
284 */
285 armpmu_event_set_period(event, hwc, hwc->idx);
286 armpmu->enable(hwc, hwc->idx);
287}
288
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200289static void
290armpmu_del(struct perf_event *event, int flags)
291{
292 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
293 struct hw_perf_event *hwc = &event->hw;
294 int idx = hwc->idx;
295
296 WARN_ON(idx < 0);
297
298 clear_bit(idx, cpuc->active_mask);
299 armpmu_stop(event, PERF_EF_UPDATE);
300 cpuc->events[idx] = NULL;
301 clear_bit(idx, cpuc->used_mask);
302
303 perf_event_update_userpage(event);
304}
305
Jamie Iles1b8873a2010-02-02 20:25:44 +0100306static int
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200307armpmu_add(struct perf_event *event, int flags)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100308{
309 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
310 struct hw_perf_event *hwc = &event->hw;
311 int idx;
312 int err = 0;
313
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200314 perf_pmu_disable(event->pmu);
Peter Zijlstra24cd7f52010-06-11 17:32:03 +0200315
Jamie Iles1b8873a2010-02-02 20:25:44 +0100316 /* If we don't have a space for the counter then finish early. */
317 idx = armpmu->get_event_idx(cpuc, hwc);
318 if (idx < 0) {
319 err = idx;
320 goto out;
321 }
322
323 /*
324 * If there is an event in the counter we are going to use then make
325 * sure it is disabled.
326 */
327 event->hw.idx = idx;
328 armpmu->disable(hwc, idx);
329 cpuc->events[idx] = event;
330 set_bit(idx, cpuc->active_mask);
331
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200332 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
333 if (flags & PERF_EF_START)
334 armpmu_start(event, PERF_EF_RELOAD);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100335
336 /* Propagate our changes to the userspace mapping. */
337 perf_event_update_userpage(event);
338
339out:
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200340 perf_pmu_enable(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100341 return err;
342}
343
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200344static struct pmu pmu;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100345
346static int
347validate_event(struct cpu_hw_events *cpuc,
348 struct perf_event *event)
349{
350 struct hw_perf_event fake_event = event->hw;
Mark Rutland7b9f72c2011-04-27 16:22:21 +0100351 struct pmu *leader_pmu = event->group_leader->pmu;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100352
Mark Rutland7b9f72c2011-04-27 16:22:21 +0100353 if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
Will Deacon65b47112010-09-02 09:32:08 +0100354 return 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100355
356 return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
357}
358
359static int
360validate_group(struct perf_event *event)
361{
362 struct perf_event *sibling, *leader = event->group_leader;
363 struct cpu_hw_events fake_pmu;
364
365 memset(&fake_pmu, 0, sizeof(fake_pmu));
366
367 if (!validate_event(&fake_pmu, leader))
368 return -ENOSPC;
369
370 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
371 if (!validate_event(&fake_pmu, sibling))
372 return -ENOSPC;
373 }
374
375 if (!validate_event(&fake_pmu, event))
376 return -ENOSPC;
377
378 return 0;
379}
380
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530381static irqreturn_t armpmu_platform_irq(int irq, void *dev)
382{
383 struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev);
384
385 return plat->handle_irq(irq, dev, armpmu->handle_irq);
386}
387
Will Deacon0b390e22011-07-27 15:18:59 +0100388static void
389armpmu_release_hardware(void)
390{
391 int i, irq, irqs;
392
393 irqs = min(pmu_device->num_resources, num_possible_cpus());
394
395 for (i = 0; i < irqs; ++i) {
396 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
397 continue;
398 irq = platform_get_irq(pmu_device, i);
399 if (irq >= 0)
400 free_irq(irq, NULL);
401 }
402
403 armpmu->stop();
404 release_pmu(ARM_PMU_DEVICE_CPU);
405}
406
Jamie Iles1b8873a2010-02-02 20:25:44 +0100407static int
408armpmu_reserve_hardware(void)
409{
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530410 struct arm_pmu_platdata *plat;
411 irq_handler_t handle_irq;
Will Deaconb0e89592011-07-26 22:10:28 +0100412 int i, err, irq, irqs;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100413
Will Deaconb0e89592011-07-26 22:10:28 +0100414 err = reserve_pmu(ARM_PMU_DEVICE_CPU);
415 if (err) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100416 pr_warning("unable to reserve pmu\n");
Will Deaconb0e89592011-07-26 22:10:28 +0100417 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100418 }
419
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530420 plat = dev_get_platdata(&pmu_device->dev);
421 if (plat && plat->handle_irq)
422 handle_irq = armpmu_platform_irq;
423 else
424 handle_irq = armpmu->handle_irq;
425
Will Deacon0b390e22011-07-27 15:18:59 +0100426 irqs = min(pmu_device->num_resources, num_possible_cpus());
Will Deaconb0e89592011-07-26 22:10:28 +0100427 if (irqs < 1) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100428 pr_err("no irqs for PMUs defined\n");
429 return -ENODEV;
430 }
431
Will Deaconb0e89592011-07-26 22:10:28 +0100432 for (i = 0; i < irqs; ++i) {
Will Deacon0b390e22011-07-27 15:18:59 +0100433 err = 0;
Will Deacon49c006b2010-04-29 17:13:24 +0100434 irq = platform_get_irq(pmu_device, i);
435 if (irq < 0)
436 continue;
437
Will Deaconb0e89592011-07-26 22:10:28 +0100438 /*
439 * If we have a single PMU interrupt that we can't shift,
440 * assume that we're running on a uniprocessor machine and
Will Deacon0b390e22011-07-27 15:18:59 +0100441 * continue. Otherwise, continue without this interrupt.
Will Deaconb0e89592011-07-26 22:10:28 +0100442 */
Will Deacon0b390e22011-07-27 15:18:59 +0100443 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
444 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
445 irq, i);
446 continue;
Will Deaconb0e89592011-07-26 22:10:28 +0100447 }
448
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530449 err = request_irq(irq, handle_irq,
Will Deaconddee87f2010-02-25 15:04:14 +0100450 IRQF_DISABLED | IRQF_NOBALANCING,
Will Deaconb0e89592011-07-26 22:10:28 +0100451 "arm-pmu", NULL);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100452 if (err) {
Will Deaconb0e89592011-07-26 22:10:28 +0100453 pr_err("unable to request IRQ%d for ARM PMU counters\n",
454 irq);
Will Deacon0b390e22011-07-27 15:18:59 +0100455 armpmu_release_hardware();
456 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100457 }
Will Deacon0b390e22011-07-27 15:18:59 +0100458
459 cpumask_set_cpu(i, &armpmu->active_irqs);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100460 }
461
Will Deacon0b390e22011-07-27 15:18:59 +0100462 return 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100463}
464
465static atomic_t active_events = ATOMIC_INIT(0);
466static DEFINE_MUTEX(pmu_reserve_mutex);
467
468static void
469hw_perf_event_destroy(struct perf_event *event)
470{
471 if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
472 armpmu_release_hardware();
473 mutex_unlock(&pmu_reserve_mutex);
474 }
475}
476
477static int
Will Deacon05d22fd2011-07-19 11:57:30 +0100478event_requires_mode_exclusion(struct perf_event_attr *attr)
479{
480 return attr->exclude_idle || attr->exclude_user ||
481 attr->exclude_kernel || attr->exclude_hv;
482}
483
484static int
Jamie Iles1b8873a2010-02-02 20:25:44 +0100485__hw_perf_event_init(struct perf_event *event)
486{
487 struct hw_perf_event *hwc = &event->hw;
488 int mapping, err;
489
490 /* Decode the generic type into an ARM event identifier. */
491 if (PERF_TYPE_HARDWARE == event->attr.type) {
Will Deacon84fee972010-11-13 17:13:56 +0000492 mapping = armpmu_map_event(event->attr.config);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100493 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
494 mapping = armpmu_map_cache_event(event->attr.config);
495 } else if (PERF_TYPE_RAW == event->attr.type) {
Will Deacon84fee972010-11-13 17:13:56 +0000496 mapping = armpmu_map_raw_event(event->attr.config);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100497 } else {
498 pr_debug("event type %x not supported\n", event->attr.type);
499 return -EOPNOTSUPP;
500 }
501
502 if (mapping < 0) {
503 pr_debug("event %x:%llx not supported\n", event->attr.type,
504 event->attr.config);
505 return mapping;
506 }
507
508 /*
Will Deacon05d22fd2011-07-19 11:57:30 +0100509 * We don't assign an index until we actually place the event onto
510 * hardware. Use -1 to signify that we haven't decided where to put it
511 * yet. For SMP systems, each core has it's own PMU so we can't do any
512 * clever allocation or constraints checking at this point.
Jamie Iles1b8873a2010-02-02 20:25:44 +0100513 */
Will Deacon05d22fd2011-07-19 11:57:30 +0100514 hwc->idx = -1;
515 hwc->config_base = 0;
516 hwc->config = 0;
517 hwc->event_base = 0;
518
519 /*
520 * Check whether we need to exclude the counter from certain modes.
521 */
522 if ((!armpmu->set_event_filter ||
523 armpmu->set_event_filter(hwc, &event->attr)) &&
524 event_requires_mode_exclusion(&event->attr)) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100525 pr_debug("ARM performance counters do not support "
526 "mode exclusion\n");
527 return -EPERM;
528 }
529
530 /*
Will Deacon05d22fd2011-07-19 11:57:30 +0100531 * Store the event encoding into the config_base field.
Jamie Iles1b8873a2010-02-02 20:25:44 +0100532 */
Will Deacon05d22fd2011-07-19 11:57:30 +0100533 hwc->config_base |= (unsigned long)mapping;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100534
535 if (!hwc->sample_period) {
536 hwc->sample_period = armpmu->max_period;
537 hwc->last_period = hwc->sample_period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200538 local64_set(&hwc->period_left, hwc->sample_period);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100539 }
540
541 err = 0;
542 if (event->group_leader != event) {
543 err = validate_group(event);
544 if (err)
545 return -EINVAL;
546 }
547
548 return err;
549}
550
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200551static int armpmu_event_init(struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100552{
553 int err = 0;
554
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200555 switch (event->attr.type) {
556 case PERF_TYPE_RAW:
557 case PERF_TYPE_HARDWARE:
558 case PERF_TYPE_HW_CACHE:
559 break;
560
561 default:
562 return -ENOENT;
563 }
564
Jamie Iles1b8873a2010-02-02 20:25:44 +0100565 event->destroy = hw_perf_event_destroy;
566
567 if (!atomic_inc_not_zero(&active_events)) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100568 mutex_lock(&pmu_reserve_mutex);
569 if (atomic_read(&active_events) == 0) {
570 err = armpmu_reserve_hardware();
571 }
572
573 if (!err)
574 atomic_inc(&active_events);
575 mutex_unlock(&pmu_reserve_mutex);
576 }
577
578 if (err)
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200579 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100580
581 err = __hw_perf_event_init(event);
582 if (err)
583 hw_perf_event_destroy(event);
584
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200585 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100586}
587
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200588static void armpmu_enable(struct pmu *pmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100589{
590 /* Enable all of the perf events on hardware. */
Will Deaconf4f38432011-07-01 14:38:12 +0100591 int idx, enabled = 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100592 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
593
Will Deaconecf5a892011-07-19 22:43:28 +0100594 for (idx = 0; idx < armpmu->num_events; ++idx) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100595 struct perf_event *event = cpuc->events[idx];
596
597 if (!event)
598 continue;
599
600 armpmu->enable(&event->hw, idx);
Will Deaconf4f38432011-07-01 14:38:12 +0100601 enabled = 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100602 }
603
Will Deaconf4f38432011-07-01 14:38:12 +0100604 if (enabled)
605 armpmu->start();
Jamie Iles1b8873a2010-02-02 20:25:44 +0100606}
607
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200608static void armpmu_disable(struct pmu *pmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100609{
Mark Rutland48957152011-04-27 10:31:51 +0100610 armpmu->stop();
Jamie Iles1b8873a2010-02-02 20:25:44 +0100611}
612
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200613static struct pmu pmu = {
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200614 .pmu_enable = armpmu_enable,
615 .pmu_disable = armpmu_disable,
616 .event_init = armpmu_event_init,
617 .add = armpmu_add,
618 .del = armpmu_del,
619 .start = armpmu_start,
620 .stop = armpmu_stop,
621 .read = armpmu_read,
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200622};
623
Will Deacon43eab872010-11-13 19:04:32 +0000624/* Include the PMU-specific implementations. */
625#include "perf_event_xscale.c"
626#include "perf_event_v6.c"
627#include "perf_event_v7.c"
Will Deacon49e6a322010-04-30 11:33:33 +0100628
Will Deacon574b69c2011-03-25 13:13:34 +0100629/*
630 * Ensure the PMU has sane values out of reset.
631 * This requires SMP to be available, so exists as a separate initcall.
632 */
633static int __init
634armpmu_reset(void)
635{
636 if (armpmu && armpmu->reset)
637 return on_each_cpu(armpmu->reset, NULL, 1);
638 return 0;
639}
640arch_initcall(armpmu_reset);
641
Will Deaconb0e89592011-07-26 22:10:28 +0100642/*
643 * PMU platform driver and devicetree bindings.
644 */
645static struct of_device_id armpmu_of_device_ids[] = {
646 {.compatible = "arm,cortex-a9-pmu"},
647 {.compatible = "arm,cortex-a8-pmu"},
648 {.compatible = "arm,arm1136-pmu"},
649 {.compatible = "arm,arm1176-pmu"},
650 {},
651};
652
653static struct platform_device_id armpmu_plat_device_ids[] = {
654 {.name = "arm-pmu"},
655 {},
656};
657
658static int __devinit armpmu_device_probe(struct platform_device *pdev)
659{
660 pmu_device = pdev;
661 return 0;
662}
663
664static struct platform_driver armpmu_driver = {
665 .driver = {
666 .name = "arm-pmu",
667 .of_match_table = armpmu_of_device_ids,
668 },
669 .probe = armpmu_device_probe,
670 .id_table = armpmu_plat_device_ids,
671};
672
673static int __init register_pmu_driver(void)
674{
675 return platform_driver_register(&armpmu_driver);
676}
677device_initcall(register_pmu_driver);
678
679/*
680 * CPU PMU identification and registration.
681 */
Jamie Iles1b8873a2010-02-02 20:25:44 +0100682static int __init
683init_hw_perf_events(void)
684{
685 unsigned long cpuid = read_cpuid_id();
686 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
687 unsigned long part_number = (cpuid & 0xFFF0);
688
Will Deacon49e6a322010-04-30 11:33:33 +0100689 /* ARM Ltd CPUs. */
Jamie Iles1b8873a2010-02-02 20:25:44 +0100690 if (0x41 == implementor) {
691 switch (part_number) {
692 case 0xB360: /* ARM1136 */
693 case 0xB560: /* ARM1156 */
694 case 0xB760: /* ARM1176 */
Will Deacon3cb314b2010-11-13 17:37:46 +0000695 armpmu = armv6pmu_init();
Jamie Iles1b8873a2010-02-02 20:25:44 +0100696 break;
697 case 0xB020: /* ARM11mpcore */
Will Deacon3cb314b2010-11-13 17:37:46 +0000698 armpmu = armv6mpcore_pmu_init();
Jamie Iles1b8873a2010-02-02 20:25:44 +0100699 break;
Jean PIHET796d1292010-01-26 18:51:05 +0100700 case 0xC080: /* Cortex-A8 */
Will Deacon3cb314b2010-11-13 17:37:46 +0000701 armpmu = armv7_a8_pmu_init();
Jean PIHET796d1292010-01-26 18:51:05 +0100702 break;
703 case 0xC090: /* Cortex-A9 */
Will Deacon3cb314b2010-11-13 17:37:46 +0000704 armpmu = armv7_a9_pmu_init();
Jean PIHET796d1292010-01-26 18:51:05 +0100705 break;
Will Deacon0c205cb2011-06-03 17:40:15 +0100706 case 0xC050: /* Cortex-A5 */
707 armpmu = armv7_a5_pmu_init();
708 break;
Will Deacon14abd032011-01-19 14:24:38 +0000709 case 0xC0F0: /* Cortex-A15 */
710 armpmu = armv7_a15_pmu_init();
711 break;
Will Deacon49e6a322010-04-30 11:33:33 +0100712 }
713 /* Intel CPUs [xscale]. */
714 } else if (0x69 == implementor) {
715 part_number = (cpuid >> 13) & 0x7;
716 switch (part_number) {
717 case 1:
Will Deacon3cb314b2010-11-13 17:37:46 +0000718 armpmu = xscale1pmu_init();
Will Deacon49e6a322010-04-30 11:33:33 +0100719 break;
720 case 2:
Will Deacon3cb314b2010-11-13 17:37:46 +0000721 armpmu = xscale2pmu_init();
Will Deacon49e6a322010-04-30 11:33:33 +0100722 break;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100723 }
724 }
725
Will Deacon49e6a322010-04-30 11:33:33 +0100726 if (armpmu) {
Jean PIHET796d1292010-01-26 18:51:05 +0100727 pr_info("enabled with %s PMU driver, %d counters available\n",
Will Deacon62994832010-11-13 18:45:27 +0000728 armpmu->name, armpmu->num_events);
Mark Rutland48957152011-04-27 10:31:51 +0100729 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
Will Deacon49e6a322010-04-30 11:33:33 +0100730 } else {
731 pr_info("no hardware support available\n");
Will Deacon49e6a322010-04-30 11:33:33 +0100732 }
Jamie Iles1b8873a2010-02-02 20:25:44 +0100733
734 return 0;
735}
Peter Zijlstra004417a2010-11-25 18:38:29 +0100736early_initcall(init_hw_perf_events);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100737
738/*
739 * Callchain handling code.
740 */
Jamie Iles1b8873a2010-02-02 20:25:44 +0100741
742/*
743 * The registers we're interested in are at the end of the variable
744 * length saved register structure. The fp points at the end of this
745 * structure so the address of this struct is:
746 * (struct frame_tail *)(xxx->fp)-1
747 *
748 * This code has been adapted from the ARM OProfile support.
749 */
750struct frame_tail {
Will Deacon4d6b7a72010-11-30 18:15:53 +0100751 struct frame_tail __user *fp;
752 unsigned long sp;
753 unsigned long lr;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100754} __attribute__((packed));
755
756/*
757 * Get the return address for a single stackframe and return a pointer to the
758 * next frame tail.
759 */
Will Deacon4d6b7a72010-11-30 18:15:53 +0100760static struct frame_tail __user *
761user_backtrace(struct frame_tail __user *tail,
Jamie Iles1b8873a2010-02-02 20:25:44 +0100762 struct perf_callchain_entry *entry)
763{
764 struct frame_tail buftail;
765
766 /* Also check accessibility of one struct frame_tail beyond */
767 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
768 return NULL;
769 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
770 return NULL;
771
Frederic Weisbecker70791ce2010-06-29 19:34:05 +0200772 perf_callchain_store(entry, buftail.lr);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100773
774 /*
775 * Frame pointers should strictly progress back up the stack
776 * (towards higher addresses).
777 */
Rabin Vincentcb061992011-02-09 11:35:12 +0100778 if (tail + 1 >= buftail.fp)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100779 return NULL;
780
781 return buftail.fp - 1;
782}
783
Frederic Weisbecker56962b42010-06-30 23:03:51 +0200784void
785perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100786{
Will Deacon4d6b7a72010-11-30 18:15:53 +0100787 struct frame_tail __user *tail;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100788
Jamie Iles1b8873a2010-02-02 20:25:44 +0100789
Will Deacon4d6b7a72010-11-30 18:15:53 +0100790 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100791
Sonny Rao860ad782011-04-18 22:12:59 +0100792 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
793 tail && !((unsigned long)tail & 0x3))
Jamie Iles1b8873a2010-02-02 20:25:44 +0100794 tail = user_backtrace(tail, entry);
795}
796
797/*
798 * Gets called by walk_stackframe() for every stackframe. This will be called
799 * whist unwinding the stackframe and is like a subroutine return so we use
800 * the PC.
801 */
802static int
803callchain_trace(struct stackframe *fr,
804 void *data)
805{
806 struct perf_callchain_entry *entry = data;
Frederic Weisbecker70791ce2010-06-29 19:34:05 +0200807 perf_callchain_store(entry, fr->pc);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100808 return 0;
809}
810
Frederic Weisbecker56962b42010-06-30 23:03:51 +0200811void
812perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100813{
814 struct stackframe fr;
815
Jamie Iles1b8873a2010-02-02 20:25:44 +0100816 fr.fp = regs->ARM_fp;
817 fr.sp = regs->ARM_sp;
818 fr.lr = regs->ARM_lr;
819 fr.pc = regs->ARM_pc;
820 walk_stackframe(&fr, callchain_trace, entry);
821}