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review.evervolv.com / android_kernel_oneplus_msm8996 / 7ec13d42f6d7e37fabe09dfd0d257a87f6bf2ee9 / . / arch / arm / boot / dts / vt8500.dtsi
blob: a0b490d5151969dc1d12959a8af2f0b14f7edda3 [file] [log] [blame]
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]1/*
2 * vt8500.dtsi - Device tree file for VIA VT8500 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "via,vt8500";
13
Tony Prisk7ec13d42013-04-23 10:33:44 +1200[diff] [blame^]14 cpus {
15 #address-cells = <0>;
16 #size-cells = <0>;
17
18 cpu {
19 device_type = "cpu";
20 compatible = "arm,arm926ej-s";
21 };
22 };
23
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]24 soc {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 ranges;
29 interrupt-parent = <&intc>;
30
31 intc: interrupt-controller@d8140000 {
32 compatible = "via,vt8500-intc";
33 interrupt-controller;
34 reg = <0xd8140000 0x10000>;
35 #interrupt-cells = <1>;
36 };
37
Tony Prisk649a59c2013-02-20 09:52:23 +1300[diff] [blame]38 pinctrl: pinctrl@d8110000 {
39 compatible = "via,vt8500-pinctrl";
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]40 reg = <0xd8110000 0x10000>;
Tony Prisk649a59c2013-02-20 09:52:23 +1300[diff] [blame]41 interrupt-controller;
42 #interrupt-cells = <2>;
43 gpio-controller;
44 #gpio-cells = <2>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]45 };
46
47 pmc@d8130000 {
48 compatible = "via,vt8500-pmc";
49 reg = <0xd8130000 0x1000>;
50
51 clocks {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 ref24: ref24M {
56 #clock-cells = <0>;
57 compatible = "fixed-clock";
58 clock-frequency = <24000000>;
59 };
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]60
61 clkuart0: uart0 {
62 #clock-cells = <0>;
63 compatible = "via,vt8500-device-clock";
64 clocks = <&ref24>;
65 enable-reg = <0x250>;
66 enable-bit = <1>;
67 };
68
69 clkuart1: uart1 {
70 #clock-cells = <0>;
71 compatible = "via,vt8500-device-clock";
72 clocks = <&ref24>;
73 enable-reg = <0x250>;
74 enable-bit = <2>;
75 };
76
77 clkuart2: uart2 {
78 #clock-cells = <0>;
79 compatible = "via,vt8500-device-clock";
80 clocks = <&ref24>;
81 enable-reg = <0x250>;
82 enable-bit = <3>;
83 };
84
85 clkuart3: uart3 {
86 #clock-cells = <0>;
87 compatible = "via,vt8500-device-clock";
88 clocks = <&ref24>;
89 enable-reg = <0x250>;
90 enable-bit = <4>;
91 };
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]92 };
93 };
94
95 timer@d8130100 {
96 compatible = "via,vt8500-timer";
97 reg = <0xd8130100 0x28>;
98 interrupts = <36>;
99 };
100
101 ehci@d8007900 {
102 compatible = "via,vt8500-ehci";
103 reg = <0xd8007900 0x200>;
104 interrupts = <43>;
105 };
106
107 uhci@d8007b00 {
108 compatible = "platform-uhci";
109 reg = <0xd8007b00 0x200>;
110 interrupts = <43>;
111 };
112
Tony Prisk7ab0a482013-04-03 07:20:38 +1300[diff] [blame]113 fb: fb@d8050800 {
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]114 compatible = "via,vt8500-fb";
115 reg = <0xd800e400 0x400>;
116 interrupts = <12>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]117 };
118
119 ge_rops@d8050400 {
120 compatible = "wm,prizm-ge-rops";
121 reg = <0xd8050400 0x100>;
122 };
123
124 uart@d8200000 {
125 compatible = "via,vt8500-uart";
126 reg = <0xd8200000 0x1040>;
127 interrupts = <32>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]128 clocks = <&clkuart0>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]129 };
130
131 uart@d82b0000 {
132 compatible = "via,vt8500-uart";
133 reg = <0xd82b0000 0x1040>;
134 interrupts = <33>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]135 clocks = <&clkuart1>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]136 };
137
138 uart@d8210000 {
139 compatible = "via,vt8500-uart";
140 reg = <0xd8210000 0x1040>;
141 interrupts = <47>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]142 clocks = <&clkuart2>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]143 };
144
145 uart@d82c0000 {
146 compatible = "via,vt8500-uart";
147 reg = <0xd82c0000 0x1040>;
148 interrupts = <50>;
Tony Prisk12faa352013-01-18 15:05:31 +1300[diff] [blame]149 clocks = <&clkuart3>;
Tony Priskcb935e72012-08-03 20:54:16 +1200[diff] [blame]150 };
151
152 rtc@d8100000 {
153 compatible = "via,vt8500-rtc";
154 reg = <0xd8100000 0x10000>;
155 interrupts = <48>;
156 };
157 };
158};