| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 1 | # |
| 2 | # Copyright (C) 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
| 3 | # |
| 4 | # This program is free software; you can redistribute it and/or modify |
| 5 | # it under the terms of the GNU General Public License version 2 as |
| 6 | # published by the Free Software Foundation. |
| 7 | # |
| 8 | |
| 9 | if ARC_PLAT_FPGA_LEGACY |
| 10 | |
| 11 | choice |
| 12 | prompt "FPGA Board" |
| 13 | |
| 14 | config ARC_BOARD_ANGEL4 |
| 15 | bool "ARC Angel4" |
| Vineet Gupta | 41195d2 | 2013-01-18 15:12:23 +0530 | [diff] [blame] | 16 | select ISS_SMP_EXTN if SMP |
| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 17 | help |
| 18 | ARC Angel4 FPGA Ref Platform (Xilinx Virtex Based) |
| 19 | |
| 20 | config ARC_BOARD_ML509 |
| 21 | bool "ML509" |
| 22 | help |
| 23 | ARC ML509 FPGA Ref Platform (Xilinx Virtex-5 Based) |
| 24 | |
| Vineet Gupta | 41195d2 | 2013-01-18 15:12:23 +0530 | [diff] [blame] | 25 | config ISS_SMP_EXTN |
| 26 | bool "ARC SMP Extensions (ISS Models only)" |
| 27 | default n |
| 28 | depends on SMP |
| 29 | select ARC_HAS_COH_RTSC |
| 30 | help |
| 31 | SMP Extensions to ARC700, in a "simulation only" Model, supported in |
| 32 | ARC ISS (Instruction Set Simulator). |
| 33 | The SMP extensions include: |
| 34 | -IDU (Interrupt Distribution Unit) |
| 35 | -XTL (To enable CPU start/stop/set-PC for another CPU) |
| 36 | It doesn't provide coherent Caches and/or Atomic Ops (LLOCK/SCOND) |
| 37 | |
| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 38 | endchoice |
| 39 | |
| 40 | config ARC_SERIAL_BAUD |
| 41 | int "UART Baud rate" |
| 42 | default "115200" |
| 43 | depends on SERIAL_ARC || SERIAL_ARC_CONSOLE |
| 44 | help |
| 45 | Baud rate for the ARC UART |
| 46 | |
| Vineet Gupta | 7fadc1e | 2013-01-18 15:12:24 +0530 | [diff] [blame^] | 47 | menuconfig ARC_HAS_BVCI_LAT_UNIT |
| 48 | bool "BVCI Bus Latency Unit" |
| 49 | depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4 |
| 50 | help |
| 51 | IP to add artifical latency to BVCI Bus Based FPGA builds. |
| 52 | The default latency (even worst case) for FPGA is non-realistic |
| 53 | (~10 SDRAM, ~5 SSRAM). |
| 54 | |
| 55 | config BVCI_LAT_UNITS |
| 56 | hex "Latency Unit(s) Bitmap" |
| 57 | default "0x0" |
| 58 | depends on ARC_HAS_BVCI_LAT_UNIT |
| 59 | help |
| 60 | There are multiple Latency Units corresponding to the many |
| 61 | interfaces of the system bus arbiter (both CPU side as well as |
| 62 | the peripheral side). |
| 63 | To add latency to ALL memory transaction, choose Unit 0, otherwise |
| 64 | for finer grainer - interface wise latency, specify a bitmap (1 bit |
| 65 | per unit) of all units. e.g. 1,2,12 will be 0x1003 |
| 66 | |
| 67 | Unit 0 - System Arb and Mem Controller |
| 68 | Unit 1 - I$ and System Bus |
| 69 | Unit 2 - D$ and System Bus |
| 70 | .. |
| 71 | Unit 12 - IDE Disk controller and System Bus |
| 72 | |
| 73 | config BVCI_LAT_CYCLES |
| 74 | int "Latency Value in cycles" |
| 75 | range 0 63 |
| 76 | default "30" |
| 77 | depends on ARC_HAS_BVCI_LAT_UNIT |
| 78 | |
| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 79 | endif |