Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1 | /* |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 2 | * linux/arch/arm/mach-omap2/clock2420_data.c |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 3 | * |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 6 | * |
| 7 | * Contacts: |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/clk.h> |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 18 | #include <linux/list.h> |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 19 | |
| 20 | #include <plat/clkdev_omap.h> |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 21 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 22 | #include "clock.h" |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 23 | #include "clock2xxx.h" |
| 24 | #include "opp2xxx.h" |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 25 | #include "prm.h" |
| 26 | #include "cm.h" |
| 27 | #include "prm-regbits-24xx.h" |
| 28 | #include "cm-regbits-24xx.h" |
| 29 | #include "sdrc.h" |
| 30 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 31 | #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR |
| 32 | |
| 33 | /* |
| 34 | * 2420 clock tree. |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 35 | * |
| 36 | * NOTE:In many cases here we are assigning a 'default' parent. In many |
| 37 | * cases the parent is selectable. The get/set parent calls will also |
| 38 | * switch sources. |
| 39 | * |
| 40 | * Many some clocks say always_enabled, but they can be auto idled for |
| 41 | * power savings. They will always be available upon clock request. |
| 42 | * |
| 43 | * Several sources are given initial rates which may be wrong, this will |
| 44 | * be fixed up in the init func. |
| 45 | * |
| 46 | * Things are broadly separated below by clock domains. It is |
| 47 | * noteworthy that most periferals have dependencies on multiple clock |
| 48 | * domains. Many get their interface clocks from the L4 domain, but get |
| 49 | * functional clocks from fixed sources or other core domain derived |
| 50 | * clocks. |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 51 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 52 | |
| 53 | /* Base external input clocks */ |
| 54 | static struct clk func_32k_ck = { |
| 55 | .name = "func_32k_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 56 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 57 | .rate = 32000, |
Russell King | 3f0a820 | 2009-01-31 10:05:51 +0000 | [diff] [blame] | 58 | .flags = RATE_FIXED, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 59 | .clkdm_name = "wkup_clkdm", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 60 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 61 | |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 62 | static struct clk secure_32k_ck = { |
| 63 | .name = "secure_32k_ck", |
| 64 | .ops = &clkops_null, |
| 65 | .rate = 32768, |
| 66 | .flags = RATE_FIXED, |
| 67 | .clkdm_name = "wkup_clkdm", |
| 68 | }; |
| 69 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 70 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
| 71 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ |
| 72 | .name = "osc_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 73 | .ops = &clkops_oscck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 74 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 75 | .recalc = &omap2_osc_clk_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 76 | }; |
| 77 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 78 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 79 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
| 80 | .name = "sys_ck", /* ~ ref_clk also */ |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 81 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 82 | .parent = &osc_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 83 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 44da0a5 | 2010-01-26 20:13:08 -0700 | [diff] [blame] | 84 | .recalc = &omap2xxx_sys_clk_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 85 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 86 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 87 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
| 88 | .name = "alt_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 89 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 90 | .rate = 54000000, |
Russell King | 3f0a820 | 2009-01-31 10:05:51 +0000 | [diff] [blame] | 91 | .flags = RATE_FIXED, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 92 | .clkdm_name = "wkup_clkdm", |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 93 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 94 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 95 | /* |
| 96 | * Analog domain root source clocks |
| 97 | */ |
| 98 | |
| 99 | /* dpll_ck, is broken out in to special cases through clksel */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 100 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... |
| 101 | * deal with this |
| 102 | */ |
| 103 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 104 | static struct dpll_data dpll_dd = { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 105 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 106 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, |
| 107 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, |
Russell King | c0bf313 | 2009-02-19 13:29:22 +0000 | [diff] [blame] | 108 | .clk_bypass = &sys_ck, |
| 109 | .clk_ref = &sys_ck, |
| 110 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 111 | .enable_mask = OMAP24XX_EN_DPLL_MASK, |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 112 | .max_multiplier = 1023, |
Paul Walmsley | 95f538a | 2009-01-28 12:08:44 -0700 | [diff] [blame] | 113 | .min_divider = 1, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 114 | .max_divider = 16, |
| 115 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 116 | }; |
| 117 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 118 | /* |
| 119 | * XXX Cannot add round_rate here yet, as this is still a composite clock, |
| 120 | * not just a DPLL |
| 121 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 122 | static struct clk dpll_ck = { |
| 123 | .name = "dpll_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 124 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 125 | .parent = &sys_ck, /* Can be func_32k also */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 126 | .dpll_data = &dpll_dd, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 127 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 128 | .recalc = &omap2_dpllcore_recalc, |
| 129 | .set_rate = &omap2_reprogram_dpllcore, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | static struct clk apll96_ck = { |
| 133 | .name = "apll96_ck", |
Paul Walmsley | 06b1693 | 2009-12-08 16:18:46 -0700 | [diff] [blame] | 134 | .ops = &clkops_apll96, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 135 | .parent = &sys_ck, |
| 136 | .rate = 96000000, |
Russell King | 3f0a820 | 2009-01-31 10:05:51 +0000 | [diff] [blame] | 137 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 138 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 139 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 140 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 141 | }; |
| 142 | |
| 143 | static struct clk apll54_ck = { |
| 144 | .name = "apll54_ck", |
Paul Walmsley | 06b1693 | 2009-12-08 16:18:46 -0700 | [diff] [blame] | 145 | .ops = &clkops_apll54, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 146 | .parent = &sys_ck, |
| 147 | .rate = 54000000, |
Russell King | 3f0a820 | 2009-01-31 10:05:51 +0000 | [diff] [blame] | 148 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 149 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 150 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 151 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 152 | }; |
| 153 | |
| 154 | /* |
| 155 | * PRCM digital base sources |
| 156 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 157 | |
| 158 | /* func_54m_ck */ |
| 159 | |
| 160 | static const struct clksel_rate func_54m_apll54_rates[] = { |
| 161 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 162 | { .div = 0 }, |
| 163 | }; |
| 164 | |
| 165 | static const struct clksel_rate func_54m_alt_rates[] = { |
| 166 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 167 | { .div = 0 }, |
| 168 | }; |
| 169 | |
| 170 | static const struct clksel func_54m_clksel[] = { |
| 171 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, |
| 172 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, |
| 173 | { .parent = NULL }, |
| 174 | }; |
| 175 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 176 | static struct clk func_54m_ck = { |
| 177 | .name = "func_54m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 178 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 179 | .parent = &apll54_ck, /* can also be alt_clk */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 180 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 181 | .init = &omap2_init_clksel_parent, |
| 182 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 183 | .clksel_mask = OMAP24XX_54M_SOURCE, |
| 184 | .clksel = func_54m_clksel, |
| 185 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 186 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 187 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 188 | static struct clk core_ck = { |
| 189 | .name = "core_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 190 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 191 | .parent = &dpll_ck, /* can also be 32k */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 192 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 193 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 194 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 195 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 196 | static struct clk func_96m_ck = { |
| 197 | .name = "func_96m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 198 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 199 | .parent = &apll96_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 200 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 201 | .recalc = &followparent_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 202 | }; |
| 203 | |
| 204 | /* func_48m_ck */ |
| 205 | |
| 206 | static const struct clksel_rate func_48m_apll96_rates[] = { |
| 207 | { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 208 | { .div = 0 }, |
| 209 | }; |
| 210 | |
| 211 | static const struct clksel_rate func_48m_alt_rates[] = { |
| 212 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 213 | { .div = 0 }, |
| 214 | }; |
| 215 | |
| 216 | static const struct clksel func_48m_clksel[] = { |
| 217 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, |
| 218 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, |
| 219 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 220 | }; |
| 221 | |
| 222 | static struct clk func_48m_ck = { |
| 223 | .name = "func_48m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 224 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 225 | .parent = &apll96_ck, /* 96M or Alt */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 226 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 227 | .init = &omap2_init_clksel_parent, |
| 228 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 229 | .clksel_mask = OMAP24XX_48M_SOURCE, |
| 230 | .clksel = func_48m_clksel, |
| 231 | .recalc = &omap2_clksel_recalc, |
| 232 | .round_rate = &omap2_clksel_round_rate, |
| 233 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 234 | }; |
| 235 | |
| 236 | static struct clk func_12m_ck = { |
| 237 | .name = "func_12m_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 238 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 239 | .parent = &func_48m_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 240 | .fixed_div = 4, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 241 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e9b98f6 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 242 | .recalc = &omap_fixed_divisor_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 243 | }; |
| 244 | |
| 245 | /* Secure timer, only available in secure mode */ |
| 246 | static struct clk wdt1_osc_ck = { |
| 247 | .name = "ck_wdt1_osc", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 248 | .ops = &clkops_null, /* RMK: missing? */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 249 | .parent = &osc_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 250 | .recalc = &followparent_recalc, |
| 251 | }; |
| 252 | |
| 253 | /* |
| 254 | * The common_clkout* clksel_rate structs are common to |
| 255 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. |
| 256 | * sys_clkout2_* are 2420-only, so the |
| 257 | * clksel_rate flags fields are inaccurate for those clocks. This is |
| 258 | * harmless since access to those clocks are gated by the struct clk |
| 259 | * flags fields, which mark them as 2420-only. |
| 260 | */ |
| 261 | static const struct clksel_rate common_clkout_src_core_rates[] = { |
| 262 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 263 | { .div = 0 } |
| 264 | }; |
| 265 | |
| 266 | static const struct clksel_rate common_clkout_src_sys_rates[] = { |
| 267 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 268 | { .div = 0 } |
| 269 | }; |
| 270 | |
| 271 | static const struct clksel_rate common_clkout_src_96m_rates[] = { |
| 272 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 273 | { .div = 0 } |
| 274 | }; |
| 275 | |
| 276 | static const struct clksel_rate common_clkout_src_54m_rates[] = { |
| 277 | { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 278 | { .div = 0 } |
| 279 | }; |
| 280 | |
| 281 | static const struct clksel common_clkout_src_clksel[] = { |
| 282 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, |
| 283 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, |
| 284 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, |
| 285 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, |
| 286 | { .parent = NULL } |
| 287 | }; |
| 288 | |
| 289 | static struct clk sys_clkout_src = { |
| 290 | .name = "sys_clkout_src", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 291 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 292 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 293 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 294 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 295 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
| 296 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 297 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 298 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, |
| 299 | .clksel = common_clkout_src_clksel, |
| 300 | .recalc = &omap2_clksel_recalc, |
| 301 | .round_rate = &omap2_clksel_round_rate, |
| 302 | .set_rate = &omap2_clksel_set_rate |
| 303 | }; |
| 304 | |
| 305 | static const struct clksel_rate common_clkout_rates[] = { |
| 306 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 307 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, |
| 308 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, |
| 309 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, |
| 310 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, |
| 311 | { .div = 0 }, |
| 312 | }; |
| 313 | |
| 314 | static const struct clksel sys_clkout_clksel[] = { |
| 315 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, |
| 316 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 317 | }; |
| 318 | |
| 319 | static struct clk sys_clkout = { |
| 320 | .name = "sys_clkout", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 321 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 322 | .parent = &sys_clkout_src, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 323 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 324 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 325 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
| 326 | .clksel = sys_clkout_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 327 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 328 | .round_rate = &omap2_clksel_round_rate, |
| 329 | .set_rate = &omap2_clksel_set_rate |
| 330 | }; |
| 331 | |
| 332 | /* In 2430, new in 2420 ES2 */ |
| 333 | static struct clk sys_clkout2_src = { |
| 334 | .name = "sys_clkout2_src", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 335 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 336 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 337 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 338 | .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 339 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, |
| 340 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 341 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 342 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, |
| 343 | .clksel = common_clkout_src_clksel, |
| 344 | .recalc = &omap2_clksel_recalc, |
| 345 | .round_rate = &omap2_clksel_round_rate, |
| 346 | .set_rate = &omap2_clksel_set_rate |
| 347 | }; |
| 348 | |
| 349 | static const struct clksel sys_clkout2_clksel[] = { |
| 350 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, |
| 351 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 352 | }; |
| 353 | |
| 354 | /* In 2430, new in 2420 ES2 */ |
| 355 | static struct clk sys_clkout2 = { |
| 356 | .name = "sys_clkout2", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 357 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 358 | .parent = &sys_clkout2_src, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 359 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 360 | .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 361 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, |
| 362 | .clksel = sys_clkout2_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 363 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 364 | .round_rate = &omap2_clksel_round_rate, |
| 365 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 366 | }; |
| 367 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 368 | static struct clk emul_ck = { |
| 369 | .name = "emul_ck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 370 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 371 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 372 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 373 | .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 374 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
| 375 | .recalc = &followparent_recalc, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 376 | |
| 377 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 378 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 379 | /* |
| 380 | * MPU clock domain |
| 381 | * Clocks: |
| 382 | * MPU_FCLK, MPU_ICLK |
| 383 | * INT_M_FCLK, INT_M_I_CLK |
| 384 | * |
| 385 | * - Individual clocks are hardware managed. |
| 386 | * - Base divider comes from: CM_CLKSEL_MPU |
| 387 | * |
| 388 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 389 | static const struct clksel_rate mpu_core_rates[] = { |
| 390 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 391 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 392 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, |
| 393 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 394 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 395 | { .div = 0 }, |
| 396 | }; |
| 397 | |
| 398 | static const struct clksel mpu_clksel[] = { |
| 399 | { .parent = &core_ck, .rates = mpu_core_rates }, |
| 400 | { .parent = NULL } |
| 401 | }; |
| 402 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 403 | static struct clk mpu_ck = { /* Control cpu */ |
| 404 | .name = "mpu_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 405 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 406 | .parent = &core_ck, |
Paul Walmsley | 1a33771 | 2010-02-22 22:09:16 -0700 | [diff] [blame] | 407 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 408 | .clkdm_name = "mpu_clkdm", |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 409 | .init = &omap2_init_clksel_parent, |
| 410 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
| 411 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 412 | .clksel = mpu_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 413 | .recalc = &omap2_clksel_recalc, |
| 414 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 415 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 416 | /* |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 417 | * DSP (2420-UMA+IVA1) clock domain |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 418 | * Clocks: |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 419 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 420 | * |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 421 | * Won't be too specific here. The core clock comes into this block |
| 422 | * it is divided then tee'ed. One branch goes directly to xyz enable |
| 423 | * controls. The other branch gets further divided by 2 then possibly |
| 424 | * routed into a synchronizer and out of clocks abc. |
| 425 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 426 | static const struct clksel_rate dsp_fck_core_rates[] = { |
| 427 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 428 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 429 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 430 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 431 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 432 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 433 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, |
| 434 | { .div = 0 }, |
| 435 | }; |
| 436 | |
| 437 | static const struct clksel dsp_fck_clksel[] = { |
| 438 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, |
| 439 | { .parent = NULL } |
| 440 | }; |
| 441 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 442 | static struct clk dsp_fck = { |
| 443 | .name = "dsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 444 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 445 | .parent = &core_ck, |
Paul Walmsley | 1a33771 | 2010-02-22 22:09:16 -0700 | [diff] [blame] | 446 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 447 | .clkdm_name = "dsp_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 448 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 449 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| 450 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 451 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, |
| 452 | .clksel = dsp_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 453 | .recalc = &omap2_clksel_recalc, |
| 454 | }; |
| 455 | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 456 | /* DSP interface clock */ |
| 457 | static const struct clksel_rate dsp_irate_ick_rates[] = { |
| 458 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 459 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 460 | { .div = 0 }, |
| 461 | }; |
| 462 | |
| 463 | static const struct clksel dsp_irate_ick_clksel[] = { |
| 464 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, |
| 465 | { .parent = NULL } |
| 466 | }; |
| 467 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 468 | /* This clock does not exist as such in the TRM. */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 469 | static struct clk dsp_irate_ick = { |
| 470 | .name = "dsp_irate_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 471 | .ops = &clkops_null, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 472 | .parent = &dsp_fck, |
Paul Walmsley | 1a33771 | 2010-02-22 22:09:16 -0700 | [diff] [blame] | 473 | .flags = DELAYED_APP, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 474 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 475 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, |
| 476 | .clksel = dsp_irate_ick_clksel, |
| 477 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 478 | }; |
| 479 | |
| 480 | /* 2420 only */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 481 | static struct clk dsp_ick = { |
| 482 | .name = "dsp_ick", /* apparently ipi and isp */ |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 483 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 484 | .parent = &dsp_irate_ick, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 485 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), |
| 486 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ |
| 487 | }; |
| 488 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 489 | /* |
| 490 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with |
| 491 | * the C54x, but which is contained in the DSP powerdomain. Does not |
| 492 | * exist on later OMAPs. |
| 493 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 494 | static struct clk iva1_ifck = { |
| 495 | .name = "iva1_ifck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 496 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 497 | .parent = &core_ck, |
Paul Walmsley | 1a33771 | 2010-02-22 22:09:16 -0700 | [diff] [blame] | 498 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 499 | .clkdm_name = "iva1_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 500 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 501 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, |
| 502 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 503 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, |
| 504 | .clksel = dsp_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 505 | .recalc = &omap2_clksel_recalc, |
| 506 | }; |
| 507 | |
| 508 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ |
| 509 | static struct clk iva1_mpu_int_ifck = { |
| 510 | .name = "iva1_mpu_int_ifck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 511 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 512 | .parent = &iva1_ifck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 513 | .clkdm_name = "iva1_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 514 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 515 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, |
| 516 | .fixed_div = 2, |
Paul Walmsley | e9b98f6 | 2010-01-26 20:12:57 -0700 | [diff] [blame] | 517 | .recalc = &omap_fixed_divisor_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 518 | }; |
| 519 | |
| 520 | /* |
| 521 | * L3 clock domain |
| 522 | * L3 clocks are used for both interface and functional clocks to |
| 523 | * multiple entities. Some of these clocks are completely managed |
| 524 | * by hardware, and some others allow software control. Hardware |
| 525 | * managed ones general are based on directly CLK_REQ signals and |
| 526 | * various auto idle settings. The functional spec sets many of these |
| 527 | * as 'tie-high' for their enables. |
| 528 | * |
| 529 | * I-CLOCKS: |
| 530 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA |
| 531 | * CAM, HS-USB. |
| 532 | * F-CLOCK |
| 533 | * SSI. |
| 534 | * |
| 535 | * GPMC memories and SDRC have timing and clock sensitive registers which |
| 536 | * may very well need notification when the clock changes. Currently for low |
| 537 | * operating points, these are taken care of in sleep.S. |
| 538 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 539 | static const struct clksel_rate core_l3_core_rates[] = { |
| 540 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 541 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, |
| 542 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 543 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
| 544 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 545 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, |
| 546 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, |
| 547 | { .div = 0 } |
| 548 | }; |
| 549 | |
| 550 | static const struct clksel core_l3_clksel[] = { |
| 551 | { .parent = &core_ck, .rates = core_l3_core_rates }, |
| 552 | { .parent = NULL } |
| 553 | }; |
| 554 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 555 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
| 556 | .name = "core_l3_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 557 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 558 | .parent = &core_ck, |
Paul Walmsley | 1a33771 | 2010-02-22 22:09:16 -0700 | [diff] [blame] | 559 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 560 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 561 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 562 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
| 563 | .clksel = core_l3_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 564 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 565 | }; |
| 566 | |
| 567 | /* usb_l4_ick */ |
| 568 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { |
| 569 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 570 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 571 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 572 | { .div = 0 } |
| 573 | }; |
| 574 | |
| 575 | static const struct clksel usb_l4_ick_clksel[] = { |
| 576 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, |
| 577 | { .parent = NULL }, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 578 | }; |
| 579 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 580 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 581 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
| 582 | .name = "usb_l4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 583 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 584 | .parent = &core_l3_ck, |
Paul Walmsley | 1a33771 | 2010-02-22 22:09:16 -0700 | [diff] [blame] | 585 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 586 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 587 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 588 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| 589 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 590 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, |
| 591 | .clksel = usb_l4_ick_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 592 | .recalc = &omap2_clksel_recalc, |
| 593 | }; |
| 594 | |
| 595 | /* |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 596 | * L4 clock management domain |
| 597 | * |
| 598 | * This domain contains lots of interface clocks from the L4 interface, some |
| 599 | * functional clocks. Fixed APLL functional source clocks are managed in |
| 600 | * this domain. |
| 601 | */ |
| 602 | static const struct clksel_rate l4_core_l3_rates[] = { |
| 603 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 604 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 605 | { .div = 0 } |
| 606 | }; |
| 607 | |
| 608 | static const struct clksel l4_clksel[] = { |
| 609 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, |
| 610 | { .parent = NULL } |
| 611 | }; |
| 612 | |
| 613 | static struct clk l4_ck = { /* used both as an ick and fck */ |
| 614 | .name = "l4_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 615 | .ops = &clkops_null, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 616 | .parent = &core_l3_ck, |
Russell King | 3f0a820 | 2009-01-31 10:05:51 +0000 | [diff] [blame] | 617 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 618 | .clkdm_name = "core_l4_clkdm", |
| 619 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 620 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |
| 621 | .clksel = l4_clksel, |
| 622 | .recalc = &omap2_clksel_recalc, |
| 623 | .round_rate = &omap2_clksel_round_rate, |
| 624 | .set_rate = &omap2_clksel_set_rate |
| 625 | }; |
| 626 | |
| 627 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 628 | * SSI is in L3 management domain, its direct parent is core not l3, |
| 629 | * many core power domain entities are grouped into the L3 clock |
| 630 | * domain. |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 631 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 632 | * |
| 633 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. |
| 634 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 635 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { |
| 636 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 637 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 638 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 639 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 640 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 641 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 642 | { .div = 0 } |
| 643 | }; |
| 644 | |
| 645 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { |
| 646 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, |
| 647 | { .parent = NULL } |
| 648 | }; |
| 649 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 650 | static struct clk ssi_ssr_sst_fck = { |
| 651 | .name = "ssi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 652 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 653 | .parent = &core_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 654 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 655 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 656 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 657 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| 658 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 659 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, |
| 660 | .clksel = ssi_ssr_sst_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 661 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 662 | .round_rate = &omap2_clksel_round_rate, |
| 663 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 664 | }; |
| 665 | |
Paul Walmsley | 9299fd8 | 2009-01-27 19:12:54 -0700 | [diff] [blame] | 666 | /* |
| 667 | * Presumably this is the same as SSI_ICLK. |
| 668 | * TRM contradicts itself on what clockdomain SSI_ICLK is in |
| 669 | */ |
| 670 | static struct clk ssi_l4_ick = { |
| 671 | .name = "ssi_l4_ick", |
| 672 | .ops = &clkops_omap2_dflt_wait, |
| 673 | .parent = &l4_ck, |
| 674 | .clkdm_name = "core_l4_clkdm", |
| 675 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 676 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| 677 | .recalc = &followparent_recalc, |
| 678 | }; |
| 679 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 680 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 681 | /* |
| 682 | * GFX clock domain |
| 683 | * Clocks: |
| 684 | * GFX_FCLK, GFX_ICLK |
| 685 | * GFX_CG1(2d), GFX_CG2(3d) |
| 686 | * |
| 687 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) |
| 688 | * The 2d and 3d clocks run at a hardware determined |
| 689 | * divided value of fclk. |
| 690 | * |
| 691 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 692 | |
| 693 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ |
| 694 | static const struct clksel gfx_fck_clksel[] = { |
| 695 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, |
| 696 | { .parent = NULL }, |
| 697 | }; |
| 698 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 699 | static struct clk gfx_3d_fck = { |
| 700 | .name = "gfx_3d_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 701 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 702 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 703 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 704 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 705 | .enable_bit = OMAP24XX_EN_3D_SHIFT, |
| 706 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 707 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 708 | .clksel = gfx_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 709 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 710 | .round_rate = &omap2_clksel_round_rate, |
| 711 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 712 | }; |
| 713 | |
| 714 | static struct clk gfx_2d_fck = { |
| 715 | .name = "gfx_2d_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 716 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 717 | .parent = &core_l3_ck, |
Paul Walmsley | 1a33771 | 2010-02-22 22:09:16 -0700 | [diff] [blame] | 718 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 719 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 720 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 721 | .enable_bit = OMAP24XX_EN_2D_SHIFT, |
| 722 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 723 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 724 | .clksel = gfx_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 725 | .recalc = &omap2_clksel_recalc, |
| 726 | }; |
| 727 | |
| 728 | static struct clk gfx_ick = { |
| 729 | .name = "gfx_ick", /* From l3 */ |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 730 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 731 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 732 | .clkdm_name = "gfx_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 733 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 734 | .enable_bit = OMAP_EN_GFX_SHIFT, |
| 735 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 736 | }; |
| 737 | |
| 738 | /* |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 739 | * DSS clock domain |
| 740 | * CLOCKs: |
| 741 | * DSS_L4_ICLK, DSS_L3_ICLK, |
| 742 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK |
| 743 | * |
| 744 | * DSS is both initiator and target. |
| 745 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 746 | /* XXX Add RATE_NOT_VALIDATED */ |
| 747 | |
| 748 | static const struct clksel_rate dss1_fck_sys_rates[] = { |
| 749 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 750 | { .div = 0 } |
| 751 | }; |
| 752 | |
| 753 | static const struct clksel_rate dss1_fck_core_rates[] = { |
| 754 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, |
| 755 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, |
| 756 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, |
| 757 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, |
| 758 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, |
| 759 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, |
| 760 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, |
| 761 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, |
| 762 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, |
| 763 | { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 764 | { .div = 0 } |
| 765 | }; |
| 766 | |
| 767 | static const struct clksel dss1_fck_clksel[] = { |
| 768 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, |
| 769 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, |
| 770 | { .parent = NULL }, |
| 771 | }; |
| 772 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 773 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
| 774 | .name = "dss_ick", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 775 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 776 | .parent = &l4_ck, /* really both l3 and l4 */ |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 777 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 778 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 779 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 780 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 781 | }; |
| 782 | |
| 783 | static struct clk dss1_fck = { |
| 784 | .name = "dss1_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 785 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 786 | .parent = &core_ck, /* Core or sys */ |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 787 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 788 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 789 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 790 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 791 | .init = &omap2_init_clksel_parent, |
| 792 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 793 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, |
| 794 | .clksel = dss1_fck_clksel, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 795 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 796 | .round_rate = &omap2_clksel_round_rate, |
| 797 | .set_rate = &omap2_clksel_set_rate |
| 798 | }; |
| 799 | |
| 800 | static const struct clksel_rate dss2_fck_sys_rates[] = { |
| 801 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 802 | { .div = 0 } |
| 803 | }; |
| 804 | |
| 805 | static const struct clksel_rate dss2_fck_48m_rates[] = { |
| 806 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 807 | { .div = 0 } |
| 808 | }; |
| 809 | |
| 810 | static const struct clksel dss2_fck_clksel[] = { |
| 811 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, |
| 812 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, |
| 813 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 814 | }; |
| 815 | |
| 816 | static struct clk dss2_fck = { /* Alt clk used in power management */ |
| 817 | .name = "dss2_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 818 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 819 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 820 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 821 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 822 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 823 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
| 824 | .init = &omap2_init_clksel_parent, |
| 825 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 826 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, |
| 827 | .clksel = dss2_fck_clksel, |
| 828 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 829 | }; |
| 830 | |
| 831 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ |
| 832 | .name = "dss_54m_fck", /* 54m tv clk */ |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 833 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 834 | .parent = &func_54m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 835 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 836 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 837 | .enable_bit = OMAP24XX_EN_TV_SHIFT, |
| 838 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 839 | }; |
| 840 | |
| 841 | /* |
| 842 | * CORE power domain ICLK & FCLK defines. |
| 843 | * Many of the these can have more than one possible parent. Entries |
| 844 | * here will likely have an L4 interface parent, and may have multiple |
| 845 | * functional clock parents. |
| 846 | */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 847 | static const struct clksel_rate gpt_alt_rates[] = { |
| 848 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, |
| 849 | { .div = 0 } |
| 850 | }; |
| 851 | |
| 852 | static const struct clksel omap24xx_gpt_clksel[] = { |
| 853 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, |
| 854 | { .parent = &sys_ck, .rates = gpt_sys_rates }, |
| 855 | { .parent = &alt_ck, .rates = gpt_alt_rates }, |
| 856 | { .parent = NULL }, |
| 857 | }; |
| 858 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 859 | static struct clk gpt1_ick = { |
| 860 | .name = "gpt1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 861 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 862 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 863 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 864 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 865 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 866 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 867 | }; |
| 868 | |
| 869 | static struct clk gpt1_fck = { |
| 870 | .name = "gpt1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 871 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 872 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 873 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 874 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 875 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 876 | .init = &omap2_init_clksel_parent, |
| 877 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), |
| 878 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, |
| 879 | .clksel = omap24xx_gpt_clksel, |
| 880 | .recalc = &omap2_clksel_recalc, |
| 881 | .round_rate = &omap2_clksel_round_rate, |
| 882 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 883 | }; |
| 884 | |
| 885 | static struct clk gpt2_ick = { |
| 886 | .name = "gpt2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 887 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 888 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 889 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 890 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 891 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 892 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 893 | }; |
| 894 | |
| 895 | static struct clk gpt2_fck = { |
| 896 | .name = "gpt2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 897 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 898 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 899 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 900 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 901 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 902 | .init = &omap2_init_clksel_parent, |
| 903 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 904 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, |
| 905 | .clksel = omap24xx_gpt_clksel, |
| 906 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 907 | }; |
| 908 | |
| 909 | static struct clk gpt3_ick = { |
| 910 | .name = "gpt3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 911 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 912 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 913 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 914 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 915 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 916 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 917 | }; |
| 918 | |
| 919 | static struct clk gpt3_fck = { |
| 920 | .name = "gpt3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 921 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 922 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 923 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 924 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 925 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 926 | .init = &omap2_init_clksel_parent, |
| 927 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 928 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, |
| 929 | .clksel = omap24xx_gpt_clksel, |
| 930 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 931 | }; |
| 932 | |
| 933 | static struct clk gpt4_ick = { |
| 934 | .name = "gpt4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 935 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 936 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 937 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 938 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 939 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 940 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 941 | }; |
| 942 | |
| 943 | static struct clk gpt4_fck = { |
| 944 | .name = "gpt4_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 945 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 946 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 947 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 948 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 949 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 950 | .init = &omap2_init_clksel_parent, |
| 951 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 952 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, |
| 953 | .clksel = omap24xx_gpt_clksel, |
| 954 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 955 | }; |
| 956 | |
| 957 | static struct clk gpt5_ick = { |
| 958 | .name = "gpt5_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 959 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 960 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 961 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 962 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 963 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 964 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 965 | }; |
| 966 | |
| 967 | static struct clk gpt5_fck = { |
| 968 | .name = "gpt5_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 969 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 970 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 971 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 972 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 973 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 974 | .init = &omap2_init_clksel_parent, |
| 975 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 976 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, |
| 977 | .clksel = omap24xx_gpt_clksel, |
| 978 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 979 | }; |
| 980 | |
| 981 | static struct clk gpt6_ick = { |
| 982 | .name = "gpt6_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 983 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 984 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 985 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 986 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 987 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 988 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 989 | }; |
| 990 | |
| 991 | static struct clk gpt6_fck = { |
| 992 | .name = "gpt6_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 993 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 994 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 995 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 996 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 997 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 998 | .init = &omap2_init_clksel_parent, |
| 999 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1000 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, |
| 1001 | .clksel = omap24xx_gpt_clksel, |
| 1002 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1003 | }; |
| 1004 | |
| 1005 | static struct clk gpt7_ick = { |
| 1006 | .name = "gpt7_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1007 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1008 | .parent = &l4_ck, |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1009 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1010 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 1011 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1012 | }; |
| 1013 | |
| 1014 | static struct clk gpt7_fck = { |
| 1015 | .name = "gpt7_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1016 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1017 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1018 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1019 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1020 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 1021 | .init = &omap2_init_clksel_parent, |
| 1022 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1023 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, |
| 1024 | .clksel = omap24xx_gpt_clksel, |
| 1025 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1026 | }; |
| 1027 | |
| 1028 | static struct clk gpt8_ick = { |
| 1029 | .name = "gpt8_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1030 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1031 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1032 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1033 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1034 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 1035 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1036 | }; |
| 1037 | |
| 1038 | static struct clk gpt8_fck = { |
| 1039 | .name = "gpt8_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1040 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1041 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1042 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1043 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1044 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 1045 | .init = &omap2_init_clksel_parent, |
| 1046 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1047 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, |
| 1048 | .clksel = omap24xx_gpt_clksel, |
| 1049 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1050 | }; |
| 1051 | |
| 1052 | static struct clk gpt9_ick = { |
| 1053 | .name = "gpt9_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1054 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1055 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1056 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1057 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1058 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 1059 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1060 | }; |
| 1061 | |
| 1062 | static struct clk gpt9_fck = { |
| 1063 | .name = "gpt9_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1064 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1065 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1066 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1067 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1068 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 1069 | .init = &omap2_init_clksel_parent, |
| 1070 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1071 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, |
| 1072 | .clksel = omap24xx_gpt_clksel, |
| 1073 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1074 | }; |
| 1075 | |
| 1076 | static struct clk gpt10_ick = { |
| 1077 | .name = "gpt10_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1078 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1079 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1080 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1081 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1082 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 1083 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1084 | }; |
| 1085 | |
| 1086 | static struct clk gpt10_fck = { |
| 1087 | .name = "gpt10_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1088 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1089 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1090 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1091 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1092 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 1093 | .init = &omap2_init_clksel_parent, |
| 1094 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1095 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, |
| 1096 | .clksel = omap24xx_gpt_clksel, |
| 1097 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1098 | }; |
| 1099 | |
| 1100 | static struct clk gpt11_ick = { |
| 1101 | .name = "gpt11_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1102 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1103 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1104 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1105 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1106 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 1107 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1108 | }; |
| 1109 | |
| 1110 | static struct clk gpt11_fck = { |
| 1111 | .name = "gpt11_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1112 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1113 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1114 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1115 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1116 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 1117 | .init = &omap2_init_clksel_parent, |
| 1118 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1119 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, |
| 1120 | .clksel = omap24xx_gpt_clksel, |
| 1121 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1122 | }; |
| 1123 | |
| 1124 | static struct clk gpt12_ick = { |
| 1125 | .name = "gpt12_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1126 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1127 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1128 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1129 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1130 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 1131 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1132 | }; |
| 1133 | |
| 1134 | static struct clk gpt12_fck = { |
| 1135 | .name = "gpt12_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1136 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | f248076 | 2009-04-23 21:11:10 -0600 | [diff] [blame] | 1137 | .parent = &secure_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1138 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1139 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1140 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 1141 | .init = &omap2_init_clksel_parent, |
| 1142 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), |
| 1143 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, |
| 1144 | .clksel = omap24xx_gpt_clksel, |
| 1145 | .recalc = &omap2_clksel_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1146 | }; |
| 1147 | |
| 1148 | static struct clk mcbsp1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1149 | .name = "mcbsp1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1150 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1151 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1152 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1153 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1154 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 1155 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1156 | }; |
| 1157 | |
| 1158 | static struct clk mcbsp1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1159 | .name = "mcbsp1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1160 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1161 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1162 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1163 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1164 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 1165 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1166 | }; |
| 1167 | |
| 1168 | static struct clk mcbsp2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1169 | .name = "mcbsp2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1170 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1171 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1172 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1173 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1174 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 1175 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1176 | }; |
| 1177 | |
| 1178 | static struct clk mcbsp2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1179 | .name = "mcbsp2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1180 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1181 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1182 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1183 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1184 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 1185 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1186 | }; |
| 1187 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1188 | static struct clk mcspi1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1189 | .name = "mcspi1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1190 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1191 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1192 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1193 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1194 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1195 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1196 | }; |
| 1197 | |
| 1198 | static struct clk mcspi1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1199 | .name = "mcspi1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1200 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1201 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1202 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1203 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1204 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1205 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1206 | }; |
| 1207 | |
| 1208 | static struct clk mcspi2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1209 | .name = "mcspi2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1210 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1211 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1212 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1213 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1214 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1215 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1216 | }; |
| 1217 | |
| 1218 | static struct clk mcspi2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1219 | .name = "mcspi2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1220 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1221 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1222 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1223 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1224 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1225 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1226 | }; |
| 1227 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1228 | static struct clk uart1_ick = { |
| 1229 | .name = "uart1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1230 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1231 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1232 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1233 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1234 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| 1235 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1236 | }; |
| 1237 | |
| 1238 | static struct clk uart1_fck = { |
| 1239 | .name = "uart1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1240 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1241 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1242 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1243 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1244 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| 1245 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1246 | }; |
| 1247 | |
| 1248 | static struct clk uart2_ick = { |
| 1249 | .name = "uart2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1250 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1251 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1252 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1253 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1254 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| 1255 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1256 | }; |
| 1257 | |
| 1258 | static struct clk uart2_fck = { |
| 1259 | .name = "uart2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1260 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1261 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1262 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1263 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1264 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| 1265 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1266 | }; |
| 1267 | |
| 1268 | static struct clk uart3_ick = { |
| 1269 | .name = "uart3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1270 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1271 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1272 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1273 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1274 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| 1275 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1276 | }; |
| 1277 | |
| 1278 | static struct clk uart3_fck = { |
| 1279 | .name = "uart3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1280 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1281 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1282 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1283 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1284 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| 1285 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1286 | }; |
| 1287 | |
| 1288 | static struct clk gpios_ick = { |
| 1289 | .name = "gpios_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1290 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1291 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1292 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1293 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1294 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1295 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1296 | }; |
| 1297 | |
| 1298 | static struct clk gpios_fck = { |
| 1299 | .name = "gpios_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1300 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1301 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1302 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1303 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 1304 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1305 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1306 | }; |
| 1307 | |
| 1308 | static struct clk mpu_wdt_ick = { |
| 1309 | .name = "mpu_wdt_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1310 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1311 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1312 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1313 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1314 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 1315 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1316 | }; |
| 1317 | |
| 1318 | static struct clk mpu_wdt_fck = { |
| 1319 | .name = "mpu_wdt_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1320 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1321 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1322 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1323 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 1324 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 1325 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1326 | }; |
| 1327 | |
| 1328 | static struct clk sync_32k_ick = { |
| 1329 | .name = "sync_32k_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1330 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1331 | .parent = &l4_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1332 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1333 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1334 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1335 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, |
| 1336 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1337 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1338 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1339 | static struct clk wdt1_ick = { |
| 1340 | .name = "wdt1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1341 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1342 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1343 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1344 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1345 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, |
| 1346 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1347 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1348 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1349 | static struct clk omapctrl_ick = { |
| 1350 | .name = "omapctrl_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1351 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1352 | .parent = &l4_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1353 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1354 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1355 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1356 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, |
| 1357 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1358 | }; |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1359 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1360 | static struct clk cam_ick = { |
| 1361 | .name = "cam_ick", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 1362 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1363 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1364 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1365 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1366 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| 1367 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1368 | }; |
| 1369 | |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1370 | /* |
| 1371 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be |
| 1372 | * split into two separate clocks, since the parent clocks are different |
| 1373 | * and the clockdomains are also different. |
| 1374 | */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1375 | static struct clk cam_fck = { |
| 1376 | .name = "cam_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 1377 | .ops = &clkops_omap2_dflt, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1378 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1379 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1381 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| 1382 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1383 | }; |
| 1384 | |
| 1385 | static struct clk mailboxes_ick = { |
| 1386 | .name = "mailboxes_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1387 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1388 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1389 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1390 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1391 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| 1392 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1393 | }; |
| 1394 | |
| 1395 | static struct clk wdt4_ick = { |
| 1396 | .name = "wdt4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1397 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1398 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1399 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1401 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| 1402 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1403 | }; |
| 1404 | |
| 1405 | static struct clk wdt4_fck = { |
| 1406 | .name = "wdt4_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1407 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1408 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1409 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1410 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1411 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| 1412 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1413 | }; |
| 1414 | |
| 1415 | static struct clk wdt3_ick = { |
| 1416 | .name = "wdt3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1417 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1418 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1419 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1420 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1421 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| 1422 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1423 | }; |
| 1424 | |
| 1425 | static struct clk wdt3_fck = { |
| 1426 | .name = "wdt3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1427 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1428 | .parent = &func_32k_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1429 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1430 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1431 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| 1432 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1433 | }; |
| 1434 | |
| 1435 | static struct clk mspro_ick = { |
| 1436 | .name = "mspro_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1437 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1438 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1439 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1440 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1441 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| 1442 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1443 | }; |
| 1444 | |
| 1445 | static struct clk mspro_fck = { |
| 1446 | .name = "mspro_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1447 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1448 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1449 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1450 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1451 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| 1452 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1453 | }; |
| 1454 | |
| 1455 | static struct clk mmc_ick = { |
| 1456 | .name = "mmc_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1457 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1458 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1459 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1461 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| 1462 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1463 | }; |
| 1464 | |
| 1465 | static struct clk mmc_fck = { |
| 1466 | .name = "mmc_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1467 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1468 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1469 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1470 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1471 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| 1472 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1473 | }; |
| 1474 | |
| 1475 | static struct clk fac_ick = { |
| 1476 | .name = "fac_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1477 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1478 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1479 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1480 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1481 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| 1482 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1483 | }; |
| 1484 | |
| 1485 | static struct clk fac_fck = { |
| 1486 | .name = "fac_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1487 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1488 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1489 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1490 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1491 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| 1492 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1493 | }; |
| 1494 | |
| 1495 | static struct clk eac_ick = { |
| 1496 | .name = "eac_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1497 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1498 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1499 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1500 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1501 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| 1502 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1503 | }; |
| 1504 | |
| 1505 | static struct clk eac_fck = { |
| 1506 | .name = "eac_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1507 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1508 | .parent = &func_96m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1509 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1510 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1511 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| 1512 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1513 | }; |
| 1514 | |
| 1515 | static struct clk hdq_ick = { |
| 1516 | .name = "hdq_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1517 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1518 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1519 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1520 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1521 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| 1522 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1523 | }; |
| 1524 | |
| 1525 | static struct clk hdq_fck = { |
| 1526 | .name = "hdq_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1527 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1528 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1529 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1530 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1531 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| 1532 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1533 | }; |
| 1534 | |
| 1535 | static struct clk i2c2_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1536 | .name = "i2c2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1537 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1538 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1539 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1540 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1541 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| 1542 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1543 | }; |
| 1544 | |
| 1545 | static struct clk i2c2_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1546 | .name = "i2c2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1547 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1548 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1549 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1550 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1551 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| 1552 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1553 | }; |
| 1554 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1555 | static struct clk i2c1_ick = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1556 | .name = "i2c1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1557 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1558 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1559 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1560 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1561 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| 1562 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1563 | }; |
| 1564 | |
| 1565 | static struct clk i2c1_fck = { |
Paul Walmsley | b92c170 | 2010-02-22 22:09:19 -0700 | [diff] [blame] | 1566 | .name = "i2c1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1567 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1568 | .parent = &func_12m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1569 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1570 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1571 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| 1572 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1573 | }; |
| 1574 | |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1575 | static struct clk gpmc_fck = { |
| 1576 | .name = "gpmc_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1577 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1578 | .parent = &core_l3_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1579 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1580 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1581 | .recalc = &followparent_recalc, |
| 1582 | }; |
| 1583 | |
| 1584 | static struct clk sdma_fck = { |
| 1585 | .name = "sdma_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1586 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1587 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1588 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1589 | .recalc = &followparent_recalc, |
| 1590 | }; |
| 1591 | |
| 1592 | static struct clk sdma_ick = { |
| 1593 | .name = "sdma_ick", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1594 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1595 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1596 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1597 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1598 | }; |
| 1599 | |
| 1600 | static struct clk vlynq_ick = { |
| 1601 | .name = "vlynq_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1602 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1603 | .parent = &core_l3_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1604 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1605 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1606 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| 1607 | .recalc = &followparent_recalc, |
| 1608 | }; |
| 1609 | |
| 1610 | static const struct clksel_rate vlynq_fck_96m_rates[] = { |
| 1611 | { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, |
| 1612 | { .div = 0 } |
| 1613 | }; |
| 1614 | |
| 1615 | static const struct clksel_rate vlynq_fck_core_rates[] = { |
| 1616 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, |
| 1617 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, |
| 1618 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, |
| 1619 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, |
| 1620 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, |
| 1621 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, |
| 1622 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, |
| 1623 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, |
| 1624 | { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, |
| 1625 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, |
| 1626 | { .div = 0 } |
| 1627 | }; |
| 1628 | |
| 1629 | static const struct clksel vlynq_fck_clksel[] = { |
| 1630 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, |
| 1631 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, |
| 1632 | { .parent = NULL } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1633 | }; |
| 1634 | |
| 1635 | static struct clk vlynq_fck = { |
| 1636 | .name = "vlynq_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1637 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1638 | .parent = &func_96m_ck, |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 1639 | .flags = DELAYED_APP, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1640 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1641 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1642 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| 1643 | .init = &omap2_init_clksel_parent, |
| 1644 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1645 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, |
| 1646 | .clksel = vlynq_fck_clksel, |
| 1647 | .recalc = &omap2_clksel_recalc, |
| 1648 | .round_rate = &omap2_clksel_round_rate, |
| 1649 | .set_rate = &omap2_clksel_set_rate |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1650 | }; |
| 1651 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1652 | static struct clk des_ick = { |
| 1653 | .name = "des_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1654 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1655 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1656 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1657 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1658 | .enable_bit = OMAP24XX_EN_DES_SHIFT, |
| 1659 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1660 | }; |
| 1661 | |
| 1662 | static struct clk sha_ick = { |
| 1663 | .name = "sha_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1664 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1665 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1666 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1667 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1668 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, |
| 1669 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1670 | }; |
| 1671 | |
| 1672 | static struct clk rng_ick = { |
| 1673 | .name = "rng_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1674 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1675 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1676 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1677 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1678 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, |
| 1679 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1680 | }; |
| 1681 | |
| 1682 | static struct clk aes_ick = { |
| 1683 | .name = "aes_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1684 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1685 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1686 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1687 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1688 | .enable_bit = OMAP24XX_EN_AES_SHIFT, |
| 1689 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1690 | }; |
| 1691 | |
| 1692 | static struct clk pka_ick = { |
| 1693 | .name = "pka_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1694 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1695 | .parent = &l4_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1696 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1697 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 1698 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, |
| 1699 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1700 | }; |
| 1701 | |
| 1702 | static struct clk usb_fck = { |
| 1703 | .name = "usb_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1704 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1705 | .parent = &func_48m_ck, |
Paul Walmsley | d1b03f6 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 1706 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1707 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1708 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| 1709 | .recalc = &followparent_recalc, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1710 | }; |
| 1711 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1712 | /* |
| 1713 | * This clock is a composite clock which does entire set changes then |
| 1714 | * forces a rebalance. It keys on the MPU speed, but it really could |
| 1715 | * be any key speed part of a set in the rate table. |
| 1716 | * |
| 1717 | * to really change a set, you need memory table sets which get changed |
| 1718 | * in sram, pre-notifiers & post notifiers, changing the top set, without |
| 1719 | * having low level display recalc's won't work... this is why dpm notifiers |
| 1720 | * work, isr's off, walk a list of clocks already _off_ and not messing with |
| 1721 | * the bus. |
| 1722 | * |
| 1723 | * This clock should have no parent. It embodies the entire upper level |
| 1724 | * active set. A parent will mess up some of the init also. |
| 1725 | */ |
| 1726 | static struct clk virt_prcm_set = { |
| 1727 | .name = "virt_prcm_set", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 1728 | .ops = &clkops_null, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1729 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1730 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1731 | .set_rate = &omap2_select_table_rate, |
| 1732 | .round_rate = &omap2_round_to_table_rate, |
| 1733 | }; |
Paul Walmsley | e32744b | 2008-03-18 15:47:55 +0200 | [diff] [blame] | 1734 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1735 | |
| 1736 | /* |
| 1737 | * clkdev integration |
| 1738 | */ |
| 1739 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1740 | static struct omap_clk omap2420_clks[] = { |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1741 | /* external root sources */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1742 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), |
| 1743 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), |
| 1744 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), |
| 1745 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), |
| 1746 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1747 | /* internal analog sources */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1748 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), |
| 1749 | CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), |
| 1750 | CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1751 | /* internal prcm root sources */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1752 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), |
| 1753 | CLK(NULL, "core_ck", &core_ck, CK_242X), |
| 1754 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), |
| 1755 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), |
| 1756 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), |
| 1757 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), |
| 1758 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), |
| 1759 | CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1760 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), |
| 1761 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), |
| 1762 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), |
| 1763 | /* mpu domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1764 | CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1765 | /* dsp domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1766 | CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), |
| 1767 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1768 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1769 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), |
| 1770 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), |
| 1771 | /* GFX domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1772 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), |
| 1773 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), |
| 1774 | CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1775 | /* DSS domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1776 | CLK("omapdss", "ick", &dss_ick, CK_242X), |
| 1777 | CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), |
| 1778 | CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), |
| 1779 | CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1780 | /* L3 domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1781 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), |
| 1782 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), |
| 1783 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1784 | /* L4 domain clocks */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1785 | CLK(NULL, "l4_ck", &l4_ck, CK_242X), |
| 1786 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1787 | /* virtual meta-group clock */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1788 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1789 | /* general l4 interface ck, multi-parent functional clk */ |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1790 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), |
| 1791 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), |
| 1792 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), |
| 1793 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), |
| 1794 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), |
| 1795 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), |
| 1796 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), |
| 1797 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), |
| 1798 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), |
| 1799 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), |
| 1800 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), |
| 1801 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), |
| 1802 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), |
| 1803 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), |
| 1804 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), |
| 1805 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), |
| 1806 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), |
| 1807 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), |
| 1808 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), |
| 1809 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), |
| 1810 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), |
| 1811 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), |
| 1812 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), |
| 1813 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), |
| 1814 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), |
| 1815 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X), |
| 1816 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), |
| 1817 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X), |
| 1818 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), |
| 1819 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X), |
| 1820 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), |
| 1821 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X), |
| 1822 | CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), |
| 1823 | CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), |
| 1824 | CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), |
| 1825 | CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), |
| 1826 | CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), |
| 1827 | CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), |
| 1828 | CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), |
| 1829 | CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), |
| 1830 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), |
| 1831 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X), |
| 1832 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), |
| 1833 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), |
| 1834 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), |
| 1835 | CLK("omap24xxcam", "fck", &cam_fck, CK_242X), |
| 1836 | CLK("omap24xxcam", "ick", &cam_ick, CK_242X), |
| 1837 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), |
| 1838 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), |
| 1839 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1840 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), |
| 1841 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1842 | CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), |
| 1843 | CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1844 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), |
| 1845 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1846 | CLK(NULL, "fac_ick", &fac_ick, CK_242X), |
| 1847 | CLK(NULL, "fac_fck", &fac_fck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1848 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), |
| 1849 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1850 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), |
| 1851 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), |
| 1852 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1853 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1854 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1855 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1856 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), |
| 1857 | CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), |
| 1858 | CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1859 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), |
| 1860 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1861 | CLK(NULL, "des_ick", &des_ick, CK_242X), |
| 1862 | CLK(NULL, "sha_ick", &sha_ick, CK_242X), |
| 1863 | CLK("omap_rng", "ick", &rng_ick, CK_242X), |
| 1864 | CLK(NULL, "aes_ick", &aes_ick, CK_242X), |
| 1865 | CLK(NULL, "pka_ick", &pka_ick, CK_242X), |
| 1866 | CLK(NULL, "usb_fck", &usb_fck, CK_242X), |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1867 | }; |
| 1868 | |
| 1869 | /* |
| 1870 | * init code |
| 1871 | */ |
| 1872 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1873 | int __init omap2420_clk_init(void) |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1874 | { |
| 1875 | const struct prcm_config *prcm; |
| 1876 | struct omap_clk *c; |
| 1877 | u32 clkrate; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1878 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1879 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; |
| 1880 | cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); |
| 1881 | cpu_mask = RATE_IN_242X; |
| 1882 | rate_table = omap2420_rate_table; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1883 | |
| 1884 | clk_init(&omap2_clk_functions); |
| 1885 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1886 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); |
| 1887 | c++) |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1888 | clk_preinit(c->lk.clk); |
| 1889 | |
| 1890 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); |
| 1891 | propagate_rate(&osc_ck); |
Paul Walmsley | 44da0a5 | 2010-01-26 20:13:08 -0700 | [diff] [blame] | 1892 | sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1893 | propagate_rate(&sys_ck); |
| 1894 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1895 | for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); |
| 1896 | c++) { |
| 1897 | clkdev_add(&c->lk); |
| 1898 | clk_register(c->lk.clk); |
| 1899 | omap2_init_clk_clkdm(c->lk.clk); |
| 1900 | } |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1901 | |
| 1902 | /* Check the MPU rate set by bootloader */ |
| 1903 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| 1904 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
| 1905 | if (!(prcm->flags & cpu_mask)) |
| 1906 | continue; |
| 1907 | if (prcm->xtal_speed != sys_ck.rate) |
| 1908 | continue; |
| 1909 | if (prcm->dpll_speed <= clkrate) |
| 1910 | break; |
| 1911 | } |
| 1912 | curr_prcm_set = prcm; |
| 1913 | |
| 1914 | recalculate_root_clocks(); |
| 1915 | |
Paul Walmsley | 81b34fb | 2010-02-22 22:09:22 -0700 | [diff] [blame^] | 1916 | pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
| 1917 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, |
| 1918 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 1919 | |
| 1920 | /* |
| 1921 | * Only enable those clocks we will need, let the drivers |
| 1922 | * enable other clocks as necessary |
| 1923 | */ |
| 1924 | clk_enable_init_clocks(); |
| 1925 | |
| 1926 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ |
| 1927 | vclk = clk_get(NULL, "virt_prcm_set"); |
| 1928 | sclk = clk_get(NULL, "sys_ck"); |
| 1929 | dclk = clk_get(NULL, "dpll_ck"); |
| 1930 | |
| 1931 | return 0; |
| 1932 | } |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 1933 | |