blob: d6cc8bf8272e387281c30a0130914c1e961fa69f [file] [log] [blame]
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +02001/*
2 * Device Tree file for Marvell Armada XP evaluation board
3 * (DB-78460-BP)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16/dts-v1/;
Thomas Petazzoni0bec30a2012-09-13 17:41:50 +020017/include/ "armada-xp-mv78460.dtsi"
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020018
19/ {
20 model = "Marvell Armada XP Evaluation Board";
Thomas Petazzoni0bec30a2012-09-13 17:41:50 +020021 compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020022
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
Gregory CLEMENT74898362013-04-12 16:29:10 +020029 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020030 };
31
32 soc {
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020033 internal-regs {
34 serial@12000 {
35 clock-frequency = <250000000>;
Thomas Petazzonibf4f9c62013-04-09 23:06:36 +020036 status = "okay";
37 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020038 serial@12100 {
39 clock-frequency = <250000000>;
Thomas Petazzonibf4f9c62013-04-09 23:06:36 +020040 status = "okay";
41 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020042 serial@12200 {
43 clock-frequency = <250000000>;
Thomas Petazzonibf4f9c62013-04-09 23:06:36 +020044 status = "okay";
45 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020046 serial@12300 {
47 clock-frequency = <250000000>;
Thomas Petazzonibf4f9c62013-04-09 23:06:36 +020048 status = "okay";
49 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020050
51 sata@a0000 {
52 nr-ports = <2>;
Thomas Petazzonibf4f9c62013-04-09 23:06:36 +020053 status = "okay";
54 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020055
56 mdio {
57 phy0: ethernet-phy@0 {
58 reg = <0>;
59 };
60
61 phy1: ethernet-phy@1 {
62 reg = <1>;
63 };
64
65 phy2: ethernet-phy@2 {
66 reg = <25>;
67 };
68
69 phy3: ethernet-phy@3 {
70 reg = <27>;
71 };
72 };
73
74 ethernet@70000 {
Thomas Petazzonibf4f9c62013-04-09 23:06:36 +020075 status = "okay";
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020076 phy = <&phy0>;
77 phy-mode = "rgmii-id";
78 };
79 ethernet@74000 {
80 status = "okay";
81 phy = <&phy1>;
82 phy-mode = "rgmii-id";
83 };
84 ethernet@30000 {
85 status = "okay";
86 phy = <&phy2>;
87 phy-mode = "sgmii";
88 };
89 ethernet@34000 {
90 status = "okay";
91 phy = <&phy3>;
92 phy-mode = "sgmii";
93 };
94
95 mvsdio@d4000 {
96 pinctrl-0 = <&sdio_pins>;
97 pinctrl-names = "default";
98 status = "okay";
99 /* No CD or WP GPIOs */
100 };
101
102 usb@50000 {
103 status = "okay";
104 };
105
106 usb@51000 {
107 status = "okay";
108 };
109
110 usb@52000 {
111 status = "okay";
112 };
113
114 spi0: spi@10600 {
115 status = "okay";
116
117 spi-flash@0 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "m25p64";
121 reg = <0>; /* Chip select 0 */
122 spi-max-frequency = <20000000>;
123 };
124 };
125
126 pcie-controller {
127 status = "okay";
128
129 /*
130 * All 6 slots are physically present as
131 * standard PCIe slots on the board.
132 */
133 pcie@1,0 {
134 /* Port 0, Lane 0 */
135 status = "okay";
136 };
137 pcie@2,0 {
138 /* Port 0, Lane 1 */
139 status = "okay";
140 };
141 pcie@3,0 {
142 /* Port 0, Lane 2 */
143 status = "okay";
144 };
145 pcie@4,0 {
146 /* Port 0, Lane 3 */
147 status = "okay";
148 };
149 pcie@9,0 {
150 /* Port 2, Lane 0 */
151 status = "okay";
152 };
153 pcie@10,0 {
154 /* Port 3, Lane 0 */
155 status = "okay";
156 };
Thomas Petazzonibf4f9c62013-04-09 23:06:36 +0200157 };
158 };
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200159 };
160};