| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1 | /* |
| 2 | cx231xx-reg.h - driver for Conexant Cx23100/101/102 USB video capture devices |
| 3 | |
| 4 | Copyright (C) 2008 <srinivasa.deevi at conexant dot com> |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software |
| 18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | */ |
| 20 | |
| 21 | #ifndef _CX231XX_REG_H |
| 22 | #define _CX231XX_REG_H |
| 23 | |
| 24 | /***************************************************************************** |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 25 | * VBI codes * |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 26 | *****************************************************************************/ |
| 27 | |
| 28 | #define SAV_ACTIVE_VIDEO_FIELD1 0x80 |
| 29 | #define EAV_ACTIVE_VIDEO_FIELD1 0x90 |
| 30 | |
| 31 | #define SAV_ACTIVE_VIDEO_FIELD2 0xC0 |
| 32 | #define EAV_ACTIVE_VIDEO_FIELD2 0xD0 |
| 33 | |
| 34 | #define SAV_VBLANK_FIELD1 0xA0 |
| 35 | #define EAV_VBLANK_FIELD1 0xB0 |
| 36 | |
| 37 | #define SAV_VBLANK_FIELD2 0xE0 |
| 38 | #define EAV_VBLANK_FIELD2 0xF0 |
| 39 | |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 40 | #define SAV_VBI_FIELD1 0x20 |
| 41 | #define EAV_VBI_FIELD1 0x30 |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 42 | |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 43 | #define SAV_VBI_FIELD2 0x60 |
| 44 | #define EAV_VBI_FIELD2 0x70 |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 45 | |
| 46 | /*****************************************************************************/ |
| 47 | /* Audio ADC Registers */ |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 48 | #define CH_PWR_CTRL1 0x0000000E |
| 49 | #define CH_PWR_CTRL2 0x0000000F |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 50 | /*****************************************************************************/ |
| 51 | |
| 52 | #define HOST_REG1 0x000 |
| 53 | #define FLD_FORCE_CHIP_SEL 0x80 |
| 54 | #define FLD_AUTO_INC_DIS 0x20 |
| 55 | #define FLD_PREFETCH_EN 0x10 |
| 56 | /* Reserved [2:3] */ |
| 57 | #define FLD_DIGITAL_PWR_DN 0x02 |
| 58 | #define FLD_SLEEP 0x01 |
| 59 | |
| 60 | /*****************************************************************************/ |
| 61 | #define HOST_REG2 0x001 |
| 62 | |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 63 | /*****************************************************************************/ |
| 64 | #define HOST_REG3 0x002 |
| 65 | |
| 66 | /*****************************************************************************/ |
| 67 | /* added for polaris */ |
| 68 | #define GPIO_PIN_CTL0 0x3 |
| 69 | #define GPIO_PIN_CTL1 0x4 |
| 70 | #define GPIO_PIN_CTL2 0x5 |
| 71 | #define GPIO_PIN_CTL3 0x6 |
| 72 | #define TS1_PIN_CTL0 0x7 |
| 73 | #define TS1_PIN_CTL1 0x8 |
| 74 | /*****************************************************************************/ |
| 75 | |
| 76 | #define FLD_CLK_IN_EN 0x80 |
| 77 | #define FLD_XTAL_CTRL 0x70 |
| 78 | #define FLD_BB_CLK_MODE 0x0C |
| 79 | #define FLD_REF_DIV_PLL 0x02 |
| 80 | #define FLD_REF_SEL_PLL1 0x01 |
| 81 | |
| 82 | /*****************************************************************************/ |
| 83 | #define CHIP_CTRL 0x100 |
| 84 | /* Reserved [27] */ |
| 85 | /* Reserved [31:21] */ |
| 86 | #define FLD_CHIP_ACFG_DIS 0x00100000 |
| 87 | /* Reserved [19] */ |
| 88 | #define FLD_DUAL_MODE_ADC2 0x00040000 |
| 89 | #define FLD_SIF_EN 0x00020000 |
| 90 | #define FLD_SOFT_RST 0x00010000 |
| 91 | #define FLD_DEVICE_ID 0x0000FFFF |
| 92 | |
| 93 | /*****************************************************************************/ |
| 94 | #define AFE_CTRL 0x104 |
| 95 | #define AFE_CTRL_C2HH_SRC_CTRL 0x104 |
| 96 | #define FLD_DIF_OUT_SEL 0xC0000000 |
| 97 | #define FLD_AUX_PLL_CLK_ALT_SEL 0x3C000000 |
| 98 | #define FLD_UV_ORDER_MODE 0x02000000 |
| 99 | #define FLD_FUNC_MODE 0x01800000 |
| 100 | #define FLD_ROT1_PHASE_CTL 0x007F8000 |
| 101 | #define FLD_AUD_IN_SEL 0x00004000 |
| 102 | #define FLD_LUMA_IN_SEL 0x00002000 |
| 103 | #define FLD_CHROMA_IN_SEL 0x00001000 |
| 104 | /* reserve [11:10] */ |
| 105 | #define FLD_INV_SPEC_DIS 0x00000200 |
| 106 | #define FLD_VGA_SEL_CH3 0x00000100 |
| 107 | #define FLD_VGA_SEL_CH2 0x00000080 |
| 108 | #define FLD_VGA_SEL_CH1 0x00000040 |
| 109 | #define FLD_DCR_BYP_CH1 0x00000020 |
| 110 | #define FLD_DCR_BYP_CH2 0x00000010 |
| 111 | #define FLD_DCR_BYP_CH3 0x00000008 |
| 112 | #define FLD_EN_12DB_CH3 0x00000004 |
| 113 | #define FLD_EN_12DB_CH2 0x00000002 |
| 114 | #define FLD_EN_12DB_CH1 0x00000001 |
| 115 | |
| 116 | /* redefine in Cx231xx */ |
| 117 | /*****************************************************************************/ |
| 118 | #define DC_CTRL1 0x108 |
| 119 | /* reserve [31:30] */ |
| 120 | #define FLD_CLAMP_LVL_CH1 0x3FFF8000 |
| 121 | #define FLD_CLAMP_LVL_CH2 0x00007FFF |
| 122 | /*****************************************************************************/ |
| 123 | |
| 124 | /*****************************************************************************/ |
| 125 | #define DC_CTRL2 0x10c |
| 126 | /* reserve [31:28] */ |
| 127 | #define FLD_CLAMP_LVL_CH3 0x00FFFE00 |
| 128 | #define FLD_CLAMP_WIND_LENTH 0x000001E0 |
| 129 | #define FLD_C2HH_SAT_MIN 0x0000001E |
| 130 | #define FLD_FLT_BYP_SEL 0x00000001 |
| 131 | /*****************************************************************************/ |
| 132 | |
| 133 | /*****************************************************************************/ |
| 134 | #define DC_CTRL3 0x110 |
| 135 | /* reserve [31:16] */ |
| 136 | #define FLD_ERR_GAIN_CTL 0x00070000 |
| 137 | #define FLD_LPF_MIN 0x0000FFFF |
| 138 | /*****************************************************************************/ |
| 139 | |
| 140 | /*****************************************************************************/ |
| 141 | #define DC_CTRL4 0x114 |
| 142 | /* reserve [31:31] */ |
| 143 | #define FLD_INTG_CH1 0x7FFFFFFF |
| 144 | /*****************************************************************************/ |
| 145 | |
| 146 | /*****************************************************************************/ |
| 147 | #define DC_CTRL5 0x118 |
| 148 | /* reserve [31:31] */ |
| 149 | #define FLD_INTG_CH2 0x7FFFFFFF |
| 150 | /*****************************************************************************/ |
| 151 | |
| 152 | /*****************************************************************************/ |
| 153 | #define DC_CTRL6 0x11c |
| 154 | /* reserve [31:31] */ |
| 155 | #define FLD_INTG_CH3 0x7FFFFFFF |
| 156 | /*****************************************************************************/ |
| 157 | |
| 158 | /*****************************************************************************/ |
| 159 | #define PIN_CTRL 0x120 |
| 160 | #define FLD_OEF_AGC_RF 0x00000001 |
| 161 | #define FLD_OEF_AGC_IFVGA 0x00000002 |
| 162 | #define FLD_OEF_AGC_IF 0x00000004 |
| 163 | #define FLD_REG_BO_PUD 0x80000000 |
| 164 | #define FLD_IR_IRQ_STAT 0x40000000 |
| 165 | #define FLD_AUD_IRQ_STAT 0x20000000 |
| 166 | #define FLD_VID_IRQ_STAT 0x10000000 |
| 167 | /* Reserved [27:26] */ |
| 168 | #define FLD_IRQ_N_OUT_EN 0x02000000 |
| 169 | #define FLD_IRQ_N_POLAR 0x01000000 |
| 170 | /* Reserved [23:6] */ |
| 171 | #define FLD_OE_AUX_PLL_CLK 0x00000020 |
| 172 | #define FLD_OE_I2S_BCLK 0x00000010 |
| 173 | #define FLD_OE_I2S_WCLK 0x00000008 |
| 174 | #define FLD_OE_AGC_IF 0x00000004 |
| 175 | #define FLD_OE_AGC_IFVGA 0x00000002 |
| 176 | #define FLD_OE_AGC_RF 0x00000001 |
| 177 | |
| 178 | /*****************************************************************************/ |
| 179 | #define AUD_IO_CTRL 0x124 |
| 180 | /* Reserved [31:8] */ |
| 181 | #define FLD_I2S_PORT_DIR 0x00000080 |
| 182 | #define FLD_I2S_OUT_SRC 0x00000040 |
| 183 | #define FLD_AUD_CHAN3_SRC 0x00000030 |
| 184 | #define FLD_AUD_CHAN2_SRC 0x0000000C |
| 185 | #define FLD_AUD_CHAN1_SRC 0x00000003 |
| 186 | |
| 187 | /*****************************************************************************/ |
| 188 | #define AUD_LOCK1 0x128 |
| 189 | #define FLD_AUD_LOCK_KI_SHIFT 0xC0000000 |
| 190 | #define FLD_AUD_LOCK_KD_SHIFT 0x30000000 |
| 191 | /* Reserved [27:25] */ |
| 192 | #define FLD_EN_AV_LOCK 0x01000000 |
| 193 | #define FLD_VID_COUNT 0x00FFFFFF |
| 194 | |
| 195 | /*****************************************************************************/ |
| 196 | #define AUD_LOCK2 0x12C |
| 197 | #define FLD_AUD_LOCK_KI_MULT 0xF0000000 |
| 198 | #define FLD_AUD_LOCK_KD_MULT 0x0F000000 |
| 199 | /* Reserved [23:22] */ |
| 200 | #define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000 |
| 201 | #define FLD_AUD_COUNT 0x000FFFFF |
| 202 | |
| 203 | /*****************************************************************************/ |
| 204 | #define AFE_DIAG_CTRL1 0x134 |
| 205 | /* Reserved [31:16] */ |
| 206 | #define FLD_CUV_DLY_LENGTH 0x0000FF00 |
| 207 | #define FLD_YC_DLY_LENGTH 0x000000FF |
| 208 | |
| 209 | /*****************************************************************************/ |
| 210 | /* Poalris redefine */ |
| 211 | #define AFE_DIAG_CTRL3 0x138 |
| 212 | /* Reserved [31:26] */ |
| 213 | #define FLD_AUD_DUAL_FLAG_POL 0x02000000 |
| 214 | #define FLD_VID_DUAL_FLAG_POL 0x01000000 |
| 215 | /* Reserved [23:23] */ |
| 216 | #define FLD_COL_CLAMP_DIS_CH1 0x00400000 |
| 217 | #define FLD_COL_CLAMP_DIS_CH2 0x00200000 |
| 218 | #define FLD_COL_CLAMP_DIS_CH3 0x00100000 |
| 219 | |
| 220 | #define TEST_CTRL1 0x144 |
| 221 | /* Reserved [31:29] */ |
| 222 | #define FLD_LBIST_EN 0x10000000 |
| 223 | /* Reserved [27:10] */ |
| 224 | #define FLD_FI_BIST_INTR_R 0x0000200 |
| 225 | #define FLD_FI_BIST_INTR_L 0x0000100 |
| 226 | #define FLD_BIST_FAIL_AUD_PLL 0x0000080 |
| 227 | #define FLD_BIST_INTR_AUD_PLL 0x0000040 |
| 228 | #define FLD_BIST_FAIL_VID_PLL 0x0000020 |
| 229 | #define FLD_BIST_INTR_VID_PLL 0x0000010 |
| 230 | /* Reserved [3:1] */ |
| 231 | #define FLD_CIR_TEST_DIS 0x00000001 |
| 232 | |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 233 | /*****************************************************************************/ |
| 234 | #define TEST_CTRL2 0x148 |
| 235 | #define FLD_TSXCLK_POL_CTL 0x80000000 |
| 236 | #define FLD_ISO_CTL_SEL 0x40000000 |
| 237 | #define FLD_ISO_CTL_EN 0x20000000 |
| 238 | #define FLD_BIST_DEBUGZ 0x10000000 |
| 239 | #define FLD_AUD_BIST_TEST_H 0x0F000000 |
| 240 | /* Reserved [23:22] */ |
| 241 | #define FLD_FLTRN_BIST_TEST_H 0x00020000 |
| 242 | #define FLD_VID_BIST_TEST_H 0x00010000 |
| 243 | /* Reserved [19:17] */ |
| 244 | #define FLD_BIST_TEST_H 0x00010000 |
| 245 | /* Reserved [15:13] */ |
| 246 | #define FLD_TAB_EN 0x00001000 |
| 247 | /* Reserved [11:0] */ |
| 248 | |
| 249 | /*****************************************************************************/ |
| 250 | #define BIST_STAT 0x14C |
| 251 | #define FLD_AUD_BIST_FAIL_H 0xFFF00000 |
| 252 | #define FLD_FLTRN_BIST_FAIL_H 0x00180000 |
| 253 | #define FLD_VID_BIST_FAIL_H 0x00070000 |
| 254 | #define FLD_AUD_BIST_TST_DONE 0x0000FFF0 |
| 255 | #define FLD_FLTRN_BIST_TST_DONE 0x00000008 |
| 256 | #define FLD_VID_BIST_TST_DONE 0x00000007 |
| 257 | |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 258 | /*****************************************************************************/ |
| 259 | /* DirectIF registers definition have been moved to DIF_reg.h */ |
| 260 | /*****************************************************************************/ |
| 261 | #define MODE_CTRL 0x400 |
| 262 | #define FLD_AFD_PAL60_DIS 0x20000000 |
| 263 | #define FLD_AFD_FORCE_SECAM 0x10000000 |
| 264 | #define FLD_AFD_FORCE_PALNC 0x08000000 |
| 265 | #define FLD_AFD_FORCE_PAL 0x04000000 |
| 266 | #define FLD_AFD_PALM_SEL 0x03000000 |
| 267 | #define FLD_CKILL_MODE 0x00300000 |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 268 | #define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */ |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 269 | #define FLD_CLR_LOCK_STAT 0x00020000 |
| 270 | #define FLD_FAST_LOCK_MD 0x00010000 |
| 271 | #define FLD_WCEN 0x00008000 |
| 272 | #define FLD_CAGCEN 0x00004000 |
| 273 | #define FLD_CKILLEN 0x00002000 |
| 274 | #define FLD_AUTO_SC_LOCK 0x00001000 |
| 275 | #define FLD_MAN_SC_FAST_LOCK 0x00000800 |
| 276 | #define FLD_INPUT_MODE 0x00000600 |
| 277 | #define FLD_AFD_ACQUIRE 0x00000100 |
| 278 | #define FLD_AFD_NTSC_SEL 0x00000080 |
| 279 | #define FLD_AFD_PAL_SEL 0x00000040 |
| 280 | #define FLD_ACFG_DIS 0x00000020 |
| 281 | #define FLD_SQ_PIXEL 0x00000010 |
| 282 | #define FLD_VID_FMT_SEL 0x0000000F |
| 283 | |
| 284 | /*****************************************************************************/ |
| 285 | #define OUT_CTRL1 0x404 |
| 286 | #define FLD_POLAR 0x7F000000 |
| 287 | /* Reserved [23] */ |
| 288 | #define FLD_RND_MODE 0x00600000 |
| 289 | #define FLD_VIPCLAMP_EN 0x00100000 |
| 290 | #define FLD_VIPBLANK_EN 0x00080000 |
| 291 | #define FLD_VIP_OPT_AL 0x00040000 |
| 292 | #define FLD_IDID0_SOURCE 0x00020000 |
| 293 | #define FLD_DCMODE 0x00010000 |
| 294 | #define FLD_CLK_GATING 0x0000C000 |
| 295 | #define FLD_CLK_INVERT 0x00002000 |
| 296 | #define FLD_HSFMT 0x00001000 |
| 297 | #define FLD_VALIDFMT 0x00000800 |
| 298 | #define FLD_ACTFMT 0x00000400 |
| 299 | #define FLD_SWAPRAW 0x00000200 |
| 300 | #define FLD_CLAMPRAW_EN 0x00000100 |
| 301 | #define FLD_BLUE_FIELD_EN 0x00000080 |
| 302 | #define FLD_BLUE_FIELD_ACT 0x00000040 |
| 303 | #define FLD_TASKBIT_VAL 0x00000020 |
| 304 | #define FLD_ANC_DATA_EN 0x00000010 |
| 305 | #define FLD_VBIHACTRAW_EN 0x00000008 |
| 306 | #define FLD_MODE10B 0x00000004 |
| 307 | #define FLD_OUT_MODE 0x00000003 |
| 308 | |
| 309 | /*****************************************************************************/ |
| 310 | #define OUT_CTRL2 0x408 |
| 311 | #define FLD_AUD_GRP 0xC0000000 |
| 312 | #define FLD_SAMPLE_RATE 0x30000000 |
| 313 | #define FLD_AUD_ANC_EN 0x08000000 |
| 314 | #define FLD_EN_C 0x04000000 |
| 315 | #define FLD_EN_B 0x02000000 |
| 316 | #define FLD_EN_A 0x01000000 |
| 317 | /* Reserved [23:20] */ |
| 318 | #define FLD_IDID1_LSB 0x000C0000 |
| 319 | #define FLD_IDID0_LSB 0x00030000 |
| 320 | #define FLD_IDID1_MSB 0x0000FF00 |
| 321 | #define FLD_IDID0_MSB 0x000000FF |
| 322 | |
| 323 | /*****************************************************************************/ |
| 324 | #define GEN_STAT 0x40C |
| 325 | #define FLD_VCR_DETECT 0x00800000 |
| 326 | #define FLD_SPECIAL_PLAY_N 0x00400000 |
| 327 | #define FLD_VPRES 0x00200000 |
| 328 | #define FLD_AGC_LOCK 0x00100000 |
| 329 | #define FLD_CSC_LOCK 0x00080000 |
| 330 | #define FLD_VLOCK 0x00040000 |
| 331 | #define FLD_SRC_LOCK 0x00020000 |
| 332 | #define FLD_HLOCK 0x00010000 |
| 333 | #define FLD_VSYNC_N 0x00008000 |
| 334 | #define FLD_SRC_FIFO_UFLOW 0x00004000 |
| 335 | #define FLD_SRC_FIFO_OFLOW 0x00002000 |
| 336 | #define FLD_FIELD 0x00001000 |
| 337 | #define FLD_AFD_FMT_STAT 0x00000F00 |
| 338 | #define FLD_MV_TYPE2_PAIR 0x00000080 |
| 339 | #define FLD_MV_T3CS 0x00000040 |
| 340 | #define FLD_MV_CS 0x00000020 |
| 341 | #define FLD_MV_PSP 0x00000010 |
| 342 | /* Reserved [3] */ |
| 343 | #define FLD_MV_CDAT 0x00000003 |
| 344 | |
| 345 | /*****************************************************************************/ |
| 346 | #define INT_STAT_MASK 0x410 |
| 347 | #define FLD_COMB_3D_FIFO_MSK 0x80000000 |
| 348 | #define FLD_WSS_DAT_AVAIL_MSK 0x40000000 |
| 349 | #define FLD_GS2_DAT_AVAIL_MSK 0x20000000 |
| 350 | #define FLD_GS1_DAT_AVAIL_MSK 0x10000000 |
| 351 | #define FLD_CC_DAT_AVAIL_MSK 0x08000000 |
| 352 | #define FLD_VPRES_CHANGE_MSK 0x04000000 |
| 353 | #define FLD_MV_CHANGE_MSK 0x02000000 |
| 354 | #define FLD_END_VBI_EVEN_MSK 0x01000000 |
| 355 | #define FLD_END_VBI_ODD_MSK 0x00800000 |
| 356 | #define FLD_FMT_CHANGE_MSK 0x00400000 |
| 357 | #define FLD_VSYNC_TRAIL_MSK 0x00200000 |
| 358 | #define FLD_HLOCK_CHANGE_MSK 0x00100000 |
| 359 | #define FLD_VLOCK_CHANGE_MSK 0x00080000 |
| 360 | #define FLD_CSC_LOCK_CHANGE_MSK 0x00040000 |
| 361 | #define FLD_SRC_FIFO_UFLOW_MSK 0x00020000 |
| 362 | #define FLD_SRC_FIFO_OFLOW_MSK 0x00010000 |
| 363 | #define FLD_COMB_3D_FIFO_STAT 0x00008000 |
| 364 | #define FLD_WSS_DAT_AVAIL_STAT 0x00004000 |
| 365 | #define FLD_GS2_DAT_AVAIL_STAT 0x00002000 |
| 366 | #define FLD_GS1_DAT_AVAIL_STAT 0x00001000 |
| 367 | #define FLD_CC_DAT_AVAIL_STAT 0x00000800 |
| 368 | #define FLD_VPRES_CHANGE_STAT 0x00000400 |
| 369 | #define FLD_MV_CHANGE_STAT 0x00000200 |
| 370 | #define FLD_END_VBI_EVEN_STAT 0x00000100 |
| 371 | #define FLD_END_VBI_ODD_STAT 0x00000080 |
| 372 | #define FLD_FMT_CHANGE_STAT 0x00000040 |
| 373 | #define FLD_VSYNC_TRAIL_STAT 0x00000020 |
| 374 | #define FLD_HLOCK_CHANGE_STAT 0x00000010 |
| 375 | #define FLD_VLOCK_CHANGE_STAT 0x00000008 |
| 376 | #define FLD_CSC_LOCK_CHANGE_STAT 0x00000004 |
| 377 | #define FLD_SRC_FIFO_UFLOW_STAT 0x00000002 |
| 378 | #define FLD_SRC_FIFO_OFLOW_STAT 0x00000001 |
| 379 | |
| 380 | /*****************************************************************************/ |
| 381 | #define LUMA_CTRL 0x414 |
| 382 | #define BRIGHTNESS_CTRL_BYTE 0x414 |
| 383 | #define CONTRAST_CTRL_BYTE 0x415 |
| 384 | #define LUMA_CTRL_BYTE_3 0x416 |
| 385 | #define FLD_LUMA_CORE_SEL 0x00C00000 |
| 386 | #define FLD_RANGE 0x00300000 |
| 387 | /* Reserved [19] */ |
| 388 | #define FLD_PEAK_EN 0x00040000 |
| 389 | #define FLD_PEAK_SEL 0x00030000 |
| 390 | #define FLD_CNTRST 0x0000FF00 |
| 391 | #define FLD_BRITE 0x000000FF |
| 392 | |
| 393 | /*****************************************************************************/ |
| 394 | #define HSCALE_CTRL 0x418 |
| 395 | #define FLD_HFILT 0x03000000 |
| 396 | #define FLD_HSCALE 0x00FFFFFF |
| 397 | |
| 398 | /*****************************************************************************/ |
| 399 | #define VSCALE_CTRL 0x41C |
| 400 | #define FLD_LINE_AVG_DIS 0x01000000 |
| 401 | /* Reserved [23:20] */ |
| 402 | #define FLD_VS_INTRLACE 0x00080000 |
| 403 | #define FLD_VFILT 0x00070000 |
| 404 | /* Reserved [15:13] */ |
| 405 | #define FLD_VSCALE 0x00001FFF |
| 406 | |
| 407 | /*****************************************************************************/ |
| 408 | #define CHROMA_CTRL 0x420 |
| 409 | #define USAT_CTRL_BYTE 0x420 |
| 410 | #define VSAT_CTRL_BYTE 0x421 |
| 411 | #define HUE_CTRL_BYTE 0x422 |
| 412 | #define FLD_C_LPF_EN 0x20000000 |
| 413 | #define FLD_CHR_DELAY 0x1C000000 |
| 414 | #define FLD_C_CORE_SEL 0x03000000 |
| 415 | #define FLD_HUE 0x00FF0000 |
| 416 | #define FLD_VSAT 0x0000FF00 |
| 417 | #define FLD_USAT 0x000000FF |
| 418 | |
| 419 | /*****************************************************************************/ |
| 420 | #define VBI_LINE_CTRL1 0x424 |
| 421 | #define FLD_VBI_MD_LINE4 0xFF000000 |
| 422 | #define FLD_VBI_MD_LINE3 0x00FF0000 |
| 423 | #define FLD_VBI_MD_LINE2 0x0000FF00 |
| 424 | #define FLD_VBI_MD_LINE1 0x000000FF |
| 425 | |
| 426 | /*****************************************************************************/ |
| 427 | #define VBI_LINE_CTRL2 0x428 |
| 428 | #define FLD_VBI_MD_LINE8 0xFF000000 |
| 429 | #define FLD_VBI_MD_LINE7 0x00FF0000 |
| 430 | #define FLD_VBI_MD_LINE6 0x0000FF00 |
| 431 | #define FLD_VBI_MD_LINE5 0x000000FF |
| 432 | |
| 433 | /*****************************************************************************/ |
| 434 | #define VBI_LINE_CTRL3 0x42C |
| 435 | #define FLD_VBI_MD_LINE12 0xFF000000 |
| 436 | #define FLD_VBI_MD_LINE11 0x00FF0000 |
| 437 | #define FLD_VBI_MD_LINE10 0x0000FF00 |
| 438 | #define FLD_VBI_MD_LINE9 0x000000FF |
| 439 | |
| 440 | /*****************************************************************************/ |
| 441 | #define VBI_LINE_CTRL4 0x430 |
| 442 | #define FLD_VBI_MD_LINE16 0xFF000000 |
| 443 | #define FLD_VBI_MD_LINE15 0x00FF0000 |
| 444 | #define FLD_VBI_MD_LINE14 0x0000FF00 |
| 445 | #define FLD_VBI_MD_LINE13 0x000000FF |
| 446 | |
| 447 | /*****************************************************************************/ |
| 448 | #define VBI_LINE_CTRL5 0x434 |
| 449 | #define FLD_VBI_MD_LINE17 0x000000FF |
| 450 | |
| 451 | /*****************************************************************************/ |
| 452 | #define VBI_FC_CFG 0x438 |
| 453 | #define FLD_FC_ALT2 0xFF000000 |
| 454 | #define FLD_FC_ALT1 0x00FF0000 |
| 455 | #define FLD_FC_ALT2_TYPE 0x0000F000 |
| 456 | #define FLD_FC_ALT1_TYPE 0x00000F00 |
| 457 | /* Reserved [7:1] */ |
| 458 | #define FLD_FC_SEARCH_MODE 0x00000001 |
| 459 | |
| 460 | /*****************************************************************************/ |
| 461 | #define VBI_MISC_CFG1 0x43C |
| 462 | #define FLD_TTX_PKTADRU 0xFFF00000 |
| 463 | #define FLD_TTX_PKTADRL 0x000FFF00 |
| 464 | /* Reserved [7:6] */ |
| 465 | #define FLD_MOJI_PACK_DIS 0x00000020 |
| 466 | #define FLD_VPS_DEC_DIS 0x00000010 |
| 467 | #define FLD_CRI_MARG_SCALE 0x0000000C |
| 468 | #define FLD_EDGE_RESYNC_EN 0x00000002 |
| 469 | #define FLD_ADAPT_SLICE_DIS 0x00000001 |
| 470 | |
| 471 | /*****************************************************************************/ |
| 472 | #define VBI_MISC_CFG2 0x440 |
| 473 | #define FLD_HAMMING_TYPE 0x0F000000 |
| 474 | /* Reserved [23:20] */ |
| 475 | #define FLD_WSS_FIFO_RST 0x00080000 |
| 476 | #define FLD_GS2_FIFO_RST 0x00040000 |
| 477 | #define FLD_GS1_FIFO_RST 0x00020000 |
| 478 | #define FLD_CC_FIFO_RST 0x00010000 |
| 479 | /* Reserved [15:12] */ |
| 480 | #define FLD_VBI3_SDID 0x00000F00 |
| 481 | #define FLD_VBI2_SDID 0x000000F0 |
| 482 | #define FLD_VBI1_SDID 0x0000000F |
| 483 | |
| 484 | /*****************************************************************************/ |
| 485 | #define VBI_PAY1 0x444 |
| 486 | #define FLD_GS1_FIFO_DAT 0xFF000000 |
| 487 | #define FLD_GS1_STAT 0x00FF0000 |
| 488 | #define FLD_CC_FIFO_DAT 0x0000FF00 |
| 489 | #define FLD_CC_STAT 0x000000FF |
| 490 | |
| 491 | /*****************************************************************************/ |
| 492 | #define VBI_PAY2 0x448 |
| 493 | #define FLD_WSS_FIFO_DAT 0xFF000000 |
| 494 | #define FLD_WSS_STAT 0x00FF0000 |
| 495 | #define FLD_GS2_FIFO_DAT 0x0000FF00 |
| 496 | #define FLD_GS2_STAT 0x000000FF |
| 497 | |
| 498 | /*****************************************************************************/ |
| 499 | #define VBI_CUST1_CFG1 0x44C |
| 500 | /* Reserved [31] */ |
| 501 | #define FLD_VBI1_CRIWIN 0x7F000000 |
| 502 | #define FLD_VBI1_SLICE_DIST 0x00F00000 |
| 503 | #define FLD_VBI1_BITINC 0x000FFF00 |
| 504 | #define FLD_VBI1_HDELAY 0x000000FF |
| 505 | |
| 506 | /*****************************************************************************/ |
| 507 | #define VBI_CUST1_CFG2 0x450 |
| 508 | #define FLD_VBI1_FC_LENGTH 0x1F000000 |
| 509 | #define FLD_VBI1_FRAME_CODE 0x00FFFFFF |
| 510 | |
| 511 | /*****************************************************************************/ |
| 512 | #define VBI_CUST1_CFG3 0x454 |
| 513 | #define FLD_VBI1_HAM_EN 0x80000000 |
| 514 | #define FLD_VBI1_FIFO_MODE 0x70000000 |
| 515 | #define FLD_VBI1_FORMAT_TYPE 0x0F000000 |
| 516 | #define FLD_VBI1_PAYLD_LENGTH 0x00FF0000 |
| 517 | #define FLD_VBI1_CRI_LENGTH 0x0000F000 |
| 518 | #define FLD_VBI1_CRI_MARGIN 0x00000F00 |
| 519 | #define FLD_VBI1_CRI_TIME 0x000000FF |
| 520 | |
| 521 | /*****************************************************************************/ |
| 522 | #define VBI_CUST2_CFG1 0x458 |
| 523 | /* Reserved [31] */ |
| 524 | #define FLD_VBI2_CRIWIN 0x7F000000 |
| 525 | #define FLD_VBI2_SLICE_DIST 0x00F00000 |
| 526 | #define FLD_VBI2_BITINC 0x000FFF00 |
| 527 | #define FLD_VBI2_HDELAY 0x000000FF |
| 528 | |
| 529 | /*****************************************************************************/ |
| 530 | #define VBI_CUST2_CFG2 0x45C |
| 531 | #define FLD_VBI2_FC_LENGTH 0x1F000000 |
| 532 | #define FLD_VBI2_FRAME_CODE 0x00FFFFFF |
| 533 | |
| 534 | /*****************************************************************************/ |
| 535 | #define VBI_CUST2_CFG3 0x460 |
| 536 | #define FLD_VBI2_HAM_EN 0x80000000 |
| 537 | #define FLD_VBI2_FIFO_MODE 0x70000000 |
| 538 | #define FLD_VBI2_FORMAT_TYPE 0x0F000000 |
| 539 | #define FLD_VBI2_PAYLD_LENGTH 0x00FF0000 |
| 540 | #define FLD_VBI2_CRI_LENGTH 0x0000F000 |
| 541 | #define FLD_VBI2_CRI_MARGIN 0x00000F00 |
| 542 | #define FLD_VBI2_CRI_TIME 0x000000FF |
| 543 | |
| 544 | /*****************************************************************************/ |
| 545 | #define VBI_CUST3_CFG1 0x464 |
| 546 | /* Reserved [31] */ |
| 547 | #define FLD_VBI3_CRIWIN 0x7F000000 |
| 548 | #define FLD_VBI3_SLICE_DIST 0x00F00000 |
| 549 | #define FLD_VBI3_BITINC 0x000FFF00 |
| 550 | #define FLD_VBI3_HDELAY 0x000000FF |
| 551 | |
| 552 | /*****************************************************************************/ |
| 553 | #define VBI_CUST3_CFG2 0x468 |
| 554 | #define FLD_VBI3_FC_LENGTH 0x1F000000 |
| 555 | #define FLD_VBI3_FRAME_CODE 0x00FFFFFF |
| 556 | |
| 557 | /*****************************************************************************/ |
| 558 | #define VBI_CUST3_CFG3 0x46C |
| 559 | #define FLD_VBI3_HAM_EN 0x80000000 |
| 560 | #define FLD_VBI3_FIFO_MODE 0x70000000 |
| 561 | #define FLD_VBI3_FORMAT_TYPE 0x0F000000 |
| 562 | #define FLD_VBI3_PAYLD_LENGTH 0x00FF0000 |
| 563 | #define FLD_VBI3_CRI_LENGTH 0x0000F000 |
| 564 | #define FLD_VBI3_CRI_MARGIN 0x00000F00 |
| 565 | #define FLD_VBI3_CRI_TIME 0x000000FF |
| 566 | |
| 567 | /*****************************************************************************/ |
| 568 | #define HORIZ_TIM_CTRL 0x470 |
| 569 | #define FLD_BGDEL_CNT 0xFF000000 |
| 570 | /* Reserved [23:22] */ |
| 571 | #define FLD_HACTIVE_CNT 0x003FF000 |
| 572 | /* Reserved [11:10] */ |
| 573 | #define FLD_HBLANK_CNT 0x000003FF |
| 574 | |
| 575 | /*****************************************************************************/ |
| 576 | #define VERT_TIM_CTRL 0x474 |
| 577 | #define FLD_V656BLANK_CNT 0xFF000000 |
| 578 | /* Reserved [23:22] */ |
| 579 | #define FLD_VACTIVE_CNT 0x003FF000 |
| 580 | /* Reserved [11:10] */ |
| 581 | #define FLD_VBLANK_CNT 0x000003FF |
| 582 | |
| 583 | /*****************************************************************************/ |
| 584 | #define SRC_COMB_CFG 0x478 |
| 585 | #define FLD_CCOMB_2LN_CHECK 0x80000000 |
| 586 | #define FLD_CCOMB_3LN_EN 0x40000000 |
| 587 | #define FLD_CCOMB_2LN_EN 0x20000000 |
| 588 | #define FLD_CCOMB_3D_EN 0x10000000 |
| 589 | /* Reserved [27] */ |
| 590 | #define FLD_LCOMB_3LN_EN 0x04000000 |
| 591 | #define FLD_LCOMB_2LN_EN 0x02000000 |
| 592 | #define FLD_LCOMB_3D_EN 0x01000000 |
| 593 | #define FLD_LUMA_LPF_SEL 0x00C00000 |
| 594 | #define FLD_UV_LPF_SEL 0x00300000 |
| 595 | #define FLD_BLEND_SLOPE 0x000F0000 |
| 596 | #define FLD_CCOMB_REDUCE_EN 0x00008000 |
| 597 | /* Reserved [14:10] */ |
| 598 | #define FLD_SRC_DECIM_RATIO 0x000003FF |
| 599 | |
| 600 | /*****************************************************************************/ |
| 601 | #define CHROMA_VBIOFF_CFG 0x47C |
| 602 | #define FLD_VBI_VOFFSET 0x1F000000 |
| 603 | /* Reserved [23:20] */ |
| 604 | #define FLD_SC_STEP 0x000FFFFF |
| 605 | |
| 606 | /*****************************************************************************/ |
| 607 | #define FIELD_COUNT 0x480 |
| 608 | #define FLD_FIELD_COUNT_FLD 0x000003FF |
| 609 | |
| 610 | /*****************************************************************************/ |
| 611 | #define MISC_TIM_CTRL 0x484 |
| 612 | #define FLD_DEBOUNCE_COUNT 0xC0000000 |
| 613 | #define FLD_VT_LINE_CNT_HYST 0x30000000 |
| 614 | /* Reserved [27] */ |
| 615 | #define FLD_AFD_STAT 0x07FF0000 |
| 616 | #define FLD_VPRES_VERT_EN 0x00008000 |
| 617 | /* Reserved [14:12] */ |
| 618 | #define FLD_HR32 0x00000800 |
| 619 | #define FLD_TDALGN 0x00000400 |
| 620 | #define FLD_TDFIELD 0x00000200 |
| 621 | /* Reserved [8:6] */ |
| 622 | #define FLD_TEMPDEC 0x0000003F |
| 623 | |
| 624 | /*****************************************************************************/ |
| 625 | #define DFE_CTRL1 0x488 |
| 626 | #define FLD_CLAMP_AUTO_EN 0x80000000 |
| 627 | #define FLD_AGC_AUTO_EN 0x40000000 |
| 628 | #define FLD_VGA_CRUSH_EN 0x20000000 |
| 629 | #define FLD_VGA_AUTO_EN 0x10000000 |
| 630 | #define FLD_VBI_GATE_EN 0x08000000 |
| 631 | #define FLD_CLAMP_LEVEL 0x07000000 |
| 632 | /* Reserved [23:22] */ |
| 633 | #define FLD_CLAMP_SKIP_CNT 0x00300000 |
| 634 | #define FLD_AGC_GAIN 0x000FFF00 |
| 635 | /* Reserved [7:6] */ |
| 636 | #define FLD_VGA_GAIN 0x0000003F |
| 637 | |
| 638 | /*****************************************************************************/ |
| 639 | #define DFE_CTRL2 0x48C |
| 640 | #define FLD_VGA_ACQUIRE_RANGE 0x00FF0000 |
| 641 | #define FLD_VGA_TRACK_RANGE 0x0000FF00 |
| 642 | #define FLD_VGA_SYNC 0x000000FF |
| 643 | |
| 644 | /*****************************************************************************/ |
| 645 | #define DFE_CTRL3 0x490 |
| 646 | #define FLD_BP_PERCENT 0xFF000000 |
| 647 | #define FLD_DFT_THRESHOLD 0x00FF0000 |
| 648 | /* Reserved [15:12] */ |
| 649 | #define FLD_SYNC_WIDTH_SEL 0x00000600 |
| 650 | #define FLD_BP_LOOP_GAIN 0x00000300 |
| 651 | #define FLD_SYNC_LOOP_GAIN 0x000000C0 |
| 652 | /* Reserved [5:4] */ |
| 653 | #define FLD_AGC_LOOP_GAIN 0x0000000C |
| 654 | #define FLD_DCC_LOOP_GAIN 0x00000003 |
| 655 | |
| 656 | /*****************************************************************************/ |
| 657 | #define PLL_CTRL 0x494 |
| 658 | #define FLD_PLL_KD 0xFF000000 |
| 659 | #define FLD_PLL_KI 0x00FF0000 |
| 660 | #define FLD_PLL_MAX_OFFSET 0x0000FFFF |
| 661 | |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 662 | /*****************************************************************************/ |
| 663 | #define HTL_CTRL 0x498 |
| 664 | /* Reserved [31:24] */ |
| 665 | #define FLD_AUTO_LOCK_SPD 0x00080000 |
| 666 | #define FLD_MAN_FAST_LOCK 0x00040000 |
| 667 | #define FLD_HTL_15K_EN 0x00020000 |
| 668 | #define FLD_HTL_500K_EN 0x00010000 |
| 669 | #define FLD_HTL_KD 0x0000FF00 |
| 670 | #define FLD_HTL_KI 0x000000FF |
| 671 | |
| 672 | /*****************************************************************************/ |
| 673 | #define COMB_CTRL 0x49C |
| 674 | #define FLD_COMB_PHASE_LIMIT 0xFF000000 |
| 675 | #define FLD_CCOMB_ERR_LIMIT 0x00FF0000 |
| 676 | #define FLD_LUMA_THRESHOLD 0x0000FF00 |
| 677 | #define FLD_LCOMB_ERR_LIMIT 0x000000FF |
| 678 | |
| 679 | /*****************************************************************************/ |
| 680 | #define CRUSH_CTRL 0x4A0 |
| 681 | #define FLD_WTW_EN 0x00400000 |
| 682 | #define FLD_CRUSH_FREQ 0x00200000 |
| 683 | #define FLD_MAJ_SEL_EN 0x00100000 |
| 684 | #define FLD_MAJ_SEL 0x000C0000 |
| 685 | /* Reserved [17:15] */ |
| 686 | #define FLD_SYNC_TIP_REDUCE 0x00007E00 |
| 687 | /* Reserved [8:6] */ |
| 688 | #define FLD_SYNC_TIP_INC 0x0000003F |
| 689 | |
| 690 | /*****************************************************************************/ |
| 691 | #define SOFT_RST_CTRL 0x4A4 |
| 692 | #define FLD_VD_SOFT_RST 0x00008000 |
| 693 | /* Reserved [14:12] */ |
| 694 | #define FLD_REG_RST_MSK 0x00000800 |
| 695 | #define FLD_VOF_RST_MSK 0x00000400 |
| 696 | #define FLD_MVDET_RST_MSK 0x00000200 |
| 697 | #define FLD_VBI_RST_MSK 0x00000100 |
| 698 | #define FLD_SCALE_RST_MSK 0x00000080 |
| 699 | #define FLD_CHROMA_RST_MSK 0x00000040 |
| 700 | #define FLD_LUMA_RST_MSK 0x00000020 |
| 701 | #define FLD_VTG_RST_MSK 0x00000010 |
| 702 | #define FLD_YCSEP_RST_MSK 0x00000008 |
| 703 | #define FLD_SRC_RST_MSK 0x00000004 |
| 704 | #define FLD_DFE_RST_MSK 0x00000002 |
| 705 | /* Reserved [0] */ |
| 706 | |
| 707 | /*****************************************************************************/ |
| 708 | #define MV_DT_CTRL1 0x4A8 |
| 709 | /* Reserved [31:29] */ |
| 710 | #define FLD_PSP_STOP_LINE 0x1F000000 |
| 711 | /* Reserved [23:21] */ |
| 712 | #define FLD_PSP_STRT_LINE 0x001F0000 |
| 713 | /* Reserved [15] */ |
| 714 | #define FLD_PSP_LLIMW 0x00007F00 |
| 715 | /* Reserved [7] */ |
| 716 | #define FLD_PSP_ULIMW 0x0000007F |
| 717 | |
| 718 | /*****************************************************************************/ |
| 719 | #define MV_DT_CTRL2 0x4AC |
| 720 | #define FLD_CS_STOPWIN 0xFF000000 |
| 721 | #define FLD_CS_STRTWIN 0x00FF0000 |
| 722 | #define FLD_CS_WIDTH 0x0000FF00 |
| 723 | #define FLD_PSP_SPEC_VAL 0x000000FF |
| 724 | |
| 725 | /*****************************************************************************/ |
| 726 | #define MV_DT_CTRL3 0x4B0 |
| 727 | #define FLD_AUTO_RATE_DIS 0x80000000 |
| 728 | #define FLD_HLOCK_DIS 0x40000000 |
| 729 | #define FLD_SEL_FIELD_CNT 0x20000000 |
| 730 | #define FLD_CS_TYPE2_SEL 0x10000000 |
| 731 | #define FLD_CS_LINE_THRSH_SEL 0x08000000 |
| 732 | #define FLD_CS_ATHRESH_SEL 0x04000000 |
| 733 | #define FLD_PSP_SPEC_SEL 0x02000000 |
| 734 | #define FLD_PSP_LINES_SEL 0x01000000 |
| 735 | #define FLD_FIELD_CNT 0x00F00000 |
| 736 | #define FLD_CS_TYPE2_CNT 0x000FC000 |
| 737 | #define FLD_CS_LINE_CNT 0x00003F00 |
| 738 | #define FLD_CS_ATHRESH_LEV 0x000000FF |
| 739 | |
| 740 | /*****************************************************************************/ |
| 741 | #define CHIP_VERSION 0x4B4 |
| 742 | /* Cx231xx redefine */ |
| 743 | #define VERSION 0x4B4 |
| 744 | #define FLD_REV_ID 0x000000FF |
| 745 | |
| 746 | /*****************************************************************************/ |
| 747 | #define MISC_DIAG_CTRL 0x4B8 |
| 748 | /* Reserved [31:24] */ |
| 749 | #define FLD_SC_CONVERGE_THRESH 0x00FF0000 |
| 750 | #define FLD_CCOMB_ERR_LIMIT_3D 0x0000FF00 |
| 751 | #define FLD_LCOMB_ERR_LIMIT_3D 0x000000FF |
| 752 | |
| 753 | /*****************************************************************************/ |
| 754 | #define VBI_PASS_CTRL 0x4BC |
| 755 | #define FLD_VBI_PASS_MD 0x00200000 |
| 756 | #define FLD_VBI_SETUP_DIS 0x00100000 |
| 757 | #define FLD_PASS_LINE_CTRL 0x000FFFFF |
| 758 | |
| 759 | /*****************************************************************************/ |
| 760 | /* Cx231xx redefine */ |
| 761 | #define VCR_DET_CTRL 0x4c0 |
| 762 | #define FLD_EN_FIELD_PHASE_DET 0x80000000 |
| 763 | #define FLD_EN_HEAD_SW_DET 0x40000000 |
| 764 | #define FLD_FIELD_PHASE_LENGTH 0x01FF0000 |
| 765 | /* Reserved [29:25] */ |
| 766 | #define FLD_FIELD_PHASE_DELAY 0x0000FF00 |
| 767 | #define FLD_FIELD_PHASE_LIMIT 0x000000F0 |
| 768 | #define FLD_HEAD_SW_DET_LIMIT 0x0000000F |
| 769 | |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 770 | /*****************************************************************************/ |
| 771 | #define DL_CTL 0x800 |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 772 | #define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ |
| 773 | #define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ |
| 774 | #define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ |
| 775 | #define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 776 | /* Reserved [31:5] */ |
| 777 | #define FLD_START_8051 0x10000000 |
| 778 | #define FLD_DL_ENABLE 0x08000000 |
| 779 | #define FLD_DL_AUTO_INC 0x04000000 |
| 780 | #define FLD_DL_MAP 0x03000000 |
| 781 | |
| 782 | /*****************************************************************************/ |
| 783 | #define STD_DET_STATUS 0x804 |
| 784 | #define FLD_SPARE_STATUS1 0xFF000000 |
| 785 | #define FLD_SPARE_STATUS0 0x00FF0000 |
| 786 | #define FLD_MOD_DET_STATUS1 0x0000FF00 |
| 787 | #define FLD_MOD_DET_STATUS0 0x000000FF |
| 788 | |
| 789 | /*****************************************************************************/ |
| 790 | #define AUD_BUILD_NUM 0x806 |
| 791 | #define AUD_VER_NUM 0x807 |
| 792 | #define STD_DET_CTL 0x808 |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 793 | #define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ |
| 794 | #define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 795 | #define FLD_SPARE_CTL0 0xFF000000 |
| 796 | #define FLD_DIS_DBX 0x00800000 |
| 797 | #define FLD_DIS_BTSC 0x00400000 |
| 798 | #define FLD_DIS_NICAM_A2 0x00200000 |
| 799 | #define FLD_VIDEO_PRESENT 0x00100000 |
| 800 | #define FLD_DW8051_VIDEO_FORMAT 0x000F0000 |
| 801 | #define FLD_PREF_DEC_MODE 0x0000FF00 |
| 802 | #define FLD_AUD_CONFIG 0x000000FF |
| 803 | |
| 804 | /*****************************************************************************/ |
| 805 | #define DW8051_INT 0x80C |
| 806 | #define FLD_VIDEO_PRESENT_CHANGE 0x80000000 |
| 807 | #define FLD_VIDEO_CHANGE 0x40000000 |
| 808 | #define FLD_RDS_READY 0x20000000 |
| 809 | #define FLD_AC97_INT 0x10000000 |
| 810 | #define FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000 |
| 811 | #define FLD_NICAM_LOCK 0x04000000 |
| 812 | #define FLD_NICAM_UNLOCK 0x02000000 |
| 813 | #define FLD_DFT4_TH_CMP 0x01000000 |
| 814 | /* Reserved [23:22] */ |
| 815 | #define FLD_LOCK_IND_INT 0x00200000 |
| 816 | #define FLD_DFT3_TH_CMP 0x00100000 |
| 817 | #define FLD_DFT2_TH_CMP 0x00080000 |
| 818 | #define FLD_DFT1_TH_CMP 0x00040000 |
| 819 | #define FLD_FM2_DFT_TH_CMP 0x00020000 |
| 820 | #define FLD_FM1_DFT_TH_CMP 0x00010000 |
| 821 | #define FLD_VIDEO_PRESENT_EN 0x00008000 |
| 822 | #define FLD_VIDEO_CHANGE_EN 0x00004000 |
| 823 | #define FLD_RDS_READY_EN 0x00002000 |
| 824 | #define FLD_AC97_INT_EN 0x00001000 |
| 825 | #define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800 |
| 826 | #define FLD_NICAM_LOCK_EN 0x00000400 |
| 827 | #define FLD_NICAM_UNLOCK_EN 0x00000200 |
| 828 | #define FLD_DFT4_TH_CMP_EN 0x00000100 |
| 829 | /* Reserved [7] */ |
| 830 | #define FLD_DW8051_INT6_CTL1 0x00000040 |
| 831 | #define FLD_DW8051_INT5_CTL1 0x00000020 |
| 832 | #define FLD_DW8051_INT4_CTL1 0x00000010 |
| 833 | #define FLD_DW8051_INT3_CTL1 0x00000008 |
| 834 | #define FLD_DW8051_INT2_CTL1 0x00000004 |
| 835 | #define FLD_DW8051_INT1_CTL1 0x00000002 |
| 836 | #define FLD_DW8051_INT0_CTL1 0x00000001 |
| 837 | |
| 838 | /*****************************************************************************/ |
| 839 | #define GENERAL_CTL 0x810 |
| 840 | #define FLD_RDS_INT 0x80000000 |
| 841 | #define FLD_NBER_INT 0x40000000 |
| 842 | #define FLD_NLL_INT 0x20000000 |
| 843 | #define FLD_IFL_INT 0x10000000 |
| 844 | #define FLD_FDL_INT 0x08000000 |
| 845 | #define FLD_AFC_INT 0x04000000 |
| 846 | #define FLD_AMC_INT 0x02000000 |
| 847 | #define FLD_AC97_INT_CTL 0x01000000 |
| 848 | #define FLD_RDS_INT_DIS 0x00800000 |
| 849 | #define FLD_NBER_INT_DIS 0x00400000 |
| 850 | #define FLD_NLL_INT_DIS 0x00200000 |
| 851 | #define FLD_IFL_INT_DIS 0x00100000 |
| 852 | #define FLD_FDL_INT_DIS 0x00080000 |
| 853 | #define FLD_FC_INT_DIS 0x00040000 |
| 854 | #define FLD_AMC_INT_DIS 0x00020000 |
| 855 | #define FLD_AC97_INT_DIS 0x00010000 |
| 856 | #define FLD_REV_NUM 0x0000FF00 |
| 857 | /* Reserved [7:5] */ |
| 858 | #define FLD_DBX_SOFT_RESET_REG 0x00000010 |
| 859 | #define FLD_AD_SOFT_RESET_REG 0x00000008 |
| 860 | #define FLD_SRC_SOFT_RESET_REG 0x00000004 |
| 861 | #define FLD_CDMOD_SOFT_RESET 0x00000002 |
| 862 | #define FLD_8051_SOFT_RESET 0x00000001 |
| 863 | |
| 864 | /*****************************************************************************/ |
| 865 | #define AAGC_CTL 0x814 |
| 866 | #define FLD_AFE_12DB_EN 0x80000000 |
| 867 | #define FLD_AAGC_DEFAULT_EN 0x40000000 |
| 868 | #define FLD_AAGC_DEFAULT 0x3F000000 |
| 869 | /* Reserved [23] */ |
| 870 | #define FLD_AAGC_GAIN 0x00600000 |
| 871 | #define FLD_AAGC_TH 0x001F0000 |
| 872 | /* Reserved [15:14] */ |
| 873 | #define FLD_AAGC_HYST2 0x00003F00 |
| 874 | /* Reserved [7:6] */ |
| 875 | #define FLD_AAGC_HYST1 0x0000003F |
| 876 | |
| 877 | /*****************************************************************************/ |
| 878 | #define IF_SRC_CTL 0x818 |
| 879 | #define FLD_DBX_BYPASS 0x80000000 |
| 880 | /* Reserved [30:25] */ |
| 881 | #define FLD_IF_SRC_MODE 0x01000000 |
| 882 | /* Reserved [23:18] */ |
| 883 | #define FLD_IF_SRC_PHASE_INC 0x0001FFFF |
| 884 | |
| 885 | /*****************************************************************************/ |
| 886 | #define ANALOG_DEMOD_CTL 0x81C |
| 887 | #define FLD_ROT1_PHACC_PROG 0xFFFF0000 |
| 888 | /* Reserved [15] */ |
| 889 | #define FLD_FM1_DELAY_FIX 0x00007000 |
| 890 | #define FLD_PDF4_SHIFT 0x00000C00 |
| 891 | #define FLD_PDF3_SHIFT 0x00000300 |
| 892 | #define FLD_PDF2_SHIFT 0x000000C0 |
| 893 | #define FLD_PDF1_SHIFT 0x00000030 |
| 894 | #define FLD_FMBYPASS_MODE2 0x00000008 |
| 895 | #define FLD_FMBYPASS_MODE1 0x00000004 |
| 896 | #define FLD_NICAM_MODE 0x00000002 |
| 897 | #define FLD_BTSC_FMRADIO_MODE 0x00000001 |
| 898 | |
| 899 | /*****************************************************************************/ |
| 900 | #define ROT_FREQ_CTL 0x820 |
| 901 | #define FLD_ROT3_PHACC_PROG 0xFFFF0000 |
| 902 | #define FLD_ROT2_PHACC_PROG 0x0000FFFF |
| 903 | |
| 904 | /*****************************************************************************/ |
| 905 | #define FM_CTL 0x824 |
| 906 | #define FLD_FM2_DC_FB_SHIFT 0xF0000000 |
| 907 | #define FLD_FM2_DC_INT_SHIFT 0x0F000000 |
| 908 | #define FLD_FM2_AFC_RESET 0x00800000 |
| 909 | #define FLD_FM2_DC_PASS_IN 0x00400000 |
| 910 | #define FLD_FM2_DAGC_SHIFT 0x00380000 |
| 911 | #define FLD_FM2_CORDIC_SHIFT 0x00070000 |
| 912 | #define FLD_FM1_DC_FB_SHIFT 0x0000F000 |
| 913 | #define FLD_FM1_DC_INT_SHIFT 0x00000F00 |
| 914 | #define FLD_FM1_AFC_RESET 0x00000080 |
| 915 | #define FLD_FM1_DC_PASS_IN 0x00000040 |
| 916 | #define FLD_FM1_DAGC_SHIFT 0x00000038 |
| 917 | #define FLD_FM1_CORDIC_SHIFT 0x00000007 |
| 918 | |
| 919 | /*****************************************************************************/ |
| 920 | #define LPF_PDF_CTL 0x828 |
| 921 | /* Reserved [31:30] */ |
| 922 | #define FLD_LPF32_SHIFT1 0x30000000 |
| 923 | #define FLD_LPF32_SHIFT2 0x0C000000 |
| 924 | #define FLD_LPF160_SHIFTA 0x03000000 |
| 925 | #define FLD_LPF160_SHIFTB 0x00C00000 |
| 926 | #define FLD_LPF160_SHIFTC 0x00300000 |
| 927 | #define FLD_LPF32_COEF_SEL2 0x000C0000 |
| 928 | #define FLD_LPF32_COEF_SEL1 0x00030000 |
| 929 | #define FLD_LPF160_COEF_SELC 0x0000C000 |
| 930 | #define FLD_LPF160_COEF_SELB 0x00003000 |
| 931 | #define FLD_LPF160_COEF_SELA 0x00000C00 |
| 932 | #define FLD_LPF160_IN_EN_REG 0x00000300 |
| 933 | #define FLD_PDF4_PDF_SEL 0x000000C0 |
| 934 | #define FLD_PDF3_PDF_SEL 0x00000030 |
| 935 | #define FLD_PDF2_PDF_SEL 0x0000000C |
| 936 | #define FLD_PDF1_PDF_SEL 0x00000003 |
| 937 | |
| 938 | /*****************************************************************************/ |
| 939 | #define DFT1_CTL1 0x82C |
| 940 | #define FLD_DFT1_DWELL 0xFFFF0000 |
| 941 | #define FLD_DFT1_FREQ 0x0000FFFF |
| 942 | |
| 943 | /*****************************************************************************/ |
| 944 | #define DFT1_CTL2 0x830 |
| 945 | #define FLD_DFT1_THRESHOLD 0xFFFFFF00 |
| 946 | #define FLD_DFT1_CMP_CTL 0x00000080 |
| 947 | #define FLD_DFT1_AVG 0x00000070 |
| 948 | /* Reserved [3:1] */ |
| 949 | #define FLD_DFT1_START 0x00000001 |
| 950 | |
| 951 | /*****************************************************************************/ |
| 952 | #define DFT1_STATUS 0x834 |
| 953 | #define FLD_DFT1_DONE 0x80000000 |
| 954 | #define FLD_DFT1_TH_CMP_STAT 0x40000000 |
| 955 | #define FLD_DFT1_RESULT 0x3FFFFFFF |
| 956 | |
| 957 | /*****************************************************************************/ |
| 958 | #define DFT2_CTL1 0x838 |
| 959 | #define FLD_DFT2_DWELL 0xFFFF0000 |
| 960 | #define FLD_DFT2_FREQ 0x0000FFFF |
| 961 | |
| 962 | /*****************************************************************************/ |
| 963 | #define DFT2_CTL2 0x83C |
| 964 | #define FLD_DFT2_THRESHOLD 0xFFFFFF00 |
| 965 | #define FLD_DFT2_CMP_CTL 0x00000080 |
| 966 | #define FLD_DFT2_AVG 0x00000070 |
| 967 | /* Reserved [3:1] */ |
| 968 | #define FLD_DFT2_START 0x00000001 |
| 969 | |
| 970 | /*****************************************************************************/ |
| 971 | #define DFT2_STATUS 0x840 |
| 972 | #define FLD_DFT2_DONE 0x80000000 |
| 973 | #define FLD_DFT2_TH_CMP_STAT 0x40000000 |
| 974 | #define FLD_DFT2_RESULT 0x3FFFFFFF |
| 975 | |
| 976 | /*****************************************************************************/ |
| 977 | #define DFT3_CTL1 0x844 |
| 978 | #define FLD_DFT3_DWELL 0xFFFF0000 |
| 979 | #define FLD_DFT3_FREQ 0x0000FFFF |
| 980 | |
| 981 | /*****************************************************************************/ |
| 982 | #define DFT3_CTL2 0x848 |
| 983 | #define FLD_DFT3_THRESHOLD 0xFFFFFF00 |
| 984 | #define FLD_DFT3_CMP_CTL 0x00000080 |
| 985 | #define FLD_DFT3_AVG 0x00000070 |
| 986 | /* Reserved [3:1] */ |
| 987 | #define FLD_DFT3_START 0x00000001 |
| 988 | |
| 989 | /*****************************************************************************/ |
| 990 | #define DFT3_STATUS 0x84C |
| 991 | #define FLD_DFT3_DONE 0x80000000 |
| 992 | #define FLD_DFT3_TH_CMP_STAT 0x40000000 |
| 993 | #define FLD_DFT3_RESULT 0x3FFFFFFF |
| 994 | |
| 995 | /*****************************************************************************/ |
| 996 | #define DFT4_CTL1 0x850 |
| 997 | #define FLD_DFT4_DWELL 0xFFFF0000 |
| 998 | #define FLD_DFT4_FREQ 0x0000FFFF |
| 999 | |
| 1000 | /*****************************************************************************/ |
| 1001 | #define DFT4_CTL2 0x854 |
| 1002 | #define FLD_DFT4_THRESHOLD 0xFFFFFF00 |
| 1003 | #define FLD_DFT4_CMP_CTL 0x00000080 |
| 1004 | #define FLD_DFT4_AVG 0x00000070 |
| 1005 | /* Reserved [3:1] */ |
| 1006 | #define FLD_DFT4_START 0x00000001 |
| 1007 | |
| 1008 | /*****************************************************************************/ |
| 1009 | #define DFT4_STATUS 0x858 |
| 1010 | #define FLD_DFT4_DONE 0x80000000 |
| 1011 | #define FLD_DFT4_TH_CMP_STAT 0x40000000 |
| 1012 | #define FLD_DFT4_RESULT 0x3FFFFFFF |
| 1013 | |
| 1014 | /*****************************************************************************/ |
| 1015 | #define AM_MTS_DET 0x85C |
| 1016 | #define FLD_AM_MTS_MODE 0x80000000 |
| 1017 | /* Reserved [30:26] */ |
| 1018 | #define FLD_AM_SUB 0x02000000 |
| 1019 | #define FLD_AM_GAIN_EN 0x01000000 |
| 1020 | /* Reserved [23:16] */ |
| 1021 | #define FLD_AMMTS_GAIN_SCALE 0x0000E000 |
| 1022 | #define FLD_MTS_PDF_SHIFT 0x00001800 |
| 1023 | #define FLD_AM_REG_GAIN 0x00000700 |
| 1024 | #define FLD_AGC_REF 0x000000FF |
| 1025 | |
| 1026 | /*****************************************************************************/ |
| 1027 | #define ANALOG_MUX_CTL 0x860 |
| 1028 | /* Reserved [31:29] */ |
| 1029 | #define FLD_MUX21_SEL 0x10000000 |
| 1030 | #define FLD_MUX20_SEL 0x08000000 |
| 1031 | #define FLD_MUX19_SEL 0x04000000 |
| 1032 | #define FLD_MUX18_SEL 0x02000000 |
| 1033 | #define FLD_MUX17_SEL 0x01000000 |
| 1034 | #define FLD_MUX16_SEL 0x00800000 |
| 1035 | #define FLD_MUX15_SEL 0x00400000 |
| 1036 | #define FLD_MUX14_SEL 0x00300000 |
| 1037 | #define FLD_MUX13_SEL 0x000C0000 |
| 1038 | #define FLD_MUX12_SEL 0x00020000 |
| 1039 | #define FLD_MUX11_SEL 0x00018000 |
| 1040 | #define FLD_MUX10_SEL 0x00004000 |
| 1041 | #define FLD_MUX9_SEL 0x00002000 |
| 1042 | #define FLD_MUX8_SEL 0x00001000 |
| 1043 | #define FLD_MUX7_SEL 0x00000800 |
| 1044 | #define FLD_MUX6_SEL 0x00000600 |
| 1045 | #define FLD_MUX5_SEL 0x00000100 |
| 1046 | #define FLD_MUX4_SEL 0x000000C0 |
| 1047 | #define FLD_MUX3_SEL 0x00000030 |
| 1048 | #define FLD_MUX2_SEL 0x0000000C |
| 1049 | #define FLD_MUX1_SEL 0x00000003 |
| 1050 | |
| 1051 | /*****************************************************************************/ |
| 1052 | /* Cx231xx redefine */ |
| 1053 | #define DPLL_CTRL1 0x864 |
| 1054 | #define DIG_PLL_CTL1 0x864 |
| 1055 | |
| 1056 | #define FLD_PLL_STATUS 0x07000000 |
| 1057 | #define FLD_BANDWIDTH_SELECT 0x00030000 |
| 1058 | #define FLD_PLL_SHIFT_REG 0x00007000 |
| 1059 | #define FLD_PHASE_SHIFT 0x000007FF |
| 1060 | |
| 1061 | /*****************************************************************************/ |
| 1062 | /* Cx231xx redefine */ |
| 1063 | #define DPLL_CTRL2 0x868 |
| 1064 | #define DIG_PLL_CTL2 0x868 |
| 1065 | #define FLD_PLL_UNLOCK_THR 0xFF000000 |
| 1066 | #define FLD_PLL_LOCK_THR 0x00FF0000 |
| 1067 | /* Reserved [15:8] */ |
| 1068 | #define FLD_AM_PDF_SEL2 0x000000C0 |
| 1069 | #define FLD_AM_PDF_SEL1 0x00000030 |
| 1070 | #define FLD_DPLL_FSM_CTRL 0x0000000C |
| 1071 | /* Reserved [1] */ |
| 1072 | #define FLD_PLL_PILOT_DET 0x00000001 |
| 1073 | |
| 1074 | /*****************************************************************************/ |
| 1075 | /* Cx231xx redefine */ |
| 1076 | #define DPLL_CTRL3 0x86C |
| 1077 | #define DIG_PLL_CTL3 0x86C |
| 1078 | #define FLD_DISABLE_LOOP 0x01000000 |
| 1079 | #define FLD_A1_DS1_SEL 0x000C0000 |
| 1080 | #define FLD_A1_DS2_SEL 0x00030000 |
| 1081 | #define FLD_A1_KI 0x0000FF00 |
| 1082 | #define FLD_A1_KD 0x000000FF |
| 1083 | |
| 1084 | /*****************************************************************************/ |
| 1085 | /* Cx231xx redefine */ |
| 1086 | #define DPLL_CTRL4 0x870 |
| 1087 | #define DIG_PLL_CTL4 0x870 |
| 1088 | #define FLD_A2_DS1_SEL 0x000C0000 |
| 1089 | #define FLD_A2_DS2_SEL 0x00030000 |
| 1090 | #define FLD_A2_KI 0x0000FF00 |
| 1091 | #define FLD_A2_KD 0x000000FF |
| 1092 | |
| 1093 | /*****************************************************************************/ |
| 1094 | /* Cx231xx redefine */ |
| 1095 | #define DPLL_CTRL5 0x874 |
| 1096 | #define DIG_PLL_CTL5 0x874 |
| 1097 | #define FLD_TRK_DS1_SEL 0x000C0000 |
| 1098 | #define FLD_TRK_DS2_SEL 0x00030000 |
| 1099 | #define FLD_TRK_KI 0x0000FF00 |
| 1100 | #define FLD_TRK_KD 0x000000FF |
| 1101 | |
| 1102 | /*****************************************************************************/ |
| 1103 | #define DEEMPH_GAIN_CTL 0x878 |
| 1104 | #define FLD_DEEMPH2_GAIN 0xFFFF0000 |
| 1105 | #define FLD_DEEMPH1_GAIN 0x0000FFFF |
| 1106 | |
| 1107 | /*****************************************************************************/ |
| 1108 | /* Cx231xx redefine */ |
| 1109 | #define DEEMPH_COEFF1 0x87C |
| 1110 | #define DEEMPH_COEF1 0x87C |
| 1111 | #define FLD_DEEMPH_B0 0xFFFF0000 |
| 1112 | #define FLD_DEEMPH_A0 0x0000FFFF |
| 1113 | |
| 1114 | /*****************************************************************************/ |
| 1115 | /* Cx231xx redefine */ |
| 1116 | #define DEEMPH_COEFF2 0x880 |
| 1117 | #define DEEMPH_COEF2 0x880 |
| 1118 | #define FLD_DEEMPH_B1 0xFFFF0000 |
| 1119 | #define FLD_DEEMPH_A1 0x0000FFFF |
| 1120 | |
| 1121 | /*****************************************************************************/ |
| 1122 | #define DBX1_CTL1 0x884 |
| 1123 | #define FLD_DBX1_WBE_GAIN 0xFFFF0000 |
| 1124 | #define FLD_DBX1_IN_GAIN 0x0000FFFF |
| 1125 | |
| 1126 | /*****************************************************************************/ |
| 1127 | #define DBX1_CTL2 0x888 |
| 1128 | #define FLD_DBX1_SE_BYPASS 0xFFFF0000 |
| 1129 | #define FLD_DBX1_SE_GAIN 0x0000FFFF |
| 1130 | |
| 1131 | /*****************************************************************************/ |
| 1132 | #define DBX1_RMS_SE 0x88C |
| 1133 | #define FLD_DBX1_RMS_WBE 0xFFFF0000 |
| 1134 | #define FLD_DBX1_RMS_SE_FLD 0x0000FFFF |
| 1135 | |
| 1136 | /*****************************************************************************/ |
| 1137 | #define DBX2_CTL1 0x890 |
| 1138 | #define FLD_DBX2_WBE_GAIN 0xFFFF0000 |
| 1139 | #define FLD_DBX2_IN_GAIN 0x0000FFFF |
| 1140 | |
| 1141 | /*****************************************************************************/ |
| 1142 | #define DBX2_CTL2 0x894 |
| 1143 | #define FLD_DBX2_SE_BYPASS 0xFFFF0000 |
| 1144 | #define FLD_DBX2_SE_GAIN 0x0000FFFF |
| 1145 | |
| 1146 | /*****************************************************************************/ |
| 1147 | #define DBX2_RMS_SE 0x898 |
| 1148 | #define FLD_DBX2_RMS_WBE 0xFFFF0000 |
| 1149 | #define FLD_DBX2_RMS_SE_FLD 0x0000FFFF |
| 1150 | |
| 1151 | /*****************************************************************************/ |
| 1152 | #define AM_FM_DIFF 0x89C |
| 1153 | /* Reserved [31] */ |
| 1154 | #define FLD_FM_DIFF_OUT 0x7FFF0000 |
| 1155 | /* Reserved [15] */ |
| 1156 | #define FLD_AM_DIFF_OUT 0x00007FFF |
| 1157 | |
| 1158 | /*****************************************************************************/ |
| 1159 | #define NICAM_FAW 0x8A0 |
| 1160 | #define FLD_FAWDETWINEND 0xFC000000 |
| 1161 | #define FLD_FAWDETWINSTR 0x03FF0000 |
| 1162 | /* Reserved [15:12] */ |
| 1163 | #define FLD_FAWDETTHRSHLD3 0x00000F00 |
| 1164 | #define FLD_FAWDETTHRSHLD2 0x000000F0 |
| 1165 | #define FLD_FAWDETTHRSHLD1 0x0000000F |
| 1166 | |
| 1167 | /*****************************************************************************/ |
| 1168 | /* Cx231xx redefine */ |
| 1169 | #define DEEMPH_GAIN 0x8A4 |
| 1170 | #define NICAM_DEEMPHGAIN 0x8A4 |
| 1171 | /* Reserved [31:18] */ |
| 1172 | #define FLD_DEEMPHGAIN 0x0003FFFF |
| 1173 | |
| 1174 | /*****************************************************************************/ |
| 1175 | /* Cx231xx redefine */ |
| 1176 | #define DEEMPH_NUMER1 0x8A8 |
| 1177 | #define NICAM_DEEMPHNUMER1 0x8A8 |
| 1178 | /* Reserved [31:18] */ |
| 1179 | #define FLD_DEEMPHNUMER1 0x0003FFFF |
| 1180 | |
| 1181 | /*****************************************************************************/ |
| 1182 | /* Cx231xx redefine */ |
| 1183 | #define DEEMPH_NUMER2 0x8AC |
| 1184 | #define NICAM_DEEMPHNUMER2 0x8AC |
| 1185 | /* Reserved [31:18] */ |
| 1186 | #define FLD_DEEMPHNUMER2 0x0003FFFF |
| 1187 | |
| 1188 | /*****************************************************************************/ |
| 1189 | /* Cx231xx redefine */ |
| 1190 | #define DEEMPH_DENOM1 0x8B0 |
| 1191 | #define NICAM_DEEMPHDENOM1 0x8B0 |
| 1192 | /* Reserved [31:18] */ |
| 1193 | #define FLD_DEEMPHDENOM1 0x0003FFFF |
| 1194 | |
| 1195 | /*****************************************************************************/ |
| 1196 | /* Cx231xx redefine */ |
| 1197 | #define DEEMPH_DENOM2 0x8B4 |
| 1198 | #define NICAM_DEEMPHDENOM2 0x8B4 |
| 1199 | /* Reserved [31:18] */ |
| 1200 | #define FLD_DEEMPHDENOM2 0x0003FFFF |
| 1201 | |
| 1202 | /*****************************************************************************/ |
| 1203 | #define NICAM_ERRLOG_CTL1 0x8B8 |
| 1204 | /* Reserved [31:28] */ |
| 1205 | #define FLD_ERRINTRPTTHSHLD1 0x0FFF0000 |
| 1206 | /* Reserved [15:12] */ |
| 1207 | #define FLD_ERRLOGPERIOD 0x00000FFF |
| 1208 | |
| 1209 | /*****************************************************************************/ |
| 1210 | #define NICAM_ERRLOG_CTL2 0x8BC |
| 1211 | /* Reserved [31:28] */ |
| 1212 | #define FLD_ERRINTRPTTHSHLD3 0x0FFF0000 |
| 1213 | /* Reserved [15:12] */ |
| 1214 | #define FLD_ERRINTRPTTHSHLD2 0x00000FFF |
| 1215 | |
| 1216 | /*****************************************************************************/ |
| 1217 | #define NICAM_ERRLOG_STS1 0x8C0 |
| 1218 | /* Reserved [31:28] */ |
| 1219 | #define FLD_ERRLOG2 0x0FFF0000 |
| 1220 | /* Reserved [15:12] */ |
| 1221 | #define FLD_ERRLOG1 0x00000FFF |
| 1222 | |
| 1223 | /*****************************************************************************/ |
| 1224 | #define NICAM_ERRLOG_STS2 0x8C4 |
| 1225 | /* Reserved [31:12] */ |
| 1226 | #define FLD_ERRLOG3 0x00000FFF |
| 1227 | |
| 1228 | /*****************************************************************************/ |
| 1229 | #define NICAM_STATUS 0x8C8 |
| 1230 | /* Reserved [31:20] */ |
| 1231 | #define FLD_NICAM_CIB 0x000C0000 |
| 1232 | #define FLD_NICAM_LOCK_STAT 0x00020000 |
| 1233 | #define FLD_NICAM_MUTE 0x00010000 |
| 1234 | #define FLD_NICAMADDIT_DATA 0x0000FFE0 |
| 1235 | #define FLD_NICAMCNTRL 0x0000001F |
| 1236 | |
| 1237 | /*****************************************************************************/ |
| 1238 | #define DEMATRIX_CTL 0x8CC |
| 1239 | #define FLD_AC97_IN_SHIFT 0xF0000000 |
| 1240 | #define FLD_I2S_IN_SHIFT 0x0F000000 |
| 1241 | #define FLD_DEMATRIX_SEL_CTL 0x00FF0000 |
| 1242 | /* Reserved [15:11] */ |
| 1243 | #define FLD_DMTRX_BYPASS 0x00000400 |
| 1244 | #define FLD_DEMATRIX_MODE 0x00000300 |
| 1245 | /* Reserved [7:6] */ |
| 1246 | #define FLD_PH_DBX_SEL 0x00000020 |
| 1247 | #define FLD_PH_CH_SEL 0x00000010 |
| 1248 | #define FLD_PHASE_FIX 0x0000000F |
| 1249 | |
| 1250 | /*****************************************************************************/ |
| 1251 | #define PATH1_CTL1 0x8D0 |
| 1252 | /* Reserved [31:29] */ |
| 1253 | #define FLD_PATH1_MUTE_CTL 0x1F000000 |
| 1254 | /* Reserved [23:22] */ |
| 1255 | #define FLD_PATH1_AVC_CG 0x00300000 |
| 1256 | #define FLD_PATH1_AVC_RT 0x000F0000 |
| 1257 | #define FLD_PATH1_AVC_AT 0x0000F000 |
| 1258 | #define FLD_PATH1_AVC_STEREO 0x00000800 |
| 1259 | #define FLD_PATH1_AVC_CR 0x00000700 |
| 1260 | #define FLD_PATH1_AVC_RMS_CON 0x000000F0 |
| 1261 | #define FLD_PATH1_SEL_CTL 0x0000000F |
| 1262 | |
| 1263 | /*****************************************************************************/ |
| 1264 | #define PATH1_VOL_CTL 0x8D4 |
| 1265 | #define FLD_PATH1_AVC_THRESHOLD 0x7FFF0000 |
| 1266 | #define FLD_PATH1_BAL_LEFT 0x00008000 |
| 1267 | #define FLD_PATH1_BAL_LEVEL 0x00007F00 |
| 1268 | #define FLD_PATH1_VOLUME 0x000000FF |
| 1269 | |
| 1270 | /*****************************************************************************/ |
| 1271 | #define PATH1_EQ_CTL 0x8D8 |
| 1272 | /* Reserved [31:30] */ |
| 1273 | #define FLD_PATH1_EQ_TREBLE_VOL 0x3F000000 |
| 1274 | /* Reserved [23:22] */ |
| 1275 | #define FLD_PATH1_EQ_MID_VOL 0x003F0000 |
| 1276 | /* Reserved [15:14] */ |
| 1277 | #define FLD_PATH1_EQ_BASS_VOL 0x00003F00 |
| 1278 | /* Reserved [7:1] */ |
| 1279 | #define FLD_PATH1_EQ_BAND_SEL 0x00000001 |
| 1280 | |
| 1281 | /*****************************************************************************/ |
| 1282 | #define PATH1_SC_CTL 0x8DC |
| 1283 | #define FLD_PATH1_SC_THRESHOLD 0x7FFF0000 |
| 1284 | #define FLD_PATH1_SC_RT 0x0000F000 |
| 1285 | #define FLD_PATH1_SC_AT 0x00000F00 |
| 1286 | #define FLD_PATH1_SC_STEREO 0x00000080 |
| 1287 | #define FLD_PATH1_SC_CR 0x00000070 |
| 1288 | #define FLD_PATH1_SC_RMS_CON 0x0000000F |
| 1289 | |
| 1290 | /*****************************************************************************/ |
| 1291 | #define PATH2_CTL1 0x8E0 |
| 1292 | /* Reserved [31:26] */ |
| 1293 | #define FLD_PATH2_MUTE_CTL 0x03000000 |
| 1294 | /* Reserved [23:22] */ |
| 1295 | #define FLD_PATH2_AVC_CG 0x00300000 |
| 1296 | #define FLD_PATH2_AVC_RT 0x000F0000 |
| 1297 | #define FLD_PATH2_AVC_AT 0x0000F000 |
| 1298 | #define FLD_PATH2_AVC_STEREO 0x00000800 |
| 1299 | #define FLD_PATH2_AVC_CR 0x00000700 |
| 1300 | #define FLD_PATH2_AVC_RMS_CON 0x000000F0 |
| 1301 | #define FLD_PATH2_SEL_CTL 0x0000000F |
| 1302 | |
| 1303 | /*****************************************************************************/ |
| 1304 | #define PATH2_VOL_CTL 0x8E4 |
| 1305 | #define FLD_PATH2_AVC_THRESHOLD 0xFFFF0000 |
| 1306 | #define FLD_PATH2_BAL_LEFT 0x00008000 |
| 1307 | #define FLD_PATH2_BAL_LEVEL 0x00007F00 |
| 1308 | #define FLD_PATH2_VOLUME 0x000000FF |
| 1309 | |
| 1310 | /*****************************************************************************/ |
| 1311 | #define PATH2_EQ_CTL 0x8E8 |
| 1312 | /* Reserved [31:30] */ |
| 1313 | #define FLD_PATH2_EQ_TREBLE_VOL 0x3F000000 |
| 1314 | /* Reserved [23:22] */ |
| 1315 | #define FLD_PATH2_EQ_MID_VOL 0x003F0000 |
| 1316 | /* Reserved [15:14] */ |
| 1317 | #define FLD_PATH2_EQ_BASS_VOL 0x00003F00 |
| 1318 | /* Reserved [7:1] */ |
| 1319 | #define FLD_PATH2_EQ_BAND_SEL 0x00000001 |
| 1320 | |
| 1321 | /*****************************************************************************/ |
| 1322 | #define PATH2_SC_CTL 0x8EC |
| 1323 | #define FLD_PATH2_SC_THRESHOLD 0xFFFF0000 |
| 1324 | #define FLD_PATH2_SC_RT 0x0000F000 |
| 1325 | #define FLD_PATH2_SC_AT 0x00000F00 |
| 1326 | #define FLD_PATH2_SC_STEREO 0x00000080 |
| 1327 | #define FLD_PATH2_SC_CR 0x00000070 |
| 1328 | #define FLD_PATH2_SC_RMS_CON 0x0000000F |
| 1329 | |
| 1330 | /*****************************************************************************/ |
| 1331 | #define SRC_CTL 0x8F0 |
| 1332 | #define FLD_SRC_STATUS 0xFFFFFF00 |
| 1333 | #define FLD_FIFO_LF_EN 0x000000FC |
| 1334 | #define FLD_BYPASS_LI 0x00000002 |
| 1335 | #define FLD_BYPASS_PF 0x00000001 |
| 1336 | |
| 1337 | /*****************************************************************************/ |
| 1338 | #define SRC_LF_COEF 0x8F4 |
| 1339 | #define FLD_LOOP_FILTER_COEF2 0xFFFF0000 |
| 1340 | #define FLD_LOOP_FILTER_COEF1 0x0000FFFF |
| 1341 | |
| 1342 | /*****************************************************************************/ |
| 1343 | #define SRC1_CTL 0x8F8 |
| 1344 | /* Reserved [31:28] */ |
| 1345 | #define FLD_SRC1_FIFO_RD_TH 0x0F000000 |
| 1346 | /* Reserved [23:18] */ |
| 1347 | #define FLD_SRC1_PHASE_INC 0x0003FFFF |
| 1348 | |
| 1349 | /*****************************************************************************/ |
| 1350 | #define SRC2_CTL 0x8FC |
| 1351 | /* Reserved [31:28] */ |
| 1352 | #define FLD_SRC2_FIFO_RD_TH 0x0F000000 |
| 1353 | /* Reserved [23:18] */ |
| 1354 | #define FLD_SRC2_PHASE_INC 0x0003FFFF |
| 1355 | |
| 1356 | /*****************************************************************************/ |
| 1357 | #define SRC3_CTL 0x900 |
| 1358 | /* Reserved [31:28] */ |
| 1359 | #define FLD_SRC3_FIFO_RD_TH 0x0F000000 |
| 1360 | /* Reserved [23:18] */ |
| 1361 | #define FLD_SRC3_PHASE_INC 0x0003FFFF |
| 1362 | |
| 1363 | /*****************************************************************************/ |
| 1364 | #define SRC4_CTL 0x904 |
| 1365 | /* Reserved [31:28] */ |
| 1366 | #define FLD_SRC4_FIFO_RD_TH 0x0F000000 |
| 1367 | /* Reserved [23:18] */ |
| 1368 | #define FLD_SRC4_PHASE_INC 0x0003FFFF |
| 1369 | |
| 1370 | /*****************************************************************************/ |
| 1371 | #define SRC5_CTL 0x908 |
| 1372 | /* Reserved [31:28] */ |
| 1373 | #define FLD_SRC5_FIFO_RD_TH 0x0F000000 |
| 1374 | /* Reserved [23:18] */ |
| 1375 | #define FLD_SRC5_PHASE_INC 0x0003FFFF |
| 1376 | |
| 1377 | /*****************************************************************************/ |
| 1378 | #define SRC6_CTL 0x90C |
| 1379 | /* Reserved [31:28] */ |
| 1380 | #define FLD_SRC6_FIFO_RD_TH 0x0F000000 |
| 1381 | /* Reserved [23:18] */ |
| 1382 | #define FLD_SRC6_PHASE_INC 0x0003FFFF |
| 1383 | |
| 1384 | /*****************************************************************************/ |
| 1385 | #define BAND_OUT_SEL 0x910 |
| 1386 | #define FLD_SRC6_IN_SEL 0xC0000000 |
| 1387 | #define FLD_SRC6_CLK_SEL 0x30000000 |
| 1388 | #define FLD_SRC5_IN_SEL 0x0C000000 |
| 1389 | #define FLD_SRC5_CLK_SEL 0x03000000 |
| 1390 | #define FLD_SRC4_IN_SEL 0x00C00000 |
| 1391 | #define FLD_SRC4_CLK_SEL 0x00300000 |
| 1392 | #define FLD_SRC3_IN_SEL 0x000C0000 |
| 1393 | #define FLD_SRC3_CLK_SEL 0x00030000 |
| 1394 | #define FLD_BASEBAND_BYPASS_CTL 0x0000FF00 |
| 1395 | #define FLD_AC97_SRC_SEL 0x000000C0 |
| 1396 | #define FLD_I2S_SRC_SEL 0x00000030 |
| 1397 | #define FLD_PARALLEL2_SRC_SEL 0x0000000C |
| 1398 | #define FLD_PARALLEL1_SRC_SEL 0x00000003 |
| 1399 | |
| 1400 | /*****************************************************************************/ |
| 1401 | #define I2S_IN_CTL 0x914 |
| 1402 | /* Reserved [31:11] */ |
| 1403 | #define FLD_I2S_UP2X_BW20K 0x00000400 |
| 1404 | #define FLD_I2S_UP2X_BYPASS 0x00000200 |
| 1405 | #define FLD_I2S_IN_MASTER_MODE 0x00000100 |
| 1406 | #define FLD_I2S_IN_SONY_MODE 0x00000080 |
| 1407 | #define FLD_I2S_IN_RIGHT_JUST 0x00000040 |
| 1408 | #define FLD_I2S_IN_WS_SEL 0x00000020 |
| 1409 | #define FLD_I2S_IN_BCN_DEL 0x0000001F |
| 1410 | |
| 1411 | /*****************************************************************************/ |
| 1412 | #define I2S_OUT_CTL 0x918 |
| 1413 | /* Reserved [31:17] */ |
| 1414 | #define FLD_I2S_OUT_SOFT_RESET_EN 0x00010000 |
| 1415 | /* Reserved [15:9] */ |
| 1416 | #define FLD_I2S_OUT_MASTER_MODE 0x00000100 |
| 1417 | #define FLD_I2S_OUT_SONY_MODE 0x00000080 |
| 1418 | #define FLD_I2S_OUT_RIGHT_JUST 0x00000040 |
| 1419 | #define FLD_I2S_OUT_WS_SEL 0x00000020 |
| 1420 | #define FLD_I2S_OUT_BCN_DEL 0x0000001F |
| 1421 | |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1422 | /*****************************************************************************/ |
| 1423 | #define AC97_CTL 0x91C |
| 1424 | /* Reserved [31:26] */ |
| 1425 | #define FLD_AC97_UP2X_BW20K 0x02000000 |
| 1426 | #define FLD_AC97_UP2X_BYPASS 0x01000000 |
| 1427 | /* Reserved [23:17] */ |
| 1428 | #define FLD_AC97_RST_ACL 0x00010000 |
| 1429 | /* Reserved [15:9] */ |
| 1430 | #define FLD_AC97_WAKE_UP_SYNC 0x00000100 |
| 1431 | /* Reserved [7:1] */ |
| 1432 | #define FLD_AC97_SHUTDOWN 0x00000001 |
| 1433 | |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1434 | /* Cx231xx redefine */ |
| 1435 | #define QPSK_IAGC_CTL1 0x94c |
| 1436 | #define QPSK_IAGC_CTL2 0x950 |
| 1437 | #define QPSK_FEPR_FREQ 0x954 |
| 1438 | #define QPSK_BTL_CTL1 0x958 |
| 1439 | #define QPSK_BTL_CTL2 0x95c |
| 1440 | #define QPSK_CTL_CTL1 0x960 |
| 1441 | #define QPSK_CTL_CTL2 0x964 |
| 1442 | #define QPSK_MF_FAGC_CTL 0x968 |
| 1443 | #define QPSK_EQ_CTL 0x96c |
| 1444 | #define QPSK_LOCK_CTL 0x970 |
| 1445 | |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1446 | /*****************************************************************************/ |
| 1447 | #define FM1_DFT_CTL 0x9A8 |
| 1448 | #define FLD_FM1_DFT_THRESHOLD 0xFFFF0000 |
| 1449 | /* Reserved [15:8] */ |
| 1450 | #define FLD_FM1_DFT_CMP_CTL 0x00000080 |
| 1451 | #define FLD_FM1_DFT_AVG 0x00000070 |
| 1452 | /* Reserved [3:1] */ |
| 1453 | #define FLD_FM1_DFT_START 0x00000001 |
| 1454 | |
| 1455 | /*****************************************************************************/ |
| 1456 | #define FM1_DFT_STATUS 0x9AC |
| 1457 | #define FLD_FM1_DFT_DONE 0x80000000 |
| 1458 | /* Reserved [30:19] */ |
| 1459 | #define FLD_FM_DFT_TH_CMP 0x00040000 |
| 1460 | #define FLD_FM1_DFT 0x0003FFFF |
| 1461 | |
| 1462 | /*****************************************************************************/ |
| 1463 | #define FM2_DFT_CTL 0x9B0 |
| 1464 | #define FLD_FM2_DFT_THRESHOLD 0xFFFF0000 |
| 1465 | /* Reserved [15:8] */ |
| 1466 | #define FLD_FM2_DFT_CMP_CTL 0x00000080 |
| 1467 | #define FLD_FM2_DFT_AVG 0x00000070 |
| 1468 | /* Reserved [3:1] */ |
| 1469 | #define FLD_FM2_DFT_START 0x00000001 |
| 1470 | |
| 1471 | /*****************************************************************************/ |
| 1472 | #define FM2_DFT_STATUS 0x9B4 |
| 1473 | #define FLD_FM2_DFT_DONE 0x80000000 |
| 1474 | /* Reserved [30:19] */ |
| 1475 | #define FLD_FM2_DFT_TH_CMP_STAT 0x00040000 |
| 1476 | #define FLD_FM2_DFT 0x0003FFFF |
| 1477 | |
| 1478 | /*****************************************************************************/ |
| 1479 | /* Cx231xx redefine */ |
| 1480 | #define AAGC_STATUS_REG 0x9B8 |
| 1481 | #define AAGC_STATUS 0x9B8 |
| 1482 | /* Reserved [31:27] */ |
| 1483 | #define FLD_FM2_DAGC_OUT 0x07000000 |
| 1484 | /* Reserved [23:19] */ |
| 1485 | #define FLD_FM1_DAGC_OUT 0x00070000 |
| 1486 | /* Reserved [15:6] */ |
| 1487 | #define FLD_AFE_VGA_OUT 0x0000003F |
| 1488 | |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1489 | /*****************************************************************************/ |
| 1490 | #define MTS_GAIN_STATUS 0x9BC |
| 1491 | /* Reserved [31:14] */ |
| 1492 | #define FLD_MTS_GAIN 0x00003FFF |
| 1493 | |
| 1494 | #define RDS_OUT 0x9C0 |
| 1495 | #define FLD_RDS_Q 0xFFFF0000 |
| 1496 | #define FLD_RDS_I 0x0000FFFF |
| 1497 | |
| 1498 | /*****************************************************************************/ |
| 1499 | #define AUTOCONFIG_REG 0x9C4 |
| 1500 | /* Reserved [31:4] */ |
| 1501 | #define FLD_AUTOCONFIG_MODE 0x0000000F |
| 1502 | |
| 1503 | #define FM_AFC 0x9C8 |
| 1504 | #define FLD_FM2_AFC 0xFFFF0000 |
| 1505 | #define FLD_FM1_AFC 0x0000FFFF |
| 1506 | |
| 1507 | /*****************************************************************************/ |
| 1508 | /* Cx231xx redefine */ |
| 1509 | #define NEW_SPARE 0x9CC |
| 1510 | #define NEW_SPARE_REG 0x9CC |
| 1511 | |
| 1512 | /*****************************************************************************/ |
| 1513 | #define DBX_ADJ 0x9D0 |
| 1514 | /* Reserved [31:28] */ |
| 1515 | #define FLD_DBX2_ADJ 0x0FFF0000 |
| 1516 | /* Reserved [15:12] */ |
| 1517 | #define FLD_DBX1_ADJ 0x00000FFF |
| 1518 | |
| 1519 | #define VID_FMT_AUTO 0 |
| 1520 | #define VID_FMT_NTSC_M 1 |
| 1521 | #define VID_FMT_NTSC_J 2 |
| 1522 | #define VID_FMT_NTSC_443 3 |
| 1523 | #define VID_FMT_PAL_BDGHI 4 |
| 1524 | #define VID_FMT_PAL_M 5 |
| 1525 | #define VID_FMT_PAL_N 6 |
| 1526 | #define VID_FMT_PAL_NC 7 |
| 1527 | #define VID_FMT_PAL_60 8 |
| 1528 | #define VID_FMT_SECAM 12 |
| 1529 | #define VID_FMT_SECAM_60 13 |
| 1530 | |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 1531 | #define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */ |
| 1532 | #define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */ |
| 1533 | #define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */ |
| 1534 | #define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */ |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1535 | |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 1536 | #define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz lowpass filter bandwidth */ |
| 1537 | #define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz lowpass filter bandwidth */ |
| 1538 | #define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz lowpass filter bandwidth */ |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1539 | |
| Mauro Carvalho Chehab | 84b5dbf | 2009-03-03 06:14:34 -0300 | [diff] [blame^] | 1540 | #define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz lowpass filter bandwidth */ |
| 1541 | #define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz lowpass filter bandwidth */ |
| 1542 | #define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz lowpass filter bandwidth */ |
| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame] | 1543 | |
| 1544 | #define TWO_TAP_FILT 0 |
| 1545 | #define THREE_TAP_FILT 1 |
| 1546 | #define FOUR_TAP_FILT 2 |
| 1547 | #define FIVE_TAP_FILT 3 |
| 1548 | |
| 1549 | #define AUD_CHAN_SRC_PARALLEL 0 |
| 1550 | #define AUD_CHAN_SRC_I2S_INPUT 1 |
| 1551 | #define AUD_CHAN_SRC_FLATIRON 2 |
| 1552 | #define AUD_CHAN_SRC_PARALLEL3 3 |
| 1553 | |
| 1554 | #define OUT_MODE_601 0 |
| 1555 | #define OUT_MODE_656 1 |
| 1556 | #define OUT_MODE_VIP11 2 |
| 1557 | #define OUT_MODE_VIP20 3 |
| 1558 | |
| 1559 | #define PHASE_INC_49MHZ 0x0DF22 |
| 1560 | #define PHASE_INC_56MHZ 0x0FA5B |
| 1561 | #define PHASE_INC_28MHZ 0x010000 |
| 1562 | |
| 1563 | #endif |