blob: 6bd51ce3ce32a631f19306ebde347f24441b9397 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
Yinghai Lud4057bd2008-08-19 20:50:38 -070028#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
Alexey Dobriyan129f6942005-06-23 00:08:33 -070032#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include <linux/sysdev.h>
Eric W. Biederman3b7d1922006-10-04 02:16:59 -070034#include <linux/msi.h>
Eric W. Biederman95d77882006-10-04 02:17:01 -070035#include <linux/htirq.h>
Nigel Cunningham7dfb7102006-12-06 20:34:23 -080036#include <linux/freezer.h>
Eric W. Biedermanf26d6a22007-05-02 19:27:19 +020037#include <linux/kthread.h>
Ingo Molnar54168ed2008-08-20 09:07:45 +020038#include <linux/jiffies.h> /* time_after() */
Yinghai Lud4057bd2008-08-19 20:50:38 -070039#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -070044#include <linux/hpet.h>
Ashok Raj54d5d422005-09-06 15:16:15 -070045
Yinghai Lud4057bd2008-08-19 20:50:38 -070046#include <asm/idle.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <asm/io.h>
48#include <asm/smp.h>
49#include <asm/desc.h>
Yinghai Lud4057bd2008-08-19 20:50:38 -070050#include <asm/proto.h>
51#include <asm/acpi.h>
52#include <asm/dma.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#include <asm/timer.h>
Ingo Molnar306e4402005-06-30 02:58:55 -070054#include <asm/i8259.h>
Don Zickus3e4ff112006-06-26 13:57:01 +020055#include <asm/nmi.h>
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -070056#include <asm/msidef.h>
Eric W. Biederman8b955b02006-10-04 02:16:55 -070057#include <asm/hypertransport.h>
Yinghai Lua4dbc342008-07-25 02:14:28 -070058#include <asm/setup.h>
Yinghai Lud4057bd2008-08-19 20:50:38 -070059#include <asm/irq_remapping.h>
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -070060#include <asm/hpet.h>
Dean Nelson4173a0e2008-10-02 12:18:21 -050061#include <asm/uv/uv_hub.h>
62#include <asm/uv/uv_irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
Yinghai Lu497c9a12008-08-19 20:50:28 -070064#include <mach_ipi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070065#include <mach_apic.h>
Andi Kleen874c4fe2006-09-26 10:52:26 +020066#include <mach_apicdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +010068#define __apicdebuginit(type) static type __init
69
Linus Torvalds1da177e2005-04-16 15:20:36 -070070/*
Ingo Molnar54168ed2008-08-20 09:07:45 +020071 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 */
74int sis_apic_bug = -1;
75
Yinghai Luefa25592008-08-19 20:50:36 -070076static DEFINE_SPINLOCK(ioapic_lock);
77static DEFINE_SPINLOCK(vector_lock);
78
Yinghai Luefa25592008-08-19 20:50:36 -070079/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070080 * # of IRQ routing registers
81 */
82int nr_ioapic_registers[MAX_IO_APICS];
83
Alexey Starikovskiy9f640cc2008-04-04 23:41:13 +040084/* I/O APIC entries */
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +040085struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
Alexey Starikovskiy9f640cc2008-04-04 23:41:13 +040086int nr_ioapics;
87
Alexey Starikovskiy584f7342008-04-04 23:41:32 +040088/* MP IRQ source entries */
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +040089struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
Alexey Starikovskiy584f7342008-04-04 23:41:32 +040090
91/* # of MP IRQ source entries */
92int mp_irq_entries;
93
Alexey Starikovskiy8732fc42008-05-19 19:47:16 +040094#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95int mp_bus_id_to_type[MAX_MP_BUSSES];
96#endif
97
98DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99
Yinghai Luefa25592008-08-19 20:50:36 -0700100int skip_ioapic_setup;
101
Ingo Molnar54168ed2008-08-20 09:07:45 +0200102static int __init parse_noapic(char *str)
Yinghai Luefa25592008-08-19 20:50:36 -0700103{
104 /* disable IO-APIC */
105 disable_ioapic_setup();
106 return 0;
107}
108early_param("noapic", parse_noapic);
Chuck Ebbert66759a02005-09-12 18:49:25 +0200109
Yinghai Lu0f978f42008-08-19 20:50:26 -0700110struct irq_pin_list;
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +0200111
112/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113 * This is performance-critical, we want to do it O(1)
114 *
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
117 */
118
Yinghai Lu0f978f42008-08-19 20:50:26 -0700119struct irq_pin_list {
120 int apic, pin;
121 struct irq_pin_list *next;
122};
Yinghai Lu301e6192008-08-19 20:50:02 -0700123
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800124static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
Yinghai Lu0f978f42008-08-19 20:50:26 -0700125{
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800126 struct irq_pin_list *pin;
127 int node;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700128
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800129 node = cpu_to_node(cpu);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700130
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800131 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
132 printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700133
Yinghai Lu0f978f42008-08-19 20:50:26 -0700134 return pin;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700135}
136
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800137struct irq_cfg {
138 struct irq_pin_list *irq_2_pin;
Mike Travis22f65d32008-12-16 17:33:56 -0800139 cpumask_var_t domain;
140 cpumask_var_t old_domain;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800141 unsigned move_cleanup_count;
142 u8 vector;
143 u8 move_in_progress : 1;
Yinghai Lu48a1b102008-12-11 00:15:01 -0800144#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
145 u8 move_desc_pending : 1;
146#endif
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800147};
148
149/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150#ifdef CONFIG_SPARSE_IRQ
151static struct irq_cfg irq_cfgx[] = {
152#else
153static struct irq_cfg irq_cfgx[NR_IRQS] = {
154#endif
Mike Travis22f65d32008-12-16 17:33:56 -0800155 [0] = { .vector = IRQ0_VECTOR, },
156 [1] = { .vector = IRQ1_VECTOR, },
157 [2] = { .vector = IRQ2_VECTOR, },
158 [3] = { .vector = IRQ3_VECTOR, },
159 [4] = { .vector = IRQ4_VECTOR, },
160 [5] = { .vector = IRQ5_VECTOR, },
161 [6] = { .vector = IRQ6_VECTOR, },
162 [7] = { .vector = IRQ7_VECTOR, },
163 [8] = { .vector = IRQ8_VECTOR, },
164 [9] = { .vector = IRQ9_VECTOR, },
165 [10] = { .vector = IRQ10_VECTOR, },
166 [11] = { .vector = IRQ11_VECTOR, },
167 [12] = { .vector = IRQ12_VECTOR, },
168 [13] = { .vector = IRQ13_VECTOR, },
169 [14] = { .vector = IRQ14_VECTOR, },
170 [15] = { .vector = IRQ15_VECTOR, },
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800171};
172
173void __init arch_early_irq_init(void)
Yinghai Lu0f978f42008-08-19 20:50:26 -0700174{
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800175 struct irq_cfg *cfg;
176 struct irq_desc *desc;
177 int count;
178 int i;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700179
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800180 cfg = irq_cfgx;
181 count = ARRAY_SIZE(irq_cfgx);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700182
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
Mike Travis22f65d32008-12-16 17:33:56 -0800186 alloc_bootmem_cpumask_var(&cfg[i].domain);
187 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
188 if (i < NR_IRQS_LEGACY)
189 cpumask_setall(cfg[i].domain);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800190 }
191}
192
193#ifdef CONFIG_SPARSE_IRQ
194static struct irq_cfg *irq_cfg(unsigned int irq)
195{
196 struct irq_cfg *cfg = NULL;
197 struct irq_desc *desc;
198
199 desc = irq_to_desc(irq);
200 if (desc)
201 cfg = desc->chip_data;
202
203 return cfg;
204}
205
206static struct irq_cfg *get_one_free_irq_cfg(int cpu)
207{
208 struct irq_cfg *cfg;
209 int node;
210
211 node = cpu_to_node(cpu);
212
213 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
Mike Travis22f65d32008-12-16 17:33:56 -0800214 if (cfg) {
215 /* FIXME: needs alloc_cpumask_var_node() */
216 if (!alloc_cpumask_var(&cfg->domain, GFP_ATOMIC)) {
217 kfree(cfg);
218 cfg = NULL;
219 } else if (!alloc_cpumask_var(&cfg->old_domain, GFP_ATOMIC)) {
220 free_cpumask_var(cfg->domain);
221 kfree(cfg);
222 cfg = NULL;
223 } else {
224 cpumask_clear(cfg->domain);
225 cpumask_clear(cfg->old_domain);
226 }
227 }
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800228 printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node);
229
230 return cfg;
231}
232
233void arch_init_chip_data(struct irq_desc *desc, int cpu)
234{
235 struct irq_cfg *cfg;
236
237 cfg = desc->chip_data;
238 if (!cfg) {
239 desc->chip_data = get_one_free_irq_cfg(cpu);
240 if (!desc->chip_data) {
241 printk(KERN_ERR "can not alloc irq_cfg\n");
242 BUG_ON(1);
243 }
244 }
245}
246
Yinghai Lu48a1b102008-12-11 00:15:01 -0800247#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
248
249static void
250init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
251{
252 struct irq_pin_list *old_entry, *head, *tail, *entry;
253
254 cfg->irq_2_pin = NULL;
255 old_entry = old_cfg->irq_2_pin;
256 if (!old_entry)
257 return;
258
259 entry = get_one_free_irq_2_pin(cpu);
260 if (!entry)
261 return;
262
263 entry->apic = old_entry->apic;
264 entry->pin = old_entry->pin;
265 head = entry;
266 tail = entry;
267 old_entry = old_entry->next;
268 while (old_entry) {
269 entry = get_one_free_irq_2_pin(cpu);
270 if (!entry) {
271 entry = head;
272 while (entry) {
273 head = entry->next;
274 kfree(entry);
275 entry = head;
276 }
277 /* still use the old one */
278 return;
279 }
280 entry->apic = old_entry->apic;
281 entry->pin = old_entry->pin;
282 tail->next = entry;
283 tail = entry;
284 old_entry = old_entry->next;
285 }
286
287 tail->next = NULL;
288 cfg->irq_2_pin = head;
289}
290
291static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
292{
293 struct irq_pin_list *entry, *next;
294
295 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
296 return;
297
298 entry = old_cfg->irq_2_pin;
299
300 while (entry) {
301 next = entry->next;
302 kfree(entry);
303 entry = next;
304 }
305 old_cfg->irq_2_pin = NULL;
306}
307
308void arch_init_copy_chip_data(struct irq_desc *old_desc,
309 struct irq_desc *desc, int cpu)
310{
311 struct irq_cfg *cfg;
312 struct irq_cfg *old_cfg;
313
314 cfg = get_one_free_irq_cfg(cpu);
315
316 if (!cfg)
317 return;
318
319 desc->chip_data = cfg;
320
321 old_cfg = old_desc->chip_data;
322
323 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
324
325 init_copy_irq_2_pin(old_cfg, cfg, cpu);
326}
327
328static void free_irq_cfg(struct irq_cfg *old_cfg)
329{
330 kfree(old_cfg);
331}
332
333void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
334{
335 struct irq_cfg *old_cfg, *cfg;
336
337 old_cfg = old_desc->chip_data;
338 cfg = desc->chip_data;
339
340 if (old_cfg == cfg)
341 return;
342
343 if (old_cfg) {
344 free_irq_2_pin(old_cfg, cfg);
345 free_irq_cfg(old_cfg);
346 old_desc->chip_data = NULL;
347 }
348}
349
350static void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask)
351{
352 struct irq_cfg *cfg = desc->chip_data;
353
354 if (!cfg->move_in_progress) {
355 /* it means that domain is not changed */
356 if (!cpus_intersects(desc->affinity, mask))
357 cfg->move_desc_pending = 1;
358 }
359}
360#endif
361
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800362#else
363static struct irq_cfg *irq_cfg(unsigned int irq)
364{
365 return irq < nr_irqs ? irq_cfgx + irq : NULL;
366}
367
368#endif
369
Yinghai Lu48a1b102008-12-11 00:15:01 -0800370#ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
Mike Travise7986732008-12-16 17:33:52 -0800371static inline void
372set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu3145e942008-12-05 18:58:34 -0800373{
Yinghai Lu0f978f42008-08-19 20:50:26 -0700374}
Yinghai Lu48a1b102008-12-11 00:15:01 -0800375#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376
Linus Torvalds130fe052006-11-01 09:11:00 -0800377struct io_apic {
378 unsigned int index;
379 unsigned int unused[3];
380 unsigned int data;
381};
382
383static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
384{
385 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +0400386 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
Linus Torvalds130fe052006-11-01 09:11:00 -0800387}
388
389static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
390{
391 struct io_apic __iomem *io_apic = io_apic_base(apic);
392 writel(reg, &io_apic->index);
393 return readl(&io_apic->data);
394}
395
396static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
397{
398 struct io_apic __iomem *io_apic = io_apic_base(apic);
399 writel(reg, &io_apic->index);
400 writel(value, &io_apic->data);
401}
402
403/*
404 * Re-write a value: to be used for read-modify-write
405 * cycles where the read already set up the index register.
406 *
407 * Older SiS APIC requires we rewrite the index register
408 */
409static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
410{
Ingo Molnar54168ed2008-08-20 09:07:45 +0200411 struct io_apic __iomem *io_apic = io_apic_base(apic);
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +0200412
413 if (sis_apic_bug)
414 writel(reg, &io_apic->index);
Linus Torvalds130fe052006-11-01 09:11:00 -0800415 writel(value, &io_apic->data);
416}
417
Yinghai Lu3145e942008-12-05 18:58:34 -0800418static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700419{
420 struct irq_pin_list *entry;
421 unsigned long flags;
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700422
423 spin_lock_irqsave(&ioapic_lock, flags);
424 entry = cfg->irq_2_pin;
425 for (;;) {
426 unsigned int reg;
427 int pin;
428
429 if (!entry)
430 break;
431 pin = entry->pin;
432 reg = io_apic_read(entry->apic, 0x10 + pin*2);
433 /* Is the remote IRR bit set? */
434 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
435 spin_unlock_irqrestore(&ioapic_lock, flags);
436 return true;
437 }
438 if (!entry->next)
439 break;
440 entry = entry->next;
441 }
442 spin_unlock_irqrestore(&ioapic_lock, flags);
443
444 return false;
445}
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700446
Andi Kleencf4c6a22006-09-26 10:52:30 +0200447union entry_union {
448 struct { u32 w1, w2; };
449 struct IO_APIC_route_entry entry;
450};
451
452static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
453{
454 union entry_union eu;
455 unsigned long flags;
456 spin_lock_irqsave(&ioapic_lock, flags);
457 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
458 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
459 spin_unlock_irqrestore(&ioapic_lock, flags);
460 return eu.entry;
461}
462
Linus Torvaldsf9dadfa2006-11-01 10:05:35 -0800463/*
464 * When we write a new IO APIC routing entry, we need to write the high
465 * word first! If the mask bit in the low word is clear, we will enable
466 * the interrupt, and we need to make sure the entry is fully populated
467 * before that happens.
468 */
Andi Kleend15512f2006-12-07 02:14:07 +0100469static void
470__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
471{
472 union entry_union eu;
473 eu.entry = e;
474 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
475 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
476}
477
Andi Kleencf4c6a22006-09-26 10:52:30 +0200478static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
479{
480 unsigned long flags;
Andi Kleencf4c6a22006-09-26 10:52:30 +0200481 spin_lock_irqsave(&ioapic_lock, flags);
Andi Kleend15512f2006-12-07 02:14:07 +0100482 __ioapic_write_entry(apic, pin, e);
Linus Torvaldsf9dadfa2006-11-01 10:05:35 -0800483 spin_unlock_irqrestore(&ioapic_lock, flags);
484}
485
486/*
487 * When we mask an IO APIC routing entry, we need to write the low
488 * word first, in order to set the mask bit before we change the
489 * high bits!
490 */
491static void ioapic_mask_entry(int apic, int pin)
492{
493 unsigned long flags;
494 union entry_union eu = { .entry.mask = 1 };
495
496 spin_lock_irqsave(&ioapic_lock, flags);
Andi Kleencf4c6a22006-09-26 10:52:30 +0200497 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
498 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
499 spin_unlock_irqrestore(&ioapic_lock, flags);
500}
501
Yinghai Lu497c9a12008-08-19 20:50:28 -0700502#ifdef CONFIG_SMP
Mike Travis22f65d32008-12-16 17:33:56 -0800503static void send_cleanup_vector(struct irq_cfg *cfg)
504{
505 cpumask_var_t cleanup_mask;
506
507 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
508 unsigned int i;
509 cfg->move_cleanup_count = 0;
510 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
511 cfg->move_cleanup_count++;
512 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
513 send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
514 } else {
515 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
516 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
517 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
518 free_cpumask_var(cleanup_mask);
519 }
520 cfg->move_in_progress = 0;
521}
522
Yinghai Lu3145e942008-12-05 18:58:34 -0800523static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
Yinghai Lu497c9a12008-08-19 20:50:28 -0700524{
525 int apic, pin;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700526 struct irq_pin_list *entry;
Yinghai Lu3145e942008-12-05 18:58:34 -0800527 u8 vector = cfg->vector;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700528
Yinghai Lu497c9a12008-08-19 20:50:28 -0700529 entry = cfg->irq_2_pin;
530 for (;;) {
531 unsigned int reg;
532
533 if (!entry)
534 break;
535
536 apic = entry->apic;
537 pin = entry->pin;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200538#ifdef CONFIG_INTR_REMAP
539 /*
540 * With interrupt-remapping, destination information comes
541 * from interrupt-remapping table entry.
542 */
543 if (!irq_remapped(irq))
544 io_apic_write(apic, 0x11 + pin*2, dest);
545#else
Yinghai Lu497c9a12008-08-19 20:50:28 -0700546 io_apic_write(apic, 0x11 + pin*2, dest);
Ingo Molnar54168ed2008-08-20 09:07:45 +0200547#endif
Yinghai Lu497c9a12008-08-19 20:50:28 -0700548 reg = io_apic_read(apic, 0x10 + pin*2);
549 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
550 reg |= vector;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200551 io_apic_modify(apic, 0x10 + pin*2, reg);
Yinghai Lu497c9a12008-08-19 20:50:28 -0700552 if (!entry->next)
553 break;
554 entry = entry->next;
555 }
556}
Yinghai Luefa25592008-08-19 20:50:36 -0700557
Mike Travise7986732008-12-16 17:33:52 -0800558static int
559assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
Yinghai Luefa25592008-08-19 20:50:36 -0700560
Mike Travis22f65d32008-12-16 17:33:56 -0800561/*
562 * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid
563 * of that, or returns BAD_APICID and leaves desc->affinity untouched.
564 */
565static unsigned int
566set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -0700567{
568 struct irq_cfg *cfg;
Yinghai Lu3145e942008-12-05 18:58:34 -0800569 unsigned int irq;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700570
Rusty Russell0de26522008-12-13 21:20:26 +1030571 if (!cpumask_intersects(mask, cpu_online_mask))
Mike Travis22f65d32008-12-16 17:33:56 -0800572 return BAD_APICID;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700573
Yinghai Lu3145e942008-12-05 18:58:34 -0800574 irq = desc->irq;
575 cfg = desc->chip_data;
Mike Travise7986732008-12-16 17:33:52 -0800576 if (assign_irq_vector(irq, cfg, mask))
Mike Travis22f65d32008-12-16 17:33:56 -0800577 return BAD_APICID;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700578
Mike Travis22f65d32008-12-16 17:33:56 -0800579 cpumask_and(&desc->affinity, cfg->domain, mask);
Mike Travise7986732008-12-16 17:33:52 -0800580 set_extra_move_desc(desc, mask);
Mike Travis22f65d32008-12-16 17:33:56 -0800581 return cpu_mask_to_apicid_and(&desc->affinity, cpu_online_mask);
582}
Yinghai Lu3145e942008-12-05 18:58:34 -0800583
Mike Travis22f65d32008-12-16 17:33:56 -0800584static void
585set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
586{
587 struct irq_cfg *cfg;
588 unsigned long flags;
589 unsigned int dest;
590 unsigned int irq;
591
592 irq = desc->irq;
593 cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700594
595 spin_lock_irqsave(&ioapic_lock, flags);
Mike Travis22f65d32008-12-16 17:33:56 -0800596 dest = set_desc_affinity(desc, mask);
597 if (dest != BAD_APICID) {
598 /* Only the high 8 bits are valid. */
599 dest = SET_APIC_LOGICAL_ID(dest);
600 __target_IO_APIC_irq(irq, dest, cfg);
601 }
Yinghai Lu497c9a12008-08-19 20:50:28 -0700602 spin_unlock_irqrestore(&ioapic_lock, flags);
603}
Yinghai Lu3145e942008-12-05 18:58:34 -0800604
Mike Travis22f65d32008-12-16 17:33:56 -0800605static void
606set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
Yinghai Lu3145e942008-12-05 18:58:34 -0800607{
608 struct irq_desc *desc;
609
610 desc = irq_to_desc(irq);
611
612 set_ioapic_affinity_irq_desc(desc, mask);
613}
Yinghai Lu497c9a12008-08-19 20:50:28 -0700614#endif /* CONFIG_SMP */
615
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616/*
617 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
618 * shared ISA-space IRQs, so we have to support them. We are super
619 * fast in the common case, and fast for shared ISA-space IRQs.
620 */
Yinghai Lu3145e942008-12-05 18:58:34 -0800621static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622{
Yinghai Lu0f978f42008-08-19 20:50:26 -0700623 struct irq_pin_list *entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624
Yinghai Lu0f978f42008-08-19 20:50:26 -0700625 entry = cfg->irq_2_pin;
626 if (!entry) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800627 entry = get_one_free_irq_2_pin(cpu);
628 if (!entry) {
629 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
630 apic, pin);
631 return;
632 }
Yinghai Lu0f978f42008-08-19 20:50:26 -0700633 cfg->irq_2_pin = entry;
634 entry->apic = apic;
635 entry->pin = pin;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700636 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 }
Yinghai Lu0f978f42008-08-19 20:50:26 -0700638
639 while (entry->next) {
640 /* not again, please */
641 if (entry->apic == apic && entry->pin == pin)
642 return;
643
644 entry = entry->next;
645 }
646
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800647 entry->next = get_one_free_irq_2_pin(cpu);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700648 entry = entry->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 entry->apic = apic;
650 entry->pin = pin;
651}
652
653/*
654 * Reroute an IRQ to a different pin.
655 */
Yinghai Lu3145e942008-12-05 18:58:34 -0800656static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 int oldapic, int oldpin,
658 int newapic, int newpin)
659{
Yinghai Lu0f978f42008-08-19 20:50:26 -0700660 struct irq_pin_list *entry = cfg->irq_2_pin;
661 int replaced = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662
Yinghai Lu0f978f42008-08-19 20:50:26 -0700663 while (entry) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664 if (entry->apic == oldapic && entry->pin == oldpin) {
665 entry->apic = newapic;
666 entry->pin = newpin;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700667 replaced = 1;
668 /* every one is different, right? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 break;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700670 }
671 entry = entry->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672 }
Yinghai Lu0f978f42008-08-19 20:50:26 -0700673
674 /* why? call replace before add? */
675 if (!replaced)
Yinghai Lu3145e942008-12-05 18:58:34 -0800676 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677}
678
Yinghai Lu3145e942008-12-05 18:58:34 -0800679static inline void io_apic_modify_irq(struct irq_cfg *cfg,
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400680 int mask_and, int mask_or,
681 void (*final)(struct irq_pin_list *entry))
682{
683 int pin;
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400684 struct irq_pin_list *entry;
685
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400686 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
687 unsigned int reg;
688 pin = entry->pin;
689 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
690 reg &= mask_and;
691 reg |= mask_or;
692 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
693 if (final)
694 final(entry);
695 }
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700696}
697
Yinghai Lu3145e942008-12-05 18:58:34 -0800698static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400699{
Yinghai Lu3145e942008-12-05 18:58:34 -0800700 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400701}
Yinghai Lu4e738e22008-08-19 20:50:47 -0700702
703#ifdef CONFIG_X86_64
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400704void io_apic_sync(struct irq_pin_list *entry)
Yinghai Lu4e738e22008-08-19 20:50:47 -0700705{
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400706 /*
707 * Synchronize the IO-APIC and the CPU by doing
708 * a dummy read from the IO-APIC
709 */
710 struct io_apic __iomem *io_apic;
711 io_apic = io_apic_base(entry->apic);
Yinghai Lu4e738e22008-08-19 20:50:47 -0700712 readl(&io_apic->data);
713}
714
Yinghai Lu3145e942008-12-05 18:58:34 -0800715static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400716{
Yinghai Lu3145e942008-12-05 18:58:34 -0800717 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400718}
719#else /* CONFIG_X86_32 */
Yinghai Lu3145e942008-12-05 18:58:34 -0800720static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400721{
Yinghai Lu3145e942008-12-05 18:58:34 -0800722 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400723}
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700724
Yinghai Lu3145e942008-12-05 18:58:34 -0800725static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400726{
Yinghai Lu3145e942008-12-05 18:58:34 -0800727 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400728 IO_APIC_REDIR_MASKED, NULL);
729}
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700730
Yinghai Lu3145e942008-12-05 18:58:34 -0800731static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400732{
Yinghai Lu3145e942008-12-05 18:58:34 -0800733 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400734 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
735}
736#endif /* CONFIG_X86_32 */
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700737
Yinghai Lu3145e942008-12-05 18:58:34 -0800738static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739{
Yinghai Lu3145e942008-12-05 18:58:34 -0800740 struct irq_cfg *cfg = desc->chip_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 unsigned long flags;
742
Yinghai Lu3145e942008-12-05 18:58:34 -0800743 BUG_ON(!cfg);
744
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -0800746 __mask_IO_APIC_irq(cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 spin_unlock_irqrestore(&ioapic_lock, flags);
748}
749
Yinghai Lu3145e942008-12-05 18:58:34 -0800750static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751{
Yinghai Lu3145e942008-12-05 18:58:34 -0800752 struct irq_cfg *cfg = desc->chip_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753 unsigned long flags;
754
755 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -0800756 __unmask_IO_APIC_irq(cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757 spin_unlock_irqrestore(&ioapic_lock, flags);
758}
759
Yinghai Lu3145e942008-12-05 18:58:34 -0800760static void mask_IO_APIC_irq(unsigned int irq)
761{
762 struct irq_desc *desc = irq_to_desc(irq);
763
764 mask_IO_APIC_irq_desc(desc);
765}
766static void unmask_IO_APIC_irq(unsigned int irq)
767{
768 struct irq_desc *desc = irq_to_desc(irq);
769
770 unmask_IO_APIC_irq_desc(desc);
771}
772
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
774{
775 struct IO_APIC_route_entry entry;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +0200776
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777 /* Check delivery_mode to be sure we're not clearing an SMI pin */
Andi Kleencf4c6a22006-09-26 10:52:30 +0200778 entry = ioapic_read_entry(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779 if (entry.delivery_mode == dest_SMI)
780 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 /*
782 * Disable it in the IO-APIC irq-routing table:
783 */
Linus Torvaldsf9dadfa2006-11-01 10:05:35 -0800784 ioapic_mask_entry(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785}
786
Ingo Molnar54168ed2008-08-20 09:07:45 +0200787static void clear_IO_APIC (void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788{
789 int apic, pin;
790
791 for (apic = 0; apic < nr_ioapics; apic++)
792 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
793 clear_IO_APIC_pin(apic, pin);
794}
795
Ingo Molnar54168ed2008-08-20 09:07:45 +0200796#if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
Harvey Harrison75604d72008-01-30 13:31:17 +0100797void send_IPI_self(int vector)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798{
799 unsigned int cfg;
800
801 /*
802 * Wait for idle.
803 */
804 apic_wait_icr_idle();
805 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
806 /*
807 * Send the IPI. The write to APIC_ICR fires this off.
808 */
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +0100809 apic_write(APIC_ICR, cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810}
Ingo Molnar54168ed2008-08-20 09:07:45 +0200811#endif /* !CONFIG_SMP && CONFIG_X86_32*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700812
Ingo Molnar54168ed2008-08-20 09:07:45 +0200813#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814/*
815 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
816 * specific CPU-side IRQs.
817 */
818
819#define MAX_PIRQS 8
820static int pirq_entries [MAX_PIRQS];
821static int pirqs_enabled;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823static int __init ioapic_pirq_setup(char *str)
824{
825 int i, max;
826 int ints[MAX_PIRQS+1];
827
828 get_options(str, ARRAY_SIZE(ints), ints);
829
830 for (i = 0; i < MAX_PIRQS; i++)
831 pirq_entries[i] = -1;
832
833 pirqs_enabled = 1;
834 apic_printk(APIC_VERBOSE, KERN_INFO
835 "PIRQ redirection, working around broken MP-BIOS.\n");
836 max = MAX_PIRQS;
837 if (ints[0] < MAX_PIRQS)
838 max = ints[0];
839
840 for (i = 0; i < max; i++) {
841 apic_printk(APIC_VERBOSE, KERN_DEBUG
842 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
843 /*
844 * PIRQs are mapped upside down, usually.
845 */
846 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
847 }
848 return 1;
849}
850
851__setup("pirq=", ioapic_pirq_setup);
Ingo Molnar54168ed2008-08-20 09:07:45 +0200852#endif /* CONFIG_X86_32 */
853
854#ifdef CONFIG_INTR_REMAP
855/* I/O APIC RTE contents at the OS boot up */
856static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
857
858/*
859 * Saves and masks all the unmasked IO-APIC RTE's
860 */
861int save_mask_IO_APIC_setup(void)
862{
863 union IO_APIC_reg_01 reg_01;
864 unsigned long flags;
865 int apic, pin;
866
867 /*
868 * The number of IO-APIC IRQ registers (== #pins):
869 */
870 for (apic = 0; apic < nr_ioapics; apic++) {
871 spin_lock_irqsave(&ioapic_lock, flags);
872 reg_01.raw = io_apic_read(apic, 1);
873 spin_unlock_irqrestore(&ioapic_lock, flags);
874 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
875 }
876
877 for (apic = 0; apic < nr_ioapics; apic++) {
878 early_ioapic_entries[apic] =
879 kzalloc(sizeof(struct IO_APIC_route_entry) *
880 nr_ioapic_registers[apic], GFP_KERNEL);
881 if (!early_ioapic_entries[apic])
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400882 goto nomem;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200883 }
884
885 for (apic = 0; apic < nr_ioapics; apic++)
886 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
887 struct IO_APIC_route_entry entry;
888
889 entry = early_ioapic_entries[apic][pin] =
890 ioapic_read_entry(apic, pin);
891 if (!entry.mask) {
892 entry.mask = 1;
893 ioapic_write_entry(apic, pin, entry);
894 }
895 }
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400896
Ingo Molnar54168ed2008-08-20 09:07:45 +0200897 return 0;
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400898
899nomem:
Cyrill Gorcunovc1370b42008-09-23 23:00:02 +0400900 while (apic >= 0)
901 kfree(early_ioapic_entries[apic--]);
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400902 memset(early_ioapic_entries, 0,
903 ARRAY_SIZE(early_ioapic_entries));
904
905 return -ENOMEM;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200906}
907
908void restore_IO_APIC_setup(void)
909{
910 int apic, pin;
911
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400912 for (apic = 0; apic < nr_ioapics; apic++) {
913 if (!early_ioapic_entries[apic])
914 break;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200915 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
916 ioapic_write_entry(apic, pin,
917 early_ioapic_entries[apic][pin]);
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400918 kfree(early_ioapic_entries[apic]);
919 early_ioapic_entries[apic] = NULL;
920 }
Ingo Molnar54168ed2008-08-20 09:07:45 +0200921}
922
923void reinit_intr_remapped_IO_APIC(int intr_remapping)
924{
925 /*
926 * for now plain restore of previous settings.
927 * TBD: In the case of OS enabling interrupt-remapping,
928 * IO-APIC RTE's need to be setup to point to interrupt-remapping
929 * table entries. for now, do a plain restore, and wait for
930 * the setup_IO_APIC_irqs() to do proper initialization.
931 */
932 restore_IO_APIC_setup();
933}
934#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935
936/*
937 * Find the IRQ entry number of a certain pin.
938 */
939static int find_irq_entry(int apic, int pin, int type)
940{
941 int i;
942
943 for (i = 0; i < mp_irq_entries; i++)
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +0400944 if (mp_irqs[i].mp_irqtype == type &&
945 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
946 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
947 mp_irqs[i].mp_dstirq == pin)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948 return i;
949
950 return -1;
951}
952
953/*
954 * Find the pin to which IRQ[irq] (ISA) is connected
955 */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800956static int __init find_isa_irq_pin(int irq, int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700957{
958 int i;
959
960 for (i = 0; i < mp_irq_entries; i++) {
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +0400961 int lbus = mp_irqs[i].mp_srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700962
Alexey Starikovskiyd27e2b82008-03-20 14:54:18 +0300963 if (test_bit(lbus, mp_bus_not_pci) &&
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +0400964 (mp_irqs[i].mp_irqtype == type) &&
965 (mp_irqs[i].mp_srcbusirq == irq))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700966
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +0400967 return mp_irqs[i].mp_dstirq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968 }
969 return -1;
970}
971
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800972static int __init find_isa_irq_apic(int irq, int type)
973{
974 int i;
975
976 for (i = 0; i < mp_irq_entries; i++) {
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +0400977 int lbus = mp_irqs[i].mp_srcbus;
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800978
Alexey Starikovskiy73b29612008-03-20 14:54:24 +0300979 if (test_bit(lbus, mp_bus_not_pci) &&
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +0400980 (mp_irqs[i].mp_irqtype == type) &&
981 (mp_irqs[i].mp_srcbusirq == irq))
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800982 break;
983 }
984 if (i < mp_irq_entries) {
985 int apic;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200986 for(apic = 0; apic < nr_ioapics; apic++) {
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +0400987 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800988 return apic;
989 }
990 }
991
992 return -1;
993}
994
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995/*
996 * Find a specific PCI IRQ entry.
997 * Not an __init, possibly needed by modules
998 */
999static int pin_2_irq(int idx, int apic, int pin);
1000
1001int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1002{
1003 int apic, i, best_guess = -1;
1004
Ingo Molnar54168ed2008-08-20 09:07:45 +02001005 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1006 bus, slot, pin);
Alexey Starikovskiyce6444d2008-05-19 19:47:09 +04001007 if (test_bit(bus, mp_bus_not_pci)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001008 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 return -1;
1010 }
1011 for (i = 0; i < mp_irq_entries; i++) {
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001012 int lbus = mp_irqs[i].mp_srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013
1014 for (apic = 0; apic < nr_ioapics; apic++)
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001015 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
1016 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017 break;
1018
Alexey Starikovskiy47cab822008-03-20 14:54:30 +03001019 if (!test_bit(lbus, mp_bus_not_pci) &&
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001020 !mp_irqs[i].mp_irqtype &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021 (bus == lbus) &&
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001022 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001023 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024
1025 if (!(apic || IO_APIC_IRQ(irq)))
1026 continue;
1027
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001028 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029 return irq;
1030 /*
1031 * Use the first all-but-pin matching entry as a
1032 * best-guess fuzzy result for broken mptables.
1033 */
1034 if (best_guess < 0)
1035 best_guess = irq;
1036 }
1037 }
1038 return best_guess;
1039}
Ingo Molnar54168ed2008-08-20 09:07:45 +02001040
Alexey Dobriyan129f6942005-06-23 00:08:33 -07001041EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001042
Alexey Starikovskiyc0a282c2008-03-20 14:55:02 +03001043#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044/*
1045 * EISA Edge/Level control register, ELCR
1046 */
1047static int EISA_ELCR(unsigned int irq)
1048{
Yinghai Lu99d093d2008-12-05 18:58:32 -08001049 if (irq < NR_IRQS_LEGACY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050 unsigned int port = 0x4d0 + (irq >> 3);
1051 return (inb(port) >> (irq & 7)) & 1;
1052 }
1053 apic_printk(APIC_VERBOSE, KERN_INFO
1054 "Broken MPtable reports ISA irq %d\n", irq);
1055 return 0;
1056}
Ingo Molnar54168ed2008-08-20 09:07:45 +02001057
Alexey Starikovskiyc0a282c2008-03-20 14:55:02 +03001058#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001059
Alexey Starikovskiy67288012008-03-20 14:54:36 +03001060/* ISA interrupts are always polarity zero edge triggered,
1061 * when listed as conforming in the MP table. */
1062
1063#define default_ISA_trigger(idx) (0)
1064#define default_ISA_polarity(idx) (0)
1065
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066/* EISA interrupts are always polarity zero and can be edge or level
1067 * trigger depending on the ELCR value. If an interrupt is listed as
1068 * EISA conforming in the MP table, that means its trigger type must
1069 * be read in from the ELCR */
1070
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001071#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
Alexey Starikovskiy67288012008-03-20 14:54:36 +03001072#define default_EISA_polarity(idx) default_ISA_polarity(idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073
1074/* PCI interrupts are always polarity one level triggered,
1075 * when listed as conforming in the MP table. */
1076
1077#define default_PCI_trigger(idx) (1)
1078#define default_PCI_polarity(idx) (1)
1079
1080/* MCA interrupts are always polarity zero level triggered,
1081 * when listed as conforming in the MP table. */
1082
1083#define default_MCA_trigger(idx) (1)
Alexey Starikovskiy67288012008-03-20 14:54:36 +03001084#define default_MCA_polarity(idx) default_ISA_polarity(idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085
Shaohua Li61fd47e2007-11-17 01:05:28 -05001086static int MPBIOS_polarity(int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087{
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001088 int bus = mp_irqs[idx].mp_srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089 int polarity;
1090
1091 /*
1092 * Determine IRQ line polarity (high active or low active):
1093 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001094 switch (mp_irqs[idx].mp_irqflag & 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001096 case 0: /* conforms, ie. bus-type dependent polarity */
1097 if (test_bit(bus, mp_bus_not_pci))
1098 polarity = default_ISA_polarity(idx);
1099 else
1100 polarity = default_PCI_polarity(idx);
1101 break;
1102 case 1: /* high active */
1103 {
1104 polarity = 0;
1105 break;
1106 }
1107 case 2: /* reserved */
1108 {
1109 printk(KERN_WARNING "broken BIOS!!\n");
1110 polarity = 1;
1111 break;
1112 }
1113 case 3: /* low active */
1114 {
1115 polarity = 1;
1116 break;
1117 }
1118 default: /* invalid */
1119 {
1120 printk(KERN_WARNING "broken BIOS!!\n");
1121 polarity = 1;
1122 break;
1123 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124 }
1125 return polarity;
1126}
1127
1128static int MPBIOS_trigger(int idx)
1129{
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001130 int bus = mp_irqs[idx].mp_srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001131 int trigger;
1132
1133 /*
1134 * Determine IRQ trigger mode (edge or level sensitive):
1135 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001136 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137 {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001138 case 0: /* conforms, ie. bus-type dependent */
1139 if (test_bit(bus, mp_bus_not_pci))
1140 trigger = default_ISA_trigger(idx);
1141 else
1142 trigger = default_PCI_trigger(idx);
Alexey Starikovskiyc0a282c2008-03-20 14:55:02 +03001143#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
Ingo Molnar54168ed2008-08-20 09:07:45 +02001144 switch (mp_bus_id_to_type[bus]) {
1145 case MP_BUS_ISA: /* ISA pin */
1146 {
1147 /* set before the switch */
1148 break;
1149 }
1150 case MP_BUS_EISA: /* EISA pin */
1151 {
1152 trigger = default_EISA_trigger(idx);
1153 break;
1154 }
1155 case MP_BUS_PCI: /* PCI pin */
1156 {
1157 /* set before the switch */
1158 break;
1159 }
1160 case MP_BUS_MCA: /* MCA pin */
1161 {
1162 trigger = default_MCA_trigger(idx);
1163 break;
1164 }
1165 default:
1166 {
1167 printk(KERN_WARNING "broken BIOS!!\n");
1168 trigger = 1;
1169 break;
1170 }
1171 }
1172#endif
1173 break;
1174 case 1: /* edge */
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001175 {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001176 trigger = 0;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001177 break;
1178 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001179 case 2: /* reserved */
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001180 {
1181 printk(KERN_WARNING "broken BIOS!!\n");
1182 trigger = 1;
1183 break;
1184 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001185 case 3: /* level */
1186 {
1187 trigger = 1;
1188 break;
1189 }
1190 default: /* invalid */
1191 {
1192 printk(KERN_WARNING "broken BIOS!!\n");
1193 trigger = 0;
1194 break;
1195 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196 }
1197 return trigger;
1198}
1199
1200static inline int irq_polarity(int idx)
1201{
1202 return MPBIOS_polarity(idx);
1203}
1204
1205static inline int irq_trigger(int idx)
1206{
1207 return MPBIOS_trigger(idx);
1208}
1209
Yinghai Luefa25592008-08-19 20:50:36 -07001210int (*ioapic_renumber_irq)(int ioapic, int irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211static int pin_2_irq(int idx, int apic, int pin)
1212{
1213 int irq, i;
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001214 int bus = mp_irqs[idx].mp_srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215
1216 /*
1217 * Debugging check, we are in big trouble if this message pops up!
1218 */
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001219 if (mp_irqs[idx].mp_dstirq != pin)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1221
Ingo Molnar54168ed2008-08-20 09:07:45 +02001222 if (test_bit(bus, mp_bus_not_pci)) {
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04001223 irq = mp_irqs[idx].mp_srcbusirq;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001224 } else {
Alexey Starikovskiy643befe2008-03-20 14:54:49 +03001225 /*
1226 * PCI IRQs are mapped in order
1227 */
1228 i = irq = 0;
1229 while (i < apic)
1230 irq += nr_ioapic_registers[i++];
1231 irq += pin;
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001232 /*
Ingo Molnar54168ed2008-08-20 09:07:45 +02001233 * For MPS mode, so far only needed by ES7000 platform
1234 */
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001235 if (ioapic_renumber_irq)
1236 irq = ioapic_renumber_irq(apic, irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237 }
1238
Ingo Molnar54168ed2008-08-20 09:07:45 +02001239#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240 /*
1241 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1242 */
1243 if ((pin >= 16) && (pin <= 23)) {
1244 if (pirq_entries[pin-16] != -1) {
1245 if (!pirq_entries[pin-16]) {
1246 apic_printk(APIC_VERBOSE, KERN_DEBUG
1247 "disabling PIRQ%d\n", pin-16);
1248 } else {
1249 irq = pirq_entries[pin-16];
1250 apic_printk(APIC_VERBOSE, KERN_DEBUG
1251 "using PIRQ%d -> IRQ %d\n",
1252 pin-16, irq);
1253 }
1254 }
1255 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001256#endif
1257
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258 return irq;
1259}
1260
Yinghai Lu497c9a12008-08-19 20:50:28 -07001261void lock_vector_lock(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262{
Yinghai Lu497c9a12008-08-19 20:50:28 -07001263 /* Used to the online set of cpus does not change
1264 * during assign_irq_vector.
1265 */
1266 spin_lock(&vector_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001267}
1268
Yinghai Lu497c9a12008-08-19 20:50:28 -07001269void unlock_vector_lock(void)
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001270{
Yinghai Lu497c9a12008-08-19 20:50:28 -07001271 spin_unlock(&vector_lock);
1272}
1273
Mike Travise7986732008-12-16 17:33:52 -08001274static int
1275__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001276{
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001277 /*
1278 * NOTE! The local APIC isn't very good at handling
1279 * multiple interrupts at the same interrupt level.
1280 * As the interrupt level is determined by taking the
1281 * vector number and shifting that right by 4, we
1282 * want to spread these out a bit so that they don't
1283 * all fall in the same interrupt level.
1284 *
1285 * Also, we've got to be careful not to trash gate
1286 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1287 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001288 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1289 unsigned int old_vector;
Mike Travis22f65d32008-12-16 17:33:56 -08001290 int cpu, err;
1291 cpumask_var_t tmp_mask;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001292
Ingo Molnar54168ed2008-08-20 09:07:45 +02001293 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1294 return -EBUSY;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001295
Mike Travis22f65d32008-12-16 17:33:56 -08001296 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1297 return -ENOMEM;
1298
Ingo Molnar54168ed2008-08-20 09:07:45 +02001299 old_vector = cfg->vector;
1300 if (old_vector) {
Mike Travis22f65d32008-12-16 17:33:56 -08001301 cpumask_and(tmp_mask, mask, cpu_online_mask);
1302 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1303 if (!cpumask_empty(tmp_mask)) {
1304 free_cpumask_var(tmp_mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001305 return 0;
Mike Travis22f65d32008-12-16 17:33:56 -08001306 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001307 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07001308
Mike Travise7986732008-12-16 17:33:52 -08001309 /* Only try and allocate irqs on cpus that are present */
Mike Travis22f65d32008-12-16 17:33:56 -08001310 err = -ENOSPC;
1311 for_each_cpu_and(cpu, mask, cpu_online_mask) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001312 int new_cpu;
1313 int vector, offset;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001314
Mike Travis22f65d32008-12-16 17:33:56 -08001315 vector_allocation_domain(cpu, tmp_mask);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001316
Ingo Molnar54168ed2008-08-20 09:07:45 +02001317 vector = current_vector;
1318 offset = current_offset;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001319next:
Ingo Molnar54168ed2008-08-20 09:07:45 +02001320 vector += 8;
1321 if (vector >= first_system_vector) {
Mike Travise7986732008-12-16 17:33:52 -08001322 /* If out of vectors on large boxen, must share them. */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001323 offset = (offset + 1) % 8;
1324 vector = FIRST_DEVICE_VECTOR + offset;
Yinghai Lu7a959cf2008-08-19 20:50:32 -07001325 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001326 if (unlikely(current_vector == vector))
1327 continue;
1328#ifdef CONFIG_X86_64
1329 if (vector == IA32_SYSCALL_VECTOR)
1330 goto next;
1331#else
1332 if (vector == SYSCALL_VECTOR)
1333 goto next;
1334#endif
Mike Travis22f65d32008-12-16 17:33:56 -08001335 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02001336 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1337 goto next;
1338 /* Found one! */
1339 current_vector = vector;
1340 current_offset = offset;
1341 if (old_vector) {
1342 cfg->move_in_progress = 1;
Mike Travis22f65d32008-12-16 17:33:56 -08001343 cpumask_copy(cfg->old_domain, cfg->domain);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001344 }
Mike Travis22f65d32008-12-16 17:33:56 -08001345 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02001346 per_cpu(vector_irq, new_cpu)[vector] = irq;
1347 cfg->vector = vector;
Mike Travis22f65d32008-12-16 17:33:56 -08001348 cpumask_copy(cfg->domain, tmp_mask);
1349 err = 0;
1350 break;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001351 }
Mike Travis22f65d32008-12-16 17:33:56 -08001352 free_cpumask_var(tmp_mask);
1353 return err;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001354}
1355
Mike Travise7986732008-12-16 17:33:52 -08001356static int
1357assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001358{
1359 int err;
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001360 unsigned long flags;
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001361
1362 spin_lock_irqsave(&vector_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -08001363 err = __assign_irq_vector(irq, cfg, mask);
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001364 spin_unlock_irqrestore(&vector_lock, flags);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001365 return err;
1366}
1367
Yinghai Lu3145e942008-12-05 18:58:34 -08001368static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001369{
Yinghai Lu497c9a12008-08-19 20:50:28 -07001370 int cpu, vector;
1371
Yinghai Lu497c9a12008-08-19 20:50:28 -07001372 BUG_ON(!cfg->vector);
1373
1374 vector = cfg->vector;
Mike Travis22f65d32008-12-16 17:33:56 -08001375 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001376 per_cpu(vector_irq, cpu)[vector] = -1;
1377
1378 cfg->vector = 0;
Mike Travis22f65d32008-12-16 17:33:56 -08001379 cpumask_clear(cfg->domain);
Matthew Wilcox0ca4b6b2008-11-20 14:09:33 -07001380
1381 if (likely(!cfg->move_in_progress))
1382 return;
Mike Travis22f65d32008-12-16 17:33:56 -08001383 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
Matthew Wilcox0ca4b6b2008-11-20 14:09:33 -07001384 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1385 vector++) {
1386 if (per_cpu(vector_irq, cpu)[vector] != irq)
1387 continue;
1388 per_cpu(vector_irq, cpu)[vector] = -1;
1389 break;
1390 }
1391 }
1392 cfg->move_in_progress = 0;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001393}
1394
1395void __setup_vector_irq(int cpu)
1396{
1397 /* Initialize vector_irq on a new cpu */
1398 /* This function must be called with vector_lock held */
1399 int irq, vector;
1400 struct irq_cfg *cfg;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001401 struct irq_desc *desc;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001402
1403 /* Mark the inuse vectors */
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001404 for_each_irq_desc(irq, desc) {
1405 if (!desc)
1406 continue;
1407 cfg = desc->chip_data;
Mike Travis22f65d32008-12-16 17:33:56 -08001408 if (!cpumask_test_cpu(cpu, cfg->domain))
Yinghai Lu497c9a12008-08-19 20:50:28 -07001409 continue;
1410 vector = cfg->vector;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001411 per_cpu(vector_irq, cpu)[vector] = irq;
1412 }
1413 /* Mark the free vectors */
1414 for (vector = 0; vector < NR_VECTORS; ++vector) {
1415 irq = per_cpu(vector_irq, cpu)[vector];
1416 if (irq < 0)
1417 continue;
1418
1419 cfg = irq_cfg(irq);
Mike Travis22f65d32008-12-16 17:33:56 -08001420 if (!cpumask_test_cpu(cpu, cfg->domain))
Yinghai Lu497c9a12008-08-19 20:50:28 -07001421 per_cpu(vector_irq, cpu)[vector] = -1;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001422 }
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001423}
Glauber Costa3fde6902008-05-28 20:34:19 -07001424
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07001425static struct irq_chip ioapic_chip;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001426#ifdef CONFIG_INTR_REMAP
1427static struct irq_chip ir_ioapic_chip;
1428#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429
Ingo Molnar54168ed2008-08-20 09:07:45 +02001430#define IOAPIC_AUTO -1
1431#define IOAPIC_EDGE 0
1432#define IOAPIC_LEVEL 1
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001434#ifdef CONFIG_X86_32
Yinghai Lu1d025192008-08-19 20:50:34 -07001435static inline int IO_APIC_irq_trigger(int irq)
1436{
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001437 int apic, idx, pin;
Yinghai Lu1d025192008-08-19 20:50:34 -07001438
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001439 for (apic = 0; apic < nr_ioapics; apic++) {
1440 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1441 idx = find_irq_entry(apic, pin, mp_INT);
1442 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1443 return irq_trigger(idx);
1444 }
1445 }
1446 /*
Ingo Molnar54168ed2008-08-20 09:07:45 +02001447 * nonexistent IRQs are edge default
1448 */
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001449 return 0;
Yinghai Lu1d025192008-08-19 20:50:34 -07001450}
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001451#else
1452static inline int IO_APIC_irq_trigger(int irq)
1453{
Ingo Molnar54168ed2008-08-20 09:07:45 +02001454 return 1;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001455}
1456#endif
Yinghai Lu1d025192008-08-19 20:50:34 -07001457
Yinghai Lu3145e942008-12-05 18:58:34 -08001458static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001459{
Yinghai Lu199751d2008-08-19 20:50:27 -07001460
Jan Beulich6ebcc002006-06-26 13:56:46 +02001461 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001462 trigger == IOAPIC_LEVEL)
Yinghai Lu08678b02008-08-19 20:50:05 -07001463 desc->status |= IRQ_LEVEL;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001464 else
1465 desc->status &= ~IRQ_LEVEL;
1466
Ingo Molnar54168ed2008-08-20 09:07:45 +02001467#ifdef CONFIG_INTR_REMAP
1468 if (irq_remapped(irq)) {
1469 desc->status |= IRQ_MOVE_PCNTXT;
1470 if (trigger)
1471 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1472 handle_fasteoi_irq,
1473 "fasteoi");
1474 else
1475 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1476 handle_edge_irq, "edge");
1477 return;
1478 }
1479#endif
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001480 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1481 trigger == IOAPIC_LEVEL)
Ingo Molnara460e742006-10-17 00:10:03 -07001482 set_irq_chip_and_handler_name(irq, &ioapic_chip,
Ingo Molnar54168ed2008-08-20 09:07:45 +02001483 handle_fasteoi_irq,
1484 "fasteoi");
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001485 else
Ingo Molnara460e742006-10-17 00:10:03 -07001486 set_irq_chip_and_handler_name(irq, &ioapic_chip,
Ingo Molnar54168ed2008-08-20 09:07:45 +02001487 handle_edge_irq, "edge");
Yinghai Lu497c9a12008-08-19 20:50:28 -07001488}
1489
1490static int setup_ioapic_entry(int apic, int irq,
1491 struct IO_APIC_route_entry *entry,
1492 unsigned int destination, int trigger,
1493 int polarity, int vector)
1494{
1495 /*
1496 * add it to the IO-APIC irq-routing table:
1497 */
1498 memset(entry,0,sizeof(*entry));
1499
Ingo Molnar54168ed2008-08-20 09:07:45 +02001500#ifdef CONFIG_INTR_REMAP
1501 if (intr_remapping_enabled) {
1502 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1503 struct irte irte;
1504 struct IR_IO_APIC_route_entry *ir_entry =
1505 (struct IR_IO_APIC_route_entry *) entry;
1506 int index;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001507
Ingo Molnar54168ed2008-08-20 09:07:45 +02001508 if (!iommu)
1509 panic("No mapping iommu for ioapic %d\n", apic);
1510
1511 index = alloc_irte(iommu, irq, 1);
1512 if (index < 0)
1513 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1514
1515 memset(&irte, 0, sizeof(irte));
1516
1517 irte.present = 1;
1518 irte.dst_mode = INT_DEST_MODE;
1519 irte.trigger_mode = trigger;
1520 irte.dlvry_mode = INT_DELIVERY_MODE;
1521 irte.vector = vector;
1522 irte.dest_id = IRTE_DEST(destination);
1523
1524 modify_irte(irq, &irte);
1525
1526 ir_entry->index2 = (index >> 15) & 0x1;
1527 ir_entry->zero = 0;
1528 ir_entry->format = 1;
1529 ir_entry->index = (index & 0x7fff);
1530 } else
1531#endif
1532 {
1533 entry->delivery_mode = INT_DELIVERY_MODE;
1534 entry->dest_mode = INT_DEST_MODE;
1535 entry->dest = destination;
1536 }
1537
1538 entry->mask = 0; /* enable IRQ */
Yinghai Lu497c9a12008-08-19 20:50:28 -07001539 entry->trigger = trigger;
1540 entry->polarity = polarity;
1541 entry->vector = vector;
1542
1543 /* Mask level triggered irqs.
1544 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1545 */
1546 if (trigger)
1547 entry->mask = 1;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001548 return 0;
1549}
1550
Yinghai Lu3145e942008-12-05 18:58:34 -08001551static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc,
Ingo Molnar54168ed2008-08-20 09:07:45 +02001552 int trigger, int polarity)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001553{
1554 struct irq_cfg *cfg;
1555 struct IO_APIC_route_entry entry;
Mike Travis22f65d32008-12-16 17:33:56 -08001556 unsigned int dest;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001557
1558 if (!IO_APIC_IRQ(irq))
1559 return;
1560
Yinghai Lu3145e942008-12-05 18:58:34 -08001561 cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001562
Mike Travis22f65d32008-12-16 17:33:56 -08001563 if (assign_irq_vector(irq, cfg, TARGET_CPUS))
Yinghai Lu497c9a12008-08-19 20:50:28 -07001564 return;
1565
Mike Travis22f65d32008-12-16 17:33:56 -08001566 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001567
1568 apic_printk(APIC_VERBOSE,KERN_DEBUG
1569 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1570 "IRQ %d Mode:%i Active:%i)\n",
1571 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1572 irq, trigger, polarity);
1573
1574
1575 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
Mike Travis22f65d32008-12-16 17:33:56 -08001576 dest, trigger, polarity, cfg->vector)) {
Yinghai Lu497c9a12008-08-19 20:50:28 -07001577 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1578 mp_ioapics[apic].mp_apicid, pin);
Yinghai Lu3145e942008-12-05 18:58:34 -08001579 __clear_irq_vector(irq, cfg);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001580 return;
1581 }
1582
Yinghai Lu3145e942008-12-05 18:58:34 -08001583 ioapic_register_intr(irq, desc, trigger);
Yinghai Lu99d093d2008-12-05 18:58:32 -08001584 if (irq < NR_IRQS_LEGACY)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001585 disable_8259A_irq(irq);
1586
1587 ioapic_write_entry(apic, pin, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001588}
1589
1590static void __init setup_IO_APIC_irqs(void)
1591{
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001592 int apic, pin, idx, irq;
1593 int notcon = 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001594 struct irq_desc *desc;
Yinghai Lu3145e942008-12-05 18:58:34 -08001595 struct irq_cfg *cfg;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001596 int cpu = boot_cpu_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597
1598 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1599
1600 for (apic = 0; apic < nr_ioapics; apic++) {
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001601 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001603 idx = find_irq_entry(apic, pin, mp_INT);
1604 if (idx == -1) {
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001605 if (!notcon) {
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001606 notcon = 1;
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001607 apic_printk(APIC_VERBOSE,
1608 KERN_DEBUG " %d-%d",
1609 mp_ioapics[apic].mp_apicid,
1610 pin);
1611 } else
1612 apic_printk(APIC_VERBOSE, " %d-%d",
1613 mp_ioapics[apic].mp_apicid,
1614 pin);
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001615 continue;
1616 }
Cyrill Gorcunov56ffa1a2008-09-13 13:11:16 +04001617 if (notcon) {
1618 apic_printk(APIC_VERBOSE,
1619 " (apicid-pin) not connected\n");
1620 notcon = 0;
1621 }
Yinghai Lu20d225b2007-10-17 18:04:41 +02001622
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001623 irq = pin_2_irq(idx, apic, pin);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001624#ifdef CONFIG_X86_32
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001625 if (multi_timer_check(apic, irq))
1626 continue;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001627#endif
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001628 desc = irq_to_desc_alloc_cpu(irq, cpu);
1629 if (!desc) {
1630 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1631 continue;
1632 }
Yinghai Lu3145e942008-12-05 18:58:34 -08001633 cfg = desc->chip_data;
1634 add_pin_to_irq_cpu(cfg, cpu, apic, pin);
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001635
Yinghai Lu3145e942008-12-05 18:58:34 -08001636 setup_IO_APIC_irq(apic, pin, irq, desc,
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001637 irq_trigger(idx), irq_polarity(idx));
1638 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001639 }
1640
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001641 if (notcon)
1642 apic_printk(APIC_VERBOSE,
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001643 " (apicid-pin) not connected\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001644}
1645
1646/*
Maciej W. Rozyckif7633ce2008-05-27 21:19:34 +01001647 * Set up the timer pin, possibly with the 8259A-master behind.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001648 */
Maciej W. Rozyckif7633ce2008-05-27 21:19:34 +01001649static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1650 int vector)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001651{
1652 struct IO_APIC_route_entry entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001653
Ingo Molnar54168ed2008-08-20 09:07:45 +02001654#ifdef CONFIG_INTR_REMAP
1655 if (intr_remapping_enabled)
1656 return;
1657#endif
1658
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001659 memset(&entry, 0, sizeof(entry));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001660
1661 /*
1662 * We use logical delivery to get the timer IRQ
1663 * to the first CPU.
1664 */
1665 entry.dest_mode = INT_DEST_MODE;
Maciej W. Rozycki03be7502008-05-27 21:19:45 +01001666 entry.mask = 1; /* mask IRQ now */
Yinghai Lud83e94a2008-08-19 20:50:33 -07001667 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001668 entry.delivery_mode = INT_DELIVERY_MODE;
1669 entry.polarity = 0;
1670 entry.trigger = 0;
1671 entry.vector = vector;
1672
1673 /*
1674 * The timer IRQ doesn't have to know that behind the
Maciej W. Rozyckif7633ce2008-05-27 21:19:34 +01001675 * scene we may have a 8259A-master in AEOI mode ...
Linus Torvalds1da177e2005-04-16 15:20:36 -07001676 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001677 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001678
1679 /*
1680 * Add it to the IO-APIC irq-routing table:
1681 */
Andi Kleencf4c6a22006-09-26 10:52:30 +02001682 ioapic_write_entry(apic, pin, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683}
1684
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001685
1686__apicdebuginit(void) print_IO_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001687{
1688 int apic, i;
1689 union IO_APIC_reg_00 reg_00;
1690 union IO_APIC_reg_01 reg_01;
1691 union IO_APIC_reg_02 reg_02;
1692 union IO_APIC_reg_03 reg_03;
1693 unsigned long flags;
Yinghai Lu0f978f42008-08-19 20:50:26 -07001694 struct irq_cfg *cfg;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001695 struct irq_desc *desc;
Yinghai Lu8f09cd22008-08-19 20:50:51 -07001696 unsigned int irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697
1698 if (apic_verbosity == APIC_QUIET)
1699 return;
1700
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001701 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001702 for (i = 0; i < nr_ioapics; i++)
1703 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04001704 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001705
1706 /*
1707 * We are a bit conservative about what we expect. We have to
1708 * know about every hardware change ASAP.
1709 */
1710 printk(KERN_INFO "testing the IO APIC.......................\n");
1711
1712 for (apic = 0; apic < nr_ioapics; apic++) {
1713
1714 spin_lock_irqsave(&ioapic_lock, flags);
1715 reg_00.raw = io_apic_read(apic, 0);
1716 reg_01.raw = io_apic_read(apic, 1);
1717 if (reg_01.bits.version >= 0x10)
1718 reg_02.raw = io_apic_read(apic, 2);
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001719 if (reg_01.bits.version >= 0x20)
1720 reg_03.raw = io_apic_read(apic, 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721 spin_unlock_irqrestore(&ioapic_lock, flags);
1722
Ingo Molnar54168ed2008-08-20 09:07:45 +02001723 printk("\n");
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04001724 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1726 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1727 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1728 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001729
Ingo Molnar54168ed2008-08-20 09:07:45 +02001730 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001731 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732
1733 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1734 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001735
1736 /*
1737 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1738 * but the value of reg_02 is read as the previous read register
1739 * value, so ignore it if reg_02 == reg_01.
1740 */
1741 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1742 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1743 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744 }
1745
1746 /*
1747 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1748 * or reg_03, but the value of reg_0[23] is read as the previous read
1749 * register value, so ignore it if reg_03 == reg_0[12].
1750 */
1751 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1752 reg_03.raw != reg_01.raw) {
1753 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1754 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001755 }
1756
1757 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1758
Yinghai Lud83e94a2008-08-19 20:50:33 -07001759 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1760 " Stat Dmod Deli Vect: \n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001761
1762 for (i = 0; i <= reg_01.bits.entries; i++) {
1763 struct IO_APIC_route_entry entry;
1764
Andi Kleencf4c6a22006-09-26 10:52:30 +02001765 entry = ioapic_read_entry(apic, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766
Ingo Molnar54168ed2008-08-20 09:07:45 +02001767 printk(KERN_DEBUG " %02x %03X ",
1768 i,
1769 entry.dest
1770 );
Linus Torvalds1da177e2005-04-16 15:20:36 -07001771
1772 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1773 entry.mask,
1774 entry.trigger,
1775 entry.irr,
1776 entry.polarity,
1777 entry.delivery_status,
1778 entry.dest_mode,
1779 entry.delivery_mode,
1780 entry.vector
1781 );
1782 }
1783 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784 printk(KERN_DEBUG "IRQ to pin mappings:\n");
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001785 for_each_irq_desc(irq, desc) {
1786 struct irq_pin_list *entry;
1787
1788 if (!desc)
1789 continue;
1790 cfg = desc->chip_data;
1791 entry = cfg->irq_2_pin;
Yinghai Lu0f978f42008-08-19 20:50:26 -07001792 if (!entry)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001793 continue;
Yinghai Lu8f09cd22008-08-19 20:50:51 -07001794 printk(KERN_DEBUG "IRQ%d ", irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795 for (;;) {
1796 printk("-> %d:%d", entry->apic, entry->pin);
1797 if (!entry->next)
1798 break;
Yinghai Lu0f978f42008-08-19 20:50:26 -07001799 entry = entry->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001800 }
1801 printk("\n");
1802 }
1803
1804 printk(KERN_INFO ".................................... done.\n");
1805
1806 return;
1807}
1808
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001809__apicdebuginit(void) print_APIC_bitfield(int base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001810{
1811 unsigned int v;
1812 int i, j;
1813
1814 if (apic_verbosity == APIC_QUIET)
1815 return;
1816
1817 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1818 for (i = 0; i < 8; i++) {
1819 v = apic_read(base + i*0x10);
1820 for (j = 0; j < 32; j++) {
1821 if (v & (1<<j))
1822 printk("1");
1823 else
1824 printk("0");
1825 }
1826 printk("\n");
1827 }
1828}
1829
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001830__apicdebuginit(void) print_local_APIC(void *dummy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001831{
1832 unsigned int v, ver, maxlvt;
Hiroshi Shimamoto7ab6af72008-07-30 17:36:48 -07001833 u64 icr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001834
1835 if (apic_verbosity == APIC_QUIET)
1836 return;
1837
1838 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1839 smp_processor_id(), hard_smp_processor_id());
Andreas Herrmann66823112008-06-05 16:35:10 +02001840 v = apic_read(APIC_ID);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001841 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001842 v = apic_read(APIC_LVR);
1843 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1844 ver = GET_APIC_VERSION(v);
Thomas Gleixnere05d7232007-02-16 01:27:58 -08001845 maxlvt = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001846
1847 v = apic_read(APIC_TASKPRI);
1848 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1849
Ingo Molnar54168ed2008-08-20 09:07:45 +02001850 if (APIC_INTEGRATED(ver)) { /* !82489DX */
Yinghai Lua11b5ab2008-09-03 16:58:31 -07001851 if (!APIC_XAPIC(ver)) {
1852 v = apic_read(APIC_ARBPRI);
1853 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1854 v & APIC_ARBPRI_MASK);
1855 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001856 v = apic_read(APIC_PROCPRI);
1857 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1858 }
1859
Yinghai Lua11b5ab2008-09-03 16:58:31 -07001860 /*
1861 * Remote read supported only in the 82489DX and local APIC for
1862 * Pentium processors.
1863 */
1864 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1865 v = apic_read(APIC_RRR);
1866 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1867 }
1868
Linus Torvalds1da177e2005-04-16 15:20:36 -07001869 v = apic_read(APIC_LDR);
1870 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
Yinghai Lua11b5ab2008-09-03 16:58:31 -07001871 if (!x2apic_enabled()) {
1872 v = apic_read(APIC_DFR);
1873 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1874 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875 v = apic_read(APIC_SPIV);
1876 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1877
1878 printk(KERN_DEBUG "... APIC ISR field:\n");
1879 print_APIC_bitfield(APIC_ISR);
1880 printk(KERN_DEBUG "... APIC TMR field:\n");
1881 print_APIC_bitfield(APIC_TMR);
1882 printk(KERN_DEBUG "... APIC IRR field:\n");
1883 print_APIC_bitfield(APIC_IRR);
1884
Ingo Molnar54168ed2008-08-20 09:07:45 +02001885 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1886 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001887 apic_write(APIC_ESR, 0);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001888
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889 v = apic_read(APIC_ESR);
1890 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1891 }
1892
Hiroshi Shimamoto7ab6af72008-07-30 17:36:48 -07001893 icr = apic_icr_read();
Ingo Molnar0c425ce2008-08-18 13:04:26 +02001894 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1895 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896
1897 v = apic_read(APIC_LVTT);
1898 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1899
1900 if (maxlvt > 3) { /* PC is LVT#4. */
1901 v = apic_read(APIC_LVTPC);
1902 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1903 }
1904 v = apic_read(APIC_LVT0);
1905 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1906 v = apic_read(APIC_LVT1);
1907 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1908
1909 if (maxlvt > 2) { /* ERR is LVT#3. */
1910 v = apic_read(APIC_LVTERR);
1911 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1912 }
1913
1914 v = apic_read(APIC_TMICT);
1915 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1916 v = apic_read(APIC_TMCCT);
1917 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1918 v = apic_read(APIC_TDCR);
1919 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1920 printk("\n");
1921}
1922
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001923__apicdebuginit(void) print_all_local_APICs(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001924{
Yinghai Luffd5aae2008-08-19 20:50:50 -07001925 int cpu;
1926
1927 preempt_disable();
1928 for_each_online_cpu(cpu)
1929 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1930 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001931}
1932
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001933__apicdebuginit(void) print_PIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001934{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001935 unsigned int v;
1936 unsigned long flags;
1937
1938 if (apic_verbosity == APIC_QUIET)
1939 return;
1940
1941 printk(KERN_DEBUG "\nprinting PIC contents\n");
1942
1943 spin_lock_irqsave(&i8259A_lock, flags);
1944
1945 v = inb(0xa1) << 8 | inb(0x21);
1946 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1947
1948 v = inb(0xa0) << 8 | inb(0x20);
1949 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1950
Ingo Molnar54168ed2008-08-20 09:07:45 +02001951 outb(0x0b,0xa0);
1952 outb(0x0b,0x20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001953 v = inb(0xa0) << 8 | inb(0x20);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001954 outb(0x0a,0xa0);
1955 outb(0x0a,0x20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001956
1957 spin_unlock_irqrestore(&i8259A_lock, flags);
1958
1959 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1960
1961 v = inb(0x4d1) << 8 | inb(0x4d0);
1962 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1963}
1964
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001965__apicdebuginit(int) print_all_ICs(void)
1966{
1967 print_PIC();
1968 print_all_local_APICs();
1969 print_IO_APIC();
1970
1971 return 0;
1972}
1973
1974fs_initcall(print_all_ICs);
1975
Linus Torvalds1da177e2005-04-16 15:20:36 -07001976
Yinghai Luefa25592008-08-19 20:50:36 -07001977/* Where if anywhere is the i8259 connect in external int mode */
1978static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1979
Ingo Molnar54168ed2008-08-20 09:07:45 +02001980void __init enable_IO_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001981{
1982 union IO_APIC_reg_01 reg_01;
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08001983 int i8259_apic, i8259_pin;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001984 int apic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001985 unsigned long flags;
1986
Ingo Molnar54168ed2008-08-20 09:07:45 +02001987#ifdef CONFIG_X86_32
1988 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001989 if (!pirqs_enabled)
1990 for (i = 0; i < MAX_PIRQS; i++)
1991 pirq_entries[i] = -1;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001992#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001993
1994 /*
1995 * The number of IO-APIC IRQ registers (== #pins):
1996 */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08001997 for (apic = 0; apic < nr_ioapics; apic++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001998 spin_lock_irqsave(&ioapic_lock, flags);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08001999 reg_01.raw = io_apic_read(apic, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002000 spin_unlock_irqrestore(&ioapic_lock, flags);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002001 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2002 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002003 for(apic = 0; apic < nr_ioapics; apic++) {
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002004 int pin;
2005 /* See if any of the pins is in ExtINT mode */
Eric W. Biederman1008fdd2006-01-11 22:46:06 +01002006 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002007 struct IO_APIC_route_entry entry;
Andi Kleencf4c6a22006-09-26 10:52:30 +02002008 entry = ioapic_read_entry(apic, pin);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002009
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002010 /* If the interrupt line is enabled and in ExtInt mode
2011 * I have found the pin where the i8259 is connected.
2012 */
2013 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2014 ioapic_i8259.apic = apic;
2015 ioapic_i8259.pin = pin;
2016 goto found_i8259;
2017 }
2018 }
2019 }
2020 found_i8259:
2021 /* Look to see what if the MP table has reported the ExtINT */
2022 /* If we could not find the appropriate pin by looking at the ioapic
2023 * the i8259 probably is not connected the ioapic but give the
2024 * mptable a chance anyway.
2025 */
2026 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2027 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2028 /* Trust the MP table if nothing is setup in the hardware */
2029 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2030 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2031 ioapic_i8259.pin = i8259_pin;
2032 ioapic_i8259.apic = i8259_apic;
2033 }
2034 /* Complain if the MP table and the hardware disagree */
2035 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2036 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2037 {
2038 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002039 }
2040
2041 /*
2042 * Do not trust the IO-APIC being empty at bootup
2043 */
2044 clear_IO_APIC();
2045}
2046
2047/*
2048 * Not an __init, needed by the reboot code
2049 */
2050void disable_IO_APIC(void)
2051{
2052 /*
2053 * Clear the IO-APIC before rebooting:
2054 */
2055 clear_IO_APIC();
2056
Eric W. Biederman650927e2005-06-25 14:57:44 -07002057 /*
Karsten Wiese0b968d22005-09-09 12:59:04 +02002058 * If the i8259 is routed through an IOAPIC
Eric W. Biederman650927e2005-06-25 14:57:44 -07002059 * Put that IOAPIC in virtual wire mode
Karsten Wiese0b968d22005-09-09 12:59:04 +02002060 * so legacy interrupts can be delivered.
Eric W. Biederman650927e2005-06-25 14:57:44 -07002061 */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002062 if (ioapic_i8259.pin != -1) {
Eric W. Biederman650927e2005-06-25 14:57:44 -07002063 struct IO_APIC_route_entry entry;
Eric W. Biederman650927e2005-06-25 14:57:44 -07002064
2065 memset(&entry, 0, sizeof(entry));
2066 entry.mask = 0; /* Enabled */
2067 entry.trigger = 0; /* Edge */
2068 entry.irr = 0;
2069 entry.polarity = 0; /* High */
2070 entry.delivery_status = 0;
2071 entry.dest_mode = 0; /* Physical */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002072 entry.delivery_mode = dest_ExtINT; /* ExtInt */
Eric W. Biederman650927e2005-06-25 14:57:44 -07002073 entry.vector = 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002074 entry.dest = read_apic_id();
Eric W. Biederman650927e2005-06-25 14:57:44 -07002075
2076 /*
2077 * Add it to the IO-APIC irq-routing table:
2078 */
Andi Kleencf4c6a22006-09-26 10:52:30 +02002079 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
Eric W. Biederman650927e2005-06-25 14:57:44 -07002080 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002081
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002082 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002083}
2084
Ingo Molnar54168ed2008-08-20 09:07:45 +02002085#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -07002086/*
2087 * function to set the IO-APIC physical IDs based on the
2088 * values stored in the MPC table.
2089 *
2090 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2091 */
2092
Linus Torvalds1da177e2005-04-16 15:20:36 -07002093static void __init setup_ioapic_ids_from_mpc(void)
2094{
2095 union IO_APIC_reg_00 reg_00;
2096 physid_mask_t phys_id_present_map;
2097 int apic;
2098 int i;
2099 unsigned char old_id;
2100 unsigned long flags;
2101
Yinghai Lua4dbc342008-07-25 02:14:28 -07002102 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
Yinghai Lud49c4282008-06-08 18:31:54 -07002103 return;
Yinghai Lud49c4282008-06-08 18:31:54 -07002104
Linus Torvalds1da177e2005-04-16 15:20:36 -07002105 /*
Natalie Protasevichca05fea2005-06-23 00:08:22 -07002106 * Don't check I/O APIC IDs for xAPIC systems. They have
2107 * no meaning without the serial APIC bus.
2108 */
Shaohua Li7c5c1e42006-03-23 02:59:53 -08002109 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2110 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
Natalie Protasevichca05fea2005-06-23 00:08:22 -07002111 return;
2112 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002113 * This is broken; anything with a real cpu count has to
2114 * circumvent this idiocy regardless.
2115 */
2116 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2117
2118 /*
2119 * Set the IOAPIC ID to the value stored in the MPC table.
2120 */
2121 for (apic = 0; apic < nr_ioapics; apic++) {
2122
2123 /* Read the register 0 value */
2124 spin_lock_irqsave(&ioapic_lock, flags);
2125 reg_00.raw = io_apic_read(apic, 0);
2126 spin_unlock_irqrestore(&ioapic_lock, flags);
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002127
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002128 old_id = mp_ioapics[apic].mp_apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002129
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002130 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002131 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002132 apic, mp_ioapics[apic].mp_apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002133 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2134 reg_00.bits.ID);
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002135 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002136 }
2137
Linus Torvalds1da177e2005-04-16 15:20:36 -07002138 /*
2139 * Sanity check, is the ID really free? Every APIC in a
2140 * system must have a unique ID or we get lots of nice
2141 * 'stuck on smp_invalidate_needed IPI wait' messages.
2142 */
2143 if (check_apicid_used(phys_id_present_map,
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002144 mp_ioapics[apic].mp_apicid)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002145 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002146 apic, mp_ioapics[apic].mp_apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002147 for (i = 0; i < get_physical_broadcast(); i++)
2148 if (!physid_isset(i, phys_id_present_map))
2149 break;
2150 if (i >= get_physical_broadcast())
2151 panic("Max APIC ID exceeded!\n");
2152 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2153 i);
2154 physid_set(i, phys_id_present_map);
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002155 mp_ioapics[apic].mp_apicid = i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002156 } else {
2157 physid_mask_t tmp;
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002158 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002159 apic_printk(APIC_VERBOSE, "Setting %d in the "
2160 "phys_id_present_map\n",
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002161 mp_ioapics[apic].mp_apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002162 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2163 }
2164
2165
2166 /*
2167 * We need to adjust the IRQ routing table
2168 * if the ID changed.
2169 */
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002170 if (old_id != mp_ioapics[apic].mp_apicid)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002171 for (i = 0; i < mp_irq_entries; i++)
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04002172 if (mp_irqs[i].mp_dstapic == old_id)
2173 mp_irqs[i].mp_dstapic
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002174 = mp_ioapics[apic].mp_apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002175
2176 /*
2177 * Read the right value from the MPC table and
2178 * write it into the ID register.
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002179 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002180 apic_printk(APIC_VERBOSE, KERN_INFO
2181 "...changing IO-APIC physical APIC ID to %d ...",
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002182 mp_ioapics[apic].mp_apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002183
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002184 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002185 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lua2d332f2008-08-21 12:56:32 -07002186 io_apic_write(apic, 0, reg_00.raw);
2187 spin_unlock_irqrestore(&ioapic_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002188
2189 /*
2190 * Sanity check
2191 */
2192 spin_lock_irqsave(&ioapic_lock, flags);
2193 reg_00.raw = io_apic_read(apic, 0);
2194 spin_unlock_irqrestore(&ioapic_lock, flags);
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04002195 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002196 printk("could not set ID!\n");
2197 else
2198 apic_printk(APIC_VERBOSE, " ok.\n");
2199 }
2200}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002201#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002202
Zachary Amsden7ce0bcf2007-02-13 13:26:21 +01002203int no_timer_check __initdata;
Zachary Amsden8542b202006-12-07 02:14:09 +01002204
2205static int __init notimercheck(char *s)
2206{
2207 no_timer_check = 1;
2208 return 1;
2209}
2210__setup("no_timer_check", notimercheck);
2211
Linus Torvalds1da177e2005-04-16 15:20:36 -07002212/*
2213 * There is a nasty bug in some older SMP boards, their mptable lies
2214 * about the timer IRQ. We do the following to work around the situation:
2215 *
2216 * - timer IRQ defaults to IO-APIC IRQ
2217 * - if this function detects that timer IRQs are defunct, then we fall
2218 * back to ISA timer IRQs
2219 */
Adrian Bunkf0a7a5c2007-07-21 17:10:29 +02002220static int __init timer_irq_works(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002221{
2222 unsigned long t1 = jiffies;
Ingo Molnar4aae0702007-12-18 18:05:58 +01002223 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002224
Zachary Amsden8542b202006-12-07 02:14:09 +01002225 if (no_timer_check)
2226 return 1;
2227
Ingo Molnar4aae0702007-12-18 18:05:58 +01002228 local_save_flags(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002229 local_irq_enable();
2230 /* Let ten ticks pass... */
2231 mdelay((10 * 1000) / HZ);
Ingo Molnar4aae0702007-12-18 18:05:58 +01002232 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002233
2234 /*
2235 * Expect a few ticks at least, to be sure some possible
2236 * glue logic does not lock up after one or two first
2237 * ticks in a non-ExtINT mode. Also the local APIC
2238 * might have cached one ExtINT interrupt. Finally, at
2239 * least one tick may be lost due to delays.
2240 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02002241
2242 /* jiffies wrap? */
Julia Lawall1d16b532008-01-30 13:32:19 +01002243 if (time_after(jiffies, t1 + 4))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002244 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002245 return 0;
2246}
2247
2248/*
2249 * In the SMP+IOAPIC case it might happen that there are an unspecified
2250 * number of pending IRQ events unhandled. These cases are very rare,
2251 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2252 * better to do it this way as thus we do not have to be aware of
2253 * 'pending' interrupts in the IRQ path, except at this point.
2254 */
2255/*
2256 * Edge triggered needs to resend any interrupt
2257 * that was delayed but this is now handled in the device
2258 * independent code.
2259 */
2260
2261/*
2262 * Starting up a edge-triggered IO-APIC interrupt is
2263 * nasty - we need to make sure that we get the edge.
2264 * If it is already asserted for some reason, we need
2265 * return 1 to indicate that is was pending.
2266 *
2267 * This is not complete - we should be able to fake
2268 * an edge even if it isn't on the 8259A...
2269 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02002270
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002271static unsigned int startup_ioapic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002272{
2273 int was_pending = 0;
2274 unsigned long flags;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002275 struct irq_cfg *cfg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002276
2277 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu99d093d2008-12-05 18:58:32 -08002278 if (irq < NR_IRQS_LEGACY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002279 disable_8259A_irq(irq);
2280 if (i8259A_irq_pending(irq))
2281 was_pending = 1;
2282 }
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002283 cfg = irq_cfg(irq);
Yinghai Lu3145e942008-12-05 18:58:34 -08002284 __unmask_IO_APIC_irq(cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002285 spin_unlock_irqrestore(&ioapic_lock, flags);
2286
2287 return was_pending;
2288}
2289
Ingo Molnar54168ed2008-08-20 09:07:45 +02002290#ifdef CONFIG_X86_64
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07002291static int ioapic_retrigger_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002292{
Ingo Molnar54168ed2008-08-20 09:07:45 +02002293
2294 struct irq_cfg *cfg = irq_cfg(irq);
2295 unsigned long flags;
2296
2297 spin_lock_irqsave(&vector_lock, flags);
Mike Travis22f65d32008-12-16 17:33:56 -08002298 send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002299 spin_unlock_irqrestore(&vector_lock, flags);
Ingo Molnarc0ad90a2006-06-29 02:24:44 -07002300
2301 return 1;
2302}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002303#else
2304static int ioapic_retrigger_irq(unsigned int irq)
2305{
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002306 send_IPI_self(irq_cfg(irq)->vector);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002307
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002308 return 1;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002309}
2310#endif
2311
2312/*
2313 * Level and edge triggered IO-APIC interrupts need different handling,
2314 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2315 * handled with the level-triggered descriptor, but that one has slightly
2316 * more overhead. Level-triggered interrupts cannot be handled with the
2317 * edge-triggered handler, without risking IRQ storms and other ugly
2318 * races.
2319 */
Ingo Molnarc0ad90a2006-06-29 02:24:44 -07002320
Yinghai Lu497c9a12008-08-19 20:50:28 -07002321#ifdef CONFIG_SMP
Ingo Molnar54168ed2008-08-20 09:07:45 +02002322
2323#ifdef CONFIG_INTR_REMAP
2324static void ir_irq_migration(struct work_struct *work);
2325
2326static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2327
2328/*
2329 * Migrate the IO-APIC irq in the presence of intr-remapping.
2330 *
2331 * For edge triggered, irq migration is a simple atomic update(of vector
2332 * and cpu destination) of IRTE and flush the hardware cache.
2333 *
2334 * For level triggered, we need to modify the io-apic RTE aswell with the update
2335 * vector information, along with modifying IRTE with vector and destination.
2336 * So irq migration for level triggered is little bit more complex compared to
2337 * edge triggered migration. But the good news is, we use the same algorithm
2338 * for level triggered migration as we have today, only difference being,
2339 * we now initiate the irq migration from process context instead of the
2340 * interrupt context.
2341 *
2342 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2343 * suppression) to the IO-APIC, level triggered irq migration will also be
2344 * as simple as edge triggered migration and we can do the irq migration
2345 * with a simple atomic update to IO-APIC RTE.
2346 */
Mike Travise7986732008-12-16 17:33:52 -08002347static void
2348migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02002349{
2350 struct irq_cfg *cfg;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002351 struct irte irte;
2352 int modify_ioapic_rte;
2353 unsigned int dest;
2354 unsigned long flags;
Yinghai Lu3145e942008-12-05 18:58:34 -08002355 unsigned int irq;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002356
Mike Travis22f65d32008-12-16 17:33:56 -08002357 if (!cpumask_intersects(mask, cpu_online_mask))
Ingo Molnar54168ed2008-08-20 09:07:45 +02002358 return;
2359
Yinghai Lu3145e942008-12-05 18:58:34 -08002360 irq = desc->irq;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002361 if (get_irte(irq, &irte))
2362 return;
2363
Yinghai Lu3145e942008-12-05 18:58:34 -08002364 cfg = desc->chip_data;
2365 if (assign_irq_vector(irq, cfg, mask))
Ingo Molnar54168ed2008-08-20 09:07:45 +02002366 return;
2367
Yinghai Lu3145e942008-12-05 18:58:34 -08002368 set_extra_move_desc(desc, mask);
2369
Mike Travis22f65d32008-12-16 17:33:56 -08002370 dest = cpu_mask_to_apicid_and(cfg->domain, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002371
Ingo Molnar54168ed2008-08-20 09:07:45 +02002372 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2373 if (modify_ioapic_rte) {
2374 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -08002375 __target_IO_APIC_irq(irq, dest, cfg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002376 spin_unlock_irqrestore(&ioapic_lock, flags);
2377 }
2378
2379 irte.vector = cfg->vector;
2380 irte.dest_id = IRTE_DEST(dest);
2381
2382 /*
2383 * Modified the IRTE and flushes the Interrupt entry cache.
2384 */
2385 modify_irte(irq, &irte);
2386
Mike Travis22f65d32008-12-16 17:33:56 -08002387 if (cfg->move_in_progress)
2388 send_cleanup_vector(cfg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002389
Mike Travis22f65d32008-12-16 17:33:56 -08002390 cpumask_copy(&desc->affinity, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002391}
2392
Yinghai Lu3145e942008-12-05 18:58:34 -08002393static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
Ingo Molnar54168ed2008-08-20 09:07:45 +02002394{
2395 int ret = -1;
Yinghai Lu3145e942008-12-05 18:58:34 -08002396 struct irq_cfg *cfg = desc->chip_data;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002397
Yinghai Lu3145e942008-12-05 18:58:34 -08002398 mask_IO_APIC_irq_desc(desc);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002399
Yinghai Lu3145e942008-12-05 18:58:34 -08002400 if (io_apic_level_ack_pending(cfg)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02002401 /*
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002402 * Interrupt in progress. Migrating irq now will change the
Ingo Molnar54168ed2008-08-20 09:07:45 +02002403 * vector information in the IO-APIC RTE and that will confuse
2404 * the EOI broadcast performed by cpu.
2405 * So, delay the irq migration to the next instance.
2406 */
2407 schedule_delayed_work(&ir_migration_work, 1);
2408 goto unmask;
2409 }
2410
2411 /* everthing is clear. we have right of way */
Mike Travise7986732008-12-16 17:33:52 -08002412 migrate_ioapic_irq_desc(desc, &desc->pending_mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002413
2414 ret = 0;
2415 desc->status &= ~IRQ_MOVE_PENDING;
Mike Travis22f65d32008-12-16 17:33:56 -08002416 cpumask_clear(&desc->pending_mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002417
2418unmask:
Yinghai Lu3145e942008-12-05 18:58:34 -08002419 unmask_IO_APIC_irq_desc(desc);
2420
Ingo Molnar54168ed2008-08-20 09:07:45 +02002421 return ret;
2422}
2423
2424static void ir_irq_migration(struct work_struct *work)
2425{
2426 unsigned int irq;
2427 struct irq_desc *desc;
2428
2429 for_each_irq_desc(irq, desc) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002430 if (!desc)
2431 continue;
2432
Ingo Molnar54168ed2008-08-20 09:07:45 +02002433 if (desc->status & IRQ_MOVE_PENDING) {
2434 unsigned long flags;
2435
2436 spin_lock_irqsave(&desc->lock, flags);
2437 if (!desc->chip->set_affinity ||
2438 !(desc->status & IRQ_MOVE_PENDING)) {
2439 desc->status &= ~IRQ_MOVE_PENDING;
2440 spin_unlock_irqrestore(&desc->lock, flags);
2441 continue;
2442 }
2443
Rusty Russell0de26522008-12-13 21:20:26 +10302444 desc->chip->set_affinity(irq, &desc->pending_mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002445 spin_unlock_irqrestore(&desc->lock, flags);
2446 }
2447 }
2448}
2449
2450/*
2451 * Migrates the IRQ destination in the process context.
2452 */
Rusty Russell968ea6d2008-12-13 21:55:51 +10302453static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2454 const struct cpumask *mask)
Yinghai Lu3145e942008-12-05 18:58:34 -08002455{
2456 if (desc->status & IRQ_LEVEL) {
2457 desc->status |= IRQ_MOVE_PENDING;
Rusty Russell968ea6d2008-12-13 21:55:51 +10302458 cpumask_copy(&desc->pending_mask, mask);
Yinghai Lu3145e942008-12-05 18:58:34 -08002459 migrate_irq_remapped_level_desc(desc);
2460 return;
2461 }
2462
Mike Travise7986732008-12-16 17:33:52 -08002463 migrate_ioapic_irq_desc(desc, mask);
Yinghai Lu3145e942008-12-05 18:58:34 -08002464}
Rusty Russell0de26522008-12-13 21:20:26 +10302465static void set_ir_ioapic_affinity_irq(unsigned int irq,
2466 const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02002467{
2468 struct irq_desc *desc = irq_to_desc(irq);
2469
Yinghai Lu3145e942008-12-05 18:58:34 -08002470 set_ir_ioapic_affinity_irq_desc(desc, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002471}
2472#endif
2473
Yinghai Lu497c9a12008-08-19 20:50:28 -07002474asmlinkage void smp_irq_move_cleanup_interrupt(void)
2475{
2476 unsigned vector, me;
2477 ack_APIC_irq();
Ingo Molnar54168ed2008-08-20 09:07:45 +02002478#ifdef CONFIG_X86_64
2479 exit_idle();
2480#endif
Yinghai Lu497c9a12008-08-19 20:50:28 -07002481 irq_enter();
2482
2483 me = smp_processor_id();
2484 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2485 unsigned int irq;
2486 struct irq_desc *desc;
2487 struct irq_cfg *cfg;
2488 irq = __get_cpu_var(vector_irq)[vector];
2489
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002490 if (irq == -1)
2491 continue;
2492
Yinghai Lu497c9a12008-08-19 20:50:28 -07002493 desc = irq_to_desc(irq);
2494 if (!desc)
2495 continue;
2496
2497 cfg = irq_cfg(irq);
2498 spin_lock(&desc->lock);
2499 if (!cfg->move_cleanup_count)
2500 goto unlock;
2501
Mike Travis22f65d32008-12-16 17:33:56 -08002502 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
Yinghai Lu497c9a12008-08-19 20:50:28 -07002503 goto unlock;
2504
2505 __get_cpu_var(vector_irq)[vector] = -1;
2506 cfg->move_cleanup_count--;
2507unlock:
2508 spin_unlock(&desc->lock);
2509 }
2510
2511 irq_exit();
2512}
2513
Yinghai Lu3145e942008-12-05 18:58:34 -08002514static void irq_complete_move(struct irq_desc **descp)
Yinghai Lu497c9a12008-08-19 20:50:28 -07002515{
Yinghai Lu3145e942008-12-05 18:58:34 -08002516 struct irq_desc *desc = *descp;
2517 struct irq_cfg *cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -07002518 unsigned vector, me;
2519
Yinghai Lu48a1b102008-12-11 00:15:01 -08002520 if (likely(!cfg->move_in_progress)) {
2521#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2522 if (likely(!cfg->move_desc_pending))
2523 return;
2524
2525 /* domain is not change, but affinity is changed */
2526 me = smp_processor_id();
2527 if (cpu_isset(me, desc->affinity)) {
2528 *descp = desc = move_irq_desc(desc, me);
2529 /* get the new one */
2530 cfg = desc->chip_data;
2531 cfg->move_desc_pending = 0;
2532 }
2533#endif
Yinghai Lu497c9a12008-08-19 20:50:28 -07002534 return;
Yinghai Lu48a1b102008-12-11 00:15:01 -08002535 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07002536
2537 vector = ~get_irq_regs()->orig_ax;
2538 me = smp_processor_id();
Yinghai Lu48a1b102008-12-11 00:15:01 -08002539#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2540 *descp = desc = move_irq_desc(desc, me);
2541 /* get the new one */
2542 cfg = desc->chip_data;
2543#endif
2544
Mike Travis22f65d32008-12-16 17:33:56 -08002545 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2546 send_cleanup_vector(cfg);
Yinghai Lu497c9a12008-08-19 20:50:28 -07002547}
2548#else
Yinghai Lu3145e942008-12-05 18:58:34 -08002549static inline void irq_complete_move(struct irq_desc **descp) {}
Yinghai Lu497c9a12008-08-19 20:50:28 -07002550#endif
Yinghai Lu3145e942008-12-05 18:58:34 -08002551
Ingo Molnar54168ed2008-08-20 09:07:45 +02002552#ifdef CONFIG_INTR_REMAP
2553static void ack_x2apic_level(unsigned int irq)
2554{
2555 ack_x2APIC_irq();
2556}
2557
2558static void ack_x2apic_edge(unsigned int irq)
2559{
2560 ack_x2APIC_irq();
2561}
Yinghai Lu3145e942008-12-05 18:58:34 -08002562
Ingo Molnar54168ed2008-08-20 09:07:45 +02002563#endif
Yinghai Lu497c9a12008-08-19 20:50:28 -07002564
Yinghai Lu1d025192008-08-19 20:50:34 -07002565static void ack_apic_edge(unsigned int irq)
2566{
Yinghai Lu3145e942008-12-05 18:58:34 -08002567 struct irq_desc *desc = irq_to_desc(irq);
2568
2569 irq_complete_move(&desc);
Yinghai Lu1d025192008-08-19 20:50:34 -07002570 move_native_irq(irq);
2571 ack_APIC_irq();
2572}
2573
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002574atomic_t irq_mis_count;
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002575
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002576static void ack_apic_level(unsigned int irq)
2577{
Yinghai Lu3145e942008-12-05 18:58:34 -08002578 struct irq_desc *desc = irq_to_desc(irq);
2579
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002580#ifdef CONFIG_X86_32
2581 unsigned long v;
2582 int i;
2583#endif
Yinghai Lu3145e942008-12-05 18:58:34 -08002584 struct irq_cfg *cfg;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002585 int do_unmask_irq = 0;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002586
Yinghai Lu3145e942008-12-05 18:58:34 -08002587 irq_complete_move(&desc);
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002588#ifdef CONFIG_GENERIC_PENDING_IRQ
Ingo Molnar54168ed2008-08-20 09:07:45 +02002589 /* If we are moving the irq we need to mask it */
Yinghai Lu3145e942008-12-05 18:58:34 -08002590 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02002591 do_unmask_irq = 1;
Yinghai Lu3145e942008-12-05 18:58:34 -08002592 mask_IO_APIC_irq_desc(desc);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002593 }
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002594#endif
2595
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002596#ifdef CONFIG_X86_32
2597 /*
2598 * It appears there is an erratum which affects at least version 0x11
2599 * of I/O APIC (that's the 82093AA and cores integrated into various
2600 * chipsets). Under certain conditions a level-triggered interrupt is
2601 * erroneously delivered as edge-triggered one but the respective IRR
2602 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2603 * message but it will never arrive and further interrupts are blocked
2604 * from the source. The exact reason is so far unknown, but the
2605 * phenomenon was observed when two consecutive interrupt requests
2606 * from a given source get delivered to the same CPU and the source is
2607 * temporarily disabled in between.
2608 *
2609 * A workaround is to simulate an EOI message manually. We achieve it
2610 * by setting the trigger mode to edge and then to level when the edge
2611 * trigger mode gets detected in the TMR of a local APIC for a
2612 * level-triggered interrupt. We mask the source for the time of the
2613 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2614 * The idea is from Manfred Spraul. --macro
2615 */
Yinghai Lu3145e942008-12-05 18:58:34 -08002616 cfg = desc->chip_data;
2617 i = cfg->vector;
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002618
2619 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2620#endif
2621
Ingo Molnar54168ed2008-08-20 09:07:45 +02002622 /*
2623 * We must acknowledge the irq before we move it or the acknowledge will
2624 * not propagate properly.
2625 */
2626 ack_APIC_irq();
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002627
Ingo Molnar54168ed2008-08-20 09:07:45 +02002628 /* Now we can move and renable the irq */
2629 if (unlikely(do_unmask_irq)) {
2630 /* Only migrate the irq if the ack has been received.
2631 *
2632 * On rare occasions the broadcast level triggered ack gets
2633 * delayed going to ioapics, and if we reprogram the
2634 * vector while Remote IRR is still set the irq will never
2635 * fire again.
2636 *
2637 * To prevent this scenario we read the Remote IRR bit
2638 * of the ioapic. This has two effects.
2639 * - On any sane system the read of the ioapic will
2640 * flush writes (and acks) going to the ioapic from
2641 * this cpu.
2642 * - We get to see if the ACK has actually been delivered.
2643 *
2644 * Based on failed experiments of reprogramming the
2645 * ioapic entry from outside of irq context starting
2646 * with masking the ioapic entry and then polling until
2647 * Remote IRR was clear before reprogramming the
2648 * ioapic I don't trust the Remote IRR bit to be
2649 * completey accurate.
2650 *
2651 * However there appears to be no other way to plug
2652 * this race, so if the Remote IRR bit is not
2653 * accurate and is causing problems then it is a hardware bug
2654 * and you can go talk to the chipset vendor about it.
2655 */
Yinghai Lu3145e942008-12-05 18:58:34 -08002656 cfg = desc->chip_data;
2657 if (!io_apic_level_ack_pending(cfg))
Ingo Molnar54168ed2008-08-20 09:07:45 +02002658 move_masked_irq(irq);
Yinghai Lu3145e942008-12-05 18:58:34 -08002659 unmask_IO_APIC_irq_desc(desc);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002660 }
Yinghai Lu1d025192008-08-19 20:50:34 -07002661
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002662#ifdef CONFIG_X86_32
Yinghai Lu1d025192008-08-19 20:50:34 -07002663 if (!(v & (1 << (i & 0x1f)))) {
2664 atomic_inc(&irq_mis_count);
2665 spin_lock(&ioapic_lock);
Yinghai Lu3145e942008-12-05 18:58:34 -08002666 __mask_and_edge_IO_APIC_irq(cfg);
2667 __unmask_and_level_IO_APIC_irq(cfg);
Yinghai Lu1d025192008-08-19 20:50:34 -07002668 spin_unlock(&ioapic_lock);
2669 }
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002670#endif
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002671}
Yinghai Lu1d025192008-08-19 20:50:34 -07002672
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002673static struct irq_chip ioapic_chip __read_mostly = {
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002674 .name = "IO-APIC",
2675 .startup = startup_ioapic_irq,
2676 .mask = mask_IO_APIC_irq,
2677 .unmask = unmask_IO_APIC_irq,
2678 .ack = ack_apic_edge,
2679 .eoi = ack_apic_level,
Ashok Raj54d5d422005-09-06 15:16:15 -07002680#ifdef CONFIG_SMP
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002681 .set_affinity = set_ioapic_affinity_irq,
Ashok Raj54d5d422005-09-06 15:16:15 -07002682#endif
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07002683 .retrigger = ioapic_retrigger_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002684};
2685
Ingo Molnar54168ed2008-08-20 09:07:45 +02002686#ifdef CONFIG_INTR_REMAP
2687static struct irq_chip ir_ioapic_chip __read_mostly = {
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002688 .name = "IR-IO-APIC",
2689 .startup = startup_ioapic_irq,
2690 .mask = mask_IO_APIC_irq,
2691 .unmask = unmask_IO_APIC_irq,
2692 .ack = ack_x2apic_edge,
2693 .eoi = ack_x2apic_level,
Ingo Molnar54168ed2008-08-20 09:07:45 +02002694#ifdef CONFIG_SMP
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002695 .set_affinity = set_ir_ioapic_affinity_irq,
Ingo Molnar54168ed2008-08-20 09:07:45 +02002696#endif
2697 .retrigger = ioapic_retrigger_irq,
2698};
2699#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002700
2701static inline void init_IO_APIC_traps(void)
2702{
2703 int irq;
Yinghai Lu08678b02008-08-19 20:50:05 -07002704 struct irq_desc *desc;
Yinghai Luda51a822008-08-19 20:50:25 -07002705 struct irq_cfg *cfg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002706
2707 /*
2708 * NOTE! The local APIC isn't very good at handling
2709 * multiple interrupts at the same interrupt level.
2710 * As the interrupt level is determined by taking the
2711 * vector number and shifting that right by 4, we
2712 * want to spread these out a bit so that they don't
2713 * all fall in the same interrupt level.
2714 *
2715 * Also, we've got to be careful not to trash gate
2716 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2717 */
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002718 for_each_irq_desc(irq, desc) {
2719 if (!desc)
2720 continue;
2721
2722 cfg = desc->chip_data;
2723 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002724 /*
2725 * Hmm.. We don't have an entry for this,
2726 * so default to an old-fashioned 8259
2727 * interrupt if we can..
2728 */
Yinghai Lu99d093d2008-12-05 18:58:32 -08002729 if (irq < NR_IRQS_LEGACY)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002730 make_8259A_irq(irq);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002731 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07002732 /* Strange. Oh, well.. */
Yinghai Lu08678b02008-08-19 20:50:05 -07002733 desc->chip = &no_irq_chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002734 }
2735 }
2736}
2737
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002738/*
2739 * The local APIC irq-chip implementation:
2740 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002741
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002742static void mask_lapic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002743{
2744 unsigned long v;
2745
2746 v = apic_read(APIC_LVT0);
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01002747 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002748}
2749
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002750static void unmask_lapic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002751{
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002752 unsigned long v;
2753
2754 v = apic_read(APIC_LVT0);
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01002755 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002756}
2757
Yinghai Lu3145e942008-12-05 18:58:34 -08002758static void ack_lapic_irq(unsigned int irq)
Yinghai Lu1d025192008-08-19 20:50:34 -07002759{
2760 ack_APIC_irq();
2761}
2762
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002763static struct irq_chip lapic_chip __read_mostly = {
Maciej W. Rozycki9a1c6192008-05-27 21:19:09 +01002764 .name = "local-APIC",
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002765 .mask = mask_lapic_irq,
2766 .unmask = unmask_lapic_irq,
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002767 .ack = ack_lapic_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002768};
2769
Yinghai Lu3145e942008-12-05 18:58:34 -08002770static void lapic_register_intr(int irq, struct irq_desc *desc)
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002771{
Yinghai Lu08678b02008-08-19 20:50:05 -07002772 desc->status &= ~IRQ_LEVEL;
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002773 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2774 "edge");
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002775}
2776
Jan Beuliche9427102008-01-30 13:31:24 +01002777static void __init setup_nmi(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002778{
2779 /*
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002780 * Dirty trick to enable the NMI watchdog ...
Linus Torvalds1da177e2005-04-16 15:20:36 -07002781 * We put the 8259A master into AEOI mode and
2782 * unmask on all local APICs LVT0 as NMI.
2783 *
2784 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2785 * is from Maciej W. Rozycki - so we do not have to EOI from
2786 * the NMI handler or the timer interrupt.
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002787 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002788 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2789
Jan Beuliche9427102008-01-30 13:31:24 +01002790 enable_NMI_through_LVT0();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002791
2792 apic_printk(APIC_VERBOSE, " done.\n");
2793}
2794
2795/*
2796 * This looks a bit hackish but it's about the only one way of sending
2797 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2798 * not support the ExtINT mode, unfortunately. We need to send these
2799 * cycles as some i82489DX-based boards have glue logic that keeps the
2800 * 8259A interrupt line asserted until INTA. --macro
2801 */
Jacek Luczak28acf282008-04-12 17:41:12 +02002802static inline void __init unlock_ExtINT_logic(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002803{
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002804 int apic, pin, i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002805 struct IO_APIC_route_entry entry0, entry1;
2806 unsigned char save_control, save_freq_select;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002807
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002808 pin = find_isa_irq_pin(8, mp_INT);
Adrian Bunk956fb532006-12-07 02:14:11 +01002809 if (pin == -1) {
2810 WARN_ON_ONCE(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002811 return;
Adrian Bunk956fb532006-12-07 02:14:11 +01002812 }
2813 apic = find_isa_irq_apic(8, mp_INT);
2814 if (apic == -1) {
2815 WARN_ON_ONCE(1);
2816 return;
2817 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002818
Andi Kleencf4c6a22006-09-26 10:52:30 +02002819 entry0 = ioapic_read_entry(apic, pin);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002820 clear_IO_APIC_pin(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002821
2822 memset(&entry1, 0, sizeof(entry1));
2823
2824 entry1.dest_mode = 0; /* physical delivery */
2825 entry1.mask = 0; /* unmask IRQ now */
Yinghai Lud83e94a2008-08-19 20:50:33 -07002826 entry1.dest = hard_smp_processor_id();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002827 entry1.delivery_mode = dest_ExtINT;
2828 entry1.polarity = entry0.polarity;
2829 entry1.trigger = 0;
2830 entry1.vector = 0;
2831
Andi Kleencf4c6a22006-09-26 10:52:30 +02002832 ioapic_write_entry(apic, pin, entry1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002833
2834 save_control = CMOS_READ(RTC_CONTROL);
2835 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2836 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2837 RTC_FREQ_SELECT);
2838 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2839
2840 i = 100;
2841 while (i-- > 0) {
2842 mdelay(10);
2843 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2844 i -= 10;
2845 }
2846
2847 CMOS_WRITE(save_control, RTC_CONTROL);
2848 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002849 clear_IO_APIC_pin(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002850
Andi Kleencf4c6a22006-09-26 10:52:30 +02002851 ioapic_write_entry(apic, pin, entry0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002852}
2853
Yinghai Luefa25592008-08-19 20:50:36 -07002854static int disable_timer_pin_1 __initdata;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002855/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
Ingo Molnar54168ed2008-08-20 09:07:45 +02002856static int __init disable_timer_pin_setup(char *arg)
Yinghai Luefa25592008-08-19 20:50:36 -07002857{
2858 disable_timer_pin_1 = 1;
2859 return 0;
2860}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002861early_param("disable_timer_pin_1", disable_timer_pin_setup);
Yinghai Luefa25592008-08-19 20:50:36 -07002862
2863int timer_through_8259 __initdata;
2864
Linus Torvalds1da177e2005-04-16 15:20:36 -07002865/*
2866 * This code may look a bit paranoid, but it's supposed to cooperate with
2867 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2868 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2869 * fanatically on his truly buggy board.
Ingo Molnar54168ed2008-08-20 09:07:45 +02002870 *
2871 * FIXME: really need to revamp this for all platforms.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002872 */
Zachary Amsden8542b202006-12-07 02:14:09 +01002873static inline void __init check_timer(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002874{
Yinghai Lu3145e942008-12-05 18:58:34 -08002875 struct irq_desc *desc = irq_to_desc(0);
2876 struct irq_cfg *cfg = desc->chip_data;
2877 int cpu = boot_cpu_id;
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002878 int apic1, pin1, apic2, pin2;
Ingo Molnar4aae0702007-12-18 18:05:58 +01002879 unsigned long flags;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002880 unsigned int ver;
2881 int no_pin1 = 0;
Ingo Molnar4aae0702007-12-18 18:05:58 +01002882
2883 local_irq_save(flags);
Maciej W. Rozyckid4d25de2007-11-26 20:42:19 +01002884
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002885 ver = apic_read(APIC_LVR);
2886 ver = GET_APIC_VERSION(ver);
Ingo Molnar6e908942008-03-21 14:32:36 +01002887
Linus Torvalds1da177e2005-04-16 15:20:36 -07002888 /*
2889 * get/set the timer IRQ vector:
2890 */
2891 disable_8259A_irq(0);
Yinghai Lu3145e942008-12-05 18:58:34 -08002892 assign_irq_vector(0, cfg, TARGET_CPUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002893
2894 /*
Maciej W. Rozyckid11d5792008-05-21 22:09:11 +01002895 * As IRQ0 is to be enabled in the 8259A, the virtual
2896 * wire has to be disabled in the local APIC. Also
2897 * timer interrupts need to be acknowledged manually in
2898 * the 8259A for the i82489DX when using the NMI
2899 * watchdog as that APIC treats NMIs as level-triggered.
2900 * The AEOI mode will finish them in the 8259A
2901 * automatically.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002902 */
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01002903 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002904 init_8259A(1);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002905#ifdef CONFIG_X86_32
Maciej W. Rozyckid11d5792008-05-21 22:09:11 +01002906 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
Ingo Molnar54168ed2008-08-20 09:07:45 +02002907#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002908
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002909 pin1 = find_isa_irq_pin(0, mp_INT);
2910 apic1 = find_isa_irq_apic(0, mp_INT);
2911 pin2 = ioapic_i8259.pin;
2912 apic2 = ioapic_i8259.apic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002913
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002914 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2915 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
Yinghai Lu497c9a12008-08-19 20:50:28 -07002916 cfg->vector, apic1, pin1, apic2, pin2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002917
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002918 /*
2919 * Some BIOS writers are clueless and report the ExtINTA
2920 * I/O APIC input from the cascaded 8259A as the timer
2921 * interrupt input. So just in case, if only one pin
2922 * was found above, try it both directly and through the
2923 * 8259A.
2924 */
2925 if (pin1 == -1) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02002926#ifdef CONFIG_INTR_REMAP
2927 if (intr_remapping_enabled)
2928 panic("BIOS bug: timer not connected to IO-APIC");
2929#endif
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002930 pin1 = pin2;
2931 apic1 = apic2;
2932 no_pin1 = 1;
2933 } else if (pin2 == -1) {
2934 pin2 = pin1;
2935 apic2 = apic1;
2936 }
2937
Linus Torvalds1da177e2005-04-16 15:20:36 -07002938 if (pin1 != -1) {
2939 /*
2940 * Ok, does IRQ0 through the IOAPIC work?
2941 */
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002942 if (no_pin1) {
Yinghai Lu3145e942008-12-05 18:58:34 -08002943 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
Yinghai Lu497c9a12008-08-19 20:50:28 -07002944 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002945 }
Yinghai Lu3145e942008-12-05 18:58:34 -08002946 unmask_IO_APIC_irq_desc(desc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002947 if (timer_irq_works()) {
2948 if (nmi_watchdog == NMI_IO_APIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002949 setup_nmi();
2950 enable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002951 }
Chuck Ebbert66759a02005-09-12 18:49:25 +02002952 if (disable_timer_pin_1 > 0)
2953 clear_IO_APIC_pin(0, pin1);
Ingo Molnar4aae0702007-12-18 18:05:58 +01002954 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002955 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002956#ifdef CONFIG_INTR_REMAP
2957 if (intr_remapping_enabled)
2958 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2959#endif
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002960 clear_IO_APIC_pin(apic1, pin1);
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002961 if (!no_pin1)
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002962 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2963 "8254 timer not connected to IO-APIC\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002964
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002965 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2966 "(IRQ0) through the 8259A ...\n");
2967 apic_printk(APIC_QUIET, KERN_INFO
2968 "..... (found apic %d pin %d) ...\n", apic2, pin2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002969 /*
2970 * legacy devices should be connected to IO APIC #0
2971 */
Yinghai Lu3145e942008-12-05 18:58:34 -08002972 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
Yinghai Lu497c9a12008-08-19 20:50:28 -07002973 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
Yinghai Lu3145e942008-12-05 18:58:34 -08002974 unmask_IO_APIC_irq_desc(desc);
Maciej W. Rozyckiecd29472008-05-21 22:09:19 +01002975 enable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002976 if (timer_irq_works()) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002977 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
Maciej W. Rozycki35542c52008-05-21 22:10:22 +01002978 timer_through_8259 = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002979 if (nmi_watchdog == NMI_IO_APIC) {
Maciej W. Rozycki60134eb2008-05-21 22:09:34 +01002980 disable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002981 setup_nmi();
Maciej W. Rozycki60134eb2008-05-21 22:09:34 +01002982 enable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002983 }
Ingo Molnar4aae0702007-12-18 18:05:58 +01002984 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002985 }
2986 /*
2987 * Cleanup, just in case ...
2988 */
Maciej W. Rozyckiecd29472008-05-21 22:09:19 +01002989 disable_8259A_irq(0);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002990 clear_IO_APIC_pin(apic2, pin2);
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002991 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002992 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002993
2994 if (nmi_watchdog == NMI_IO_APIC) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002995 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2996 "through the IO-APIC - disabling NMI Watchdog!\n");
Cyrill Gorcunov067fa0f2008-05-29 22:32:30 +04002997 nmi_watchdog = NMI_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002998 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002999#ifdef CONFIG_X86_32
Maciej W. Rozyckid11d5792008-05-21 22:09:11 +01003000 timer_ack = 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003001#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003002
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003003 apic_printk(APIC_QUIET, KERN_INFO
3004 "...trying to set up timer as Virtual Wire IRQ...\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003005
Yinghai Lu3145e942008-12-05 18:58:34 -08003006 lapic_register_intr(0, desc);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003007 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003008 enable_8259A_irq(0);
3009
3010 if (timer_irq_works()) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003011 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
Ingo Molnar4aae0702007-12-18 18:05:58 +01003012 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003013 }
Maciej W. Rozyckie67465f2008-05-21 22:09:26 +01003014 disable_8259A_irq(0);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003015 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003016 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003017
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003018 apic_printk(APIC_QUIET, KERN_INFO
3019 "...trying to set up timer as ExtINT IRQ...\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003020
Linus Torvalds1da177e2005-04-16 15:20:36 -07003021 init_8259A(0);
3022 make_8259A_irq(0);
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01003023 apic_write(APIC_LVT0, APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003024
3025 unlock_ExtINT_logic();
3026
3027 if (timer_irq_works()) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003028 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
Ingo Molnar4aae0702007-12-18 18:05:58 +01003029 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003030 }
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003031 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003032 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003033 "report. Then try booting with the 'noapic' option.\n");
Ingo Molnar4aae0702007-12-18 18:05:58 +01003034out:
3035 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003036}
3037
3038/*
Maciej W. Rozyckiaf174782008-07-11 19:35:23 +01003039 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3040 * to devices. However there may be an I/O APIC pin available for
3041 * this interrupt regardless. The pin may be left unconnected, but
3042 * typically it will be reused as an ExtINT cascade interrupt for
3043 * the master 8259A. In the MPS case such a pin will normally be
3044 * reported as an ExtINT interrupt in the MP table. With ACPI
3045 * there is no provision for ExtINT interrupts, and in the absence
3046 * of an override it would be treated as an ordinary ISA I/O APIC
3047 * interrupt, that is edge-triggered and unmasked by default. We
3048 * used to do this, but it caused problems on some systems because
3049 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3050 * the same ExtINT cascade interrupt to drive the local APIC of the
3051 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3052 * the I/O APIC in all cases now. No actual device should request
3053 * it anyway. --macro
Linus Torvalds1da177e2005-04-16 15:20:36 -07003054 */
3055#define PIC_IRQS (1 << PIC_CASCADE_IR)
3056
3057void __init setup_IO_APIC(void)
3058{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003059
3060#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -07003061 enable_IO_APIC();
Ingo Molnar54168ed2008-08-20 09:07:45 +02003062#else
3063 /*
3064 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3065 */
3066#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003067
Maciej W. Rozyckiaf174782008-07-11 19:35:23 +01003068 io_apic_irqs = ~PIC_IRQS;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003069
Ingo Molnar54168ed2008-08-20 09:07:45 +02003070 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003071 /*
Ingo Molnar54168ed2008-08-20 09:07:45 +02003072 * Set up IO-APIC IRQ routing.
3073 */
3074#ifdef CONFIG_X86_32
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003075 if (!acpi_ioapic)
3076 setup_ioapic_ids_from_mpc();
Ingo Molnar54168ed2008-08-20 09:07:45 +02003077#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003078 sync_Arb_IDs();
3079 setup_IO_APIC_irqs();
3080 init_IO_APIC_traps();
Linus Torvalds1e4c85f2005-10-31 19:16:17 -08003081 check_timer();
Linus Torvalds1da177e2005-04-16 15:20:36 -07003082}
3083
3084/*
Ingo Molnar54168ed2008-08-20 09:07:45 +02003085 * Called after all the initialization is done. If we didnt find any
3086 * APIC bugs then we can allow the modify fast path
Linus Torvalds1da177e2005-04-16 15:20:36 -07003087 */
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003088
Linus Torvalds1da177e2005-04-16 15:20:36 -07003089static int __init io_apic_bug_finalize(void)
3090{
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003091 if (sis_apic_bug == -1)
3092 sis_apic_bug = 0;
3093 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003094}
3095
3096late_initcall(io_apic_bug_finalize);
3097
3098struct sysfs_ioapic_data {
3099 struct sys_device dev;
3100 struct IO_APIC_route_entry entry[0];
3101};
Ingo Molnar54168ed2008-08-20 09:07:45 +02003102static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
Linus Torvalds1da177e2005-04-16 15:20:36 -07003103
Pavel Machek438510f2005-04-16 15:25:24 -07003104static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003105{
3106 struct IO_APIC_route_entry *entry;
3107 struct sysfs_ioapic_data *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003108 int i;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003109
Linus Torvalds1da177e2005-04-16 15:20:36 -07003110 data = container_of(dev, struct sysfs_ioapic_data, dev);
3111 entry = data->entry;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003112 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3113 *entry = ioapic_read_entry(dev->id, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003114
3115 return 0;
3116}
3117
3118static int ioapic_resume(struct sys_device *dev)
3119{
3120 struct IO_APIC_route_entry *entry;
3121 struct sysfs_ioapic_data *data;
3122 unsigned long flags;
3123 union IO_APIC_reg_00 reg_00;
3124 int i;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003125
Linus Torvalds1da177e2005-04-16 15:20:36 -07003126 data = container_of(dev, struct sysfs_ioapic_data, dev);
3127 entry = data->entry;
3128
3129 spin_lock_irqsave(&ioapic_lock, flags);
3130 reg_00.raw = io_apic_read(dev->id, 0);
Alexey Starikovskiyec2cd0a2008-05-14 19:03:10 +04003131 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
3132 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003133 io_apic_write(dev->id, 0, reg_00.raw);
3134 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003135 spin_unlock_irqrestore(&ioapic_lock, flags);
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003136 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
Andi Kleencf4c6a22006-09-26 10:52:30 +02003137 ioapic_write_entry(dev->id, i, entry[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003138
3139 return 0;
3140}
3141
3142static struct sysdev_class ioapic_sysdev_class = {
Kay Sieversaf5ca3f2007-12-20 02:09:39 +01003143 .name = "ioapic",
Linus Torvalds1da177e2005-04-16 15:20:36 -07003144 .suspend = ioapic_suspend,
3145 .resume = ioapic_resume,
3146};
3147
3148static int __init ioapic_init_sysfs(void)
3149{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003150 struct sys_device * dev;
3151 int i, size, error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003152
3153 error = sysdev_class_register(&ioapic_sysdev_class);
3154 if (error)
3155 return error;
3156
Ingo Molnar54168ed2008-08-20 09:07:45 +02003157 for (i = 0; i < nr_ioapics; i++ ) {
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003158 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
Linus Torvalds1da177e2005-04-16 15:20:36 -07003159 * sizeof(struct IO_APIC_route_entry);
Christophe Jaillet25556c12008-06-22 22:13:48 +02003160 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003161 if (!mp_ioapic_data[i]) {
3162 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3163 continue;
3164 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003165 dev = &mp_ioapic_data[i]->dev;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003166 dev->id = i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003167 dev->cls = &ioapic_sysdev_class;
3168 error = sysdev_register(dev);
3169 if (error) {
3170 kfree(mp_ioapic_data[i]);
3171 mp_ioapic_data[i] = NULL;
3172 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3173 continue;
3174 }
3175 }
3176
3177 return 0;
3178}
3179
3180device_initcall(ioapic_init_sysfs);
3181
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003182/*
Eric W. Biederman95d77882006-10-04 02:17:01 -07003183 * Dynamic irq allocate and deallocation
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003184 */
Yinghai Lu199751d2008-08-19 20:50:27 -07003185unsigned int create_irq_nr(unsigned int irq_want)
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003186{
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003187 /* Allocate an unused irq */
Ingo Molnar54168ed2008-08-20 09:07:45 +02003188 unsigned int irq;
3189 unsigned int new;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003190 unsigned long flags;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003191 struct irq_cfg *cfg_new = NULL;
3192 int cpu = boot_cpu_id;
3193 struct irq_desc *desc_new = NULL;
Yinghai Lu199751d2008-08-19 20:50:27 -07003194
3195 irq = 0;
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003196 spin_lock_irqsave(&vector_lock, flags);
Yinghai Lube5d5352008-12-05 18:58:33 -08003197 for (new = irq_want; new < NR_IRQS; new++) {
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003198 if (platform_legacy_irq(new))
3199 continue;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003200
3201 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3202 if (!desc_new) {
3203 printk(KERN_INFO "can not get irq_desc for %d\n", new);
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003204 continue;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003205 }
3206 cfg_new = desc_new->chip_data;
3207
3208 if (cfg_new->vector != 0)
3209 continue;
Yinghai Lu3145e942008-12-05 18:58:34 -08003210 if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0)
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003211 irq = new;
3212 break;
3213 }
3214 spin_unlock_irqrestore(&vector_lock, flags);
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003215
Yinghai Lu199751d2008-08-19 20:50:27 -07003216 if (irq > 0) {
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003217 dynamic_irq_init(irq);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003218 /* restore it, in case dynamic_irq_init clear it */
3219 if (desc_new)
3220 desc_new->chip_data = cfg_new;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003221 }
3222 return irq;
3223}
3224
Yinghai Lube5d5352008-12-05 18:58:33 -08003225static int nr_irqs_gsi = NR_IRQS_LEGACY;
Yinghai Lu199751d2008-08-19 20:50:27 -07003226int create_irq(void)
3227{
Yinghai Lube5d5352008-12-05 18:58:33 -08003228 unsigned int irq_want;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003229 int irq;
3230
Yinghai Lube5d5352008-12-05 18:58:33 -08003231 irq_want = nr_irqs_gsi;
3232 irq = create_irq_nr(irq_want);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003233
3234 if (irq == 0)
3235 irq = -1;
3236
3237 return irq;
Yinghai Lu199751d2008-08-19 20:50:27 -07003238}
3239
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003240void destroy_irq(unsigned int irq)
3241{
3242 unsigned long flags;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003243 struct irq_cfg *cfg;
3244 struct irq_desc *desc;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003245
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003246 /* store it, in case dynamic_irq_cleanup clear it */
3247 desc = irq_to_desc(irq);
3248 cfg = desc->chip_data;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003249 dynamic_irq_cleanup(irq);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003250 /* connect back irq_cfg */
3251 if (desc)
3252 desc->chip_data = cfg;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003253
Ingo Molnar54168ed2008-08-20 09:07:45 +02003254#ifdef CONFIG_INTR_REMAP
3255 free_irte(irq);
3256#endif
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003257 spin_lock_irqsave(&vector_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -08003258 __clear_irq_vector(irq, cfg);
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003259 spin_unlock_irqrestore(&vector_lock, flags);
3260}
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003261
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003262/*
Simon Arlott27b46d72007-10-20 01:13:56 +02003263 * MSI message composition
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003264 */
3265#ifdef CONFIG_PCI_MSI
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003266static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003267{
Yinghai Lu497c9a12008-08-19 20:50:28 -07003268 struct irq_cfg *cfg;
3269 int err;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003270 unsigned dest;
3271
Yinghai Lu3145e942008-12-05 18:58:34 -08003272 cfg = irq_cfg(irq);
Mike Travis22f65d32008-12-16 17:33:56 -08003273 err = assign_irq_vector(irq, cfg, TARGET_CPUS);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003274 if (err)
3275 return err;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003276
Mike Travis22f65d32008-12-16 17:33:56 -08003277 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003278
Ingo Molnar54168ed2008-08-20 09:07:45 +02003279#ifdef CONFIG_INTR_REMAP
3280 if (irq_remapped(irq)) {
3281 struct irte irte;
3282 int ir_index;
3283 u16 sub_handle;
Yinghai Lu497c9a12008-08-19 20:50:28 -07003284
Ingo Molnar54168ed2008-08-20 09:07:45 +02003285 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3286 BUG_ON(ir_index == -1);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003287
Ingo Molnar54168ed2008-08-20 09:07:45 +02003288 memset (&irte, 0, sizeof(irte));
3289
3290 irte.present = 1;
3291 irte.dst_mode = INT_DEST_MODE;
3292 irte.trigger_mode = 0; /* edge */
3293 irte.dlvry_mode = INT_DELIVERY_MODE;
3294 irte.vector = cfg->vector;
3295 irte.dest_id = IRTE_DEST(dest);
3296
3297 modify_irte(irq, &irte);
3298
3299 msg->address_hi = MSI_ADDR_BASE_HI;
3300 msg->data = sub_handle;
3301 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3302 MSI_ADDR_IR_SHV |
3303 MSI_ADDR_IR_INDEX1(ir_index) |
3304 MSI_ADDR_IR_INDEX2(ir_index);
3305 } else
3306#endif
3307 {
3308 msg->address_hi = MSI_ADDR_BASE_HI;
3309 msg->address_lo =
3310 MSI_ADDR_BASE_LO |
3311 ((INT_DEST_MODE == 0) ?
3312 MSI_ADDR_DEST_MODE_PHYSICAL:
3313 MSI_ADDR_DEST_MODE_LOGICAL) |
3314 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3315 MSI_ADDR_REDIRECTION_CPU:
3316 MSI_ADDR_REDIRECTION_LOWPRI) |
3317 MSI_ADDR_DEST_ID(dest);
3318
3319 msg->data =
3320 MSI_DATA_TRIGGER_EDGE |
3321 MSI_DATA_LEVEL_ASSERT |
3322 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3323 MSI_DATA_DELIVERY_FIXED:
3324 MSI_DATA_DELIVERY_LOWPRI) |
3325 MSI_DATA_VECTOR(cfg->vector);
3326 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07003327 return err;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003328}
3329
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003330#ifdef CONFIG_SMP
Rusty Russell0de26522008-12-13 21:20:26 +10303331static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003332{
Yinghai Lu3145e942008-12-05 18:58:34 -08003333 struct irq_desc *desc = irq_to_desc(irq);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003334 struct irq_cfg *cfg;
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003335 struct msi_msg msg;
3336 unsigned int dest;
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003337
Mike Travis22f65d32008-12-16 17:33:56 -08003338 dest = set_desc_affinity(desc, mask);
3339 if (dest == BAD_APICID)
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003340 return;
3341
Yinghai Lu3145e942008-12-05 18:58:34 -08003342 cfg = desc->chip_data;
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003343
Yinghai Lu3145e942008-12-05 18:58:34 -08003344 read_msi_msg_desc(desc, &msg);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003345
3346 msg.data &= ~MSI_DATA_VECTOR_MASK;
Yinghai Lu497c9a12008-08-19 20:50:28 -07003347 msg.data |= MSI_DATA_VECTOR(cfg->vector);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003348 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3349 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3350
Yinghai Lu3145e942008-12-05 18:58:34 -08003351 write_msi_msg_desc(desc, &msg);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003352}
Ingo Molnar54168ed2008-08-20 09:07:45 +02003353#ifdef CONFIG_INTR_REMAP
3354/*
3355 * Migrate the MSI irq to another cpumask. This migration is
3356 * done in the process context using interrupt-remapping hardware.
3357 */
Mike Travise7986732008-12-16 17:33:52 -08003358static void
3359ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003360{
Yinghai Lu3145e942008-12-05 18:58:34 -08003361 struct irq_desc *desc = irq_to_desc(irq);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003362 struct irq_cfg *cfg;
3363 unsigned int dest;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003364 struct irte irte;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003365
Ingo Molnar54168ed2008-08-20 09:07:45 +02003366 if (get_irte(irq, &irte))
3367 return;
3368
Mike Travis22f65d32008-12-16 17:33:56 -08003369 dest = set_desc_affinity(desc, mask);
3370 if (dest == BAD_APICID)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003371 return;
3372
Ingo Molnar54168ed2008-08-20 09:07:45 +02003373 irte.vector = cfg->vector;
3374 irte.dest_id = IRTE_DEST(dest);
3375
3376 /*
3377 * atomically update the IRTE with the new destination and vector.
3378 */
3379 modify_irte(irq, &irte);
3380
3381 /*
3382 * After this point, all the interrupts will start arriving
3383 * at the new destination. So, time to cleanup the previous
3384 * vector allocation.
3385 */
Mike Travis22f65d32008-12-16 17:33:56 -08003386 if (cfg->move_in_progress)
3387 send_cleanup_vector(cfg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003388}
Yinghai Lu3145e942008-12-05 18:58:34 -08003389
Ingo Molnar54168ed2008-08-20 09:07:45 +02003390#endif
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003391#endif /* CONFIG_SMP */
3392
3393/*
3394 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3395 * which implement the MSI or MSI-X Capability Structure.
3396 */
3397static struct irq_chip msi_chip = {
3398 .name = "PCI-MSI",
3399 .unmask = unmask_msi_irq,
3400 .mask = mask_msi_irq,
Yinghai Lu1d025192008-08-19 20:50:34 -07003401 .ack = ack_apic_edge,
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003402#ifdef CONFIG_SMP
3403 .set_affinity = set_msi_irq_affinity,
3404#endif
3405 .retrigger = ioapic_retrigger_irq,
3406};
3407
Ingo Molnar54168ed2008-08-20 09:07:45 +02003408#ifdef CONFIG_INTR_REMAP
3409static struct irq_chip msi_ir_chip = {
3410 .name = "IR-PCI-MSI",
3411 .unmask = unmask_msi_irq,
3412 .mask = mask_msi_irq,
3413 .ack = ack_x2apic_edge,
3414#ifdef CONFIG_SMP
3415 .set_affinity = ir_set_msi_irq_affinity,
3416#endif
3417 .retrigger = ioapic_retrigger_irq,
3418};
3419
3420/*
3421 * Map the PCI dev to the corresponding remapping hardware unit
3422 * and allocate 'nvec' consecutive interrupt-remapping table entries
3423 * in it.
3424 */
3425static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3426{
3427 struct intel_iommu *iommu;
3428 int index;
3429
3430 iommu = map_dev_to_ir(dev);
3431 if (!iommu) {
3432 printk(KERN_ERR
3433 "Unable to map PCI %s to iommu\n", pci_name(dev));
3434 return -ENOENT;
3435 }
3436
3437 index = alloc_irte(iommu, irq, nvec);
3438 if (index < 0) {
3439 printk(KERN_ERR
3440 "Unable to allocate %d IRTE for PCI %s\n", nvec,
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003441 pci_name(dev));
Ingo Molnar54168ed2008-08-20 09:07:45 +02003442 return -ENOSPC;
3443 }
3444 return index;
3445}
3446#endif
Yinghai Lu1d025192008-08-19 20:50:34 -07003447
Yinghai Lu3145e942008-12-05 18:58:34 -08003448static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
Yinghai Lu1d025192008-08-19 20:50:34 -07003449{
3450 int ret;
3451 struct msi_msg msg;
3452
3453 ret = msi_compose_msg(dev, irq, &msg);
3454 if (ret < 0)
3455 return ret;
3456
Yinghai Lu3145e942008-12-05 18:58:34 -08003457 set_irq_msi(irq, msidesc);
Yinghai Lu1d025192008-08-19 20:50:34 -07003458 write_msi_msg(irq, &msg);
3459
Ingo Molnar54168ed2008-08-20 09:07:45 +02003460#ifdef CONFIG_INTR_REMAP
3461 if (irq_remapped(irq)) {
3462 struct irq_desc *desc = irq_to_desc(irq);
3463 /*
3464 * irq migration in process context
3465 */
3466 desc->status |= IRQ_MOVE_PCNTXT;
3467 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3468 } else
3469#endif
3470 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
Yinghai Lu1d025192008-08-19 20:50:34 -07003471
Yinghai Luc81bba42008-09-25 11:53:11 -07003472 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3473
Yinghai Lu1d025192008-08-19 20:50:34 -07003474 return 0;
3475}
3476
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003477int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc)
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003478{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003479 unsigned int irq;
3480 int ret;
Yinghai Lu199751d2008-08-19 20:50:27 -07003481 unsigned int irq_want;
3482
Yinghai Lube5d5352008-12-05 18:58:33 -08003483 irq_want = nr_irqs_gsi;
Yinghai Lu199751d2008-08-19 20:50:27 -07003484 irq = create_irq_nr(irq_want);
Yinghai Lu199751d2008-08-19 20:50:27 -07003485 if (irq == 0)
3486 return -1;
Eric W. Biedermanf7feaca2007-01-28 12:56:37 -07003487
Ingo Molnar54168ed2008-08-20 09:07:45 +02003488#ifdef CONFIG_INTR_REMAP
3489 if (!intr_remapping_enabled)
3490 goto no_ir;
3491
3492 ret = msi_alloc_irte(dev, irq, 1);
3493 if (ret < 0)
3494 goto error;
3495no_ir:
3496#endif
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003497 ret = setup_msi_irq(dev, msidesc, irq);
Eric W. Biedermanf7feaca2007-01-28 12:56:37 -07003498 if (ret < 0) {
3499 destroy_irq(irq);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003500 return ret;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003501 }
Michael Ellerman7fe37302007-04-18 19:39:21 +10003502 return 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003503
3504#ifdef CONFIG_INTR_REMAP
3505error:
3506 destroy_irq(irq);
3507 return ret;
3508#endif
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003509}
3510
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003511int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3512{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003513 unsigned int irq;
3514 int ret, sub_handle;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003515 struct msi_desc *msidesc;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003516 unsigned int irq_want;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003517
Ingo Molnar54168ed2008-08-20 09:07:45 +02003518#ifdef CONFIG_INTR_REMAP
3519 struct intel_iommu *iommu = 0;
3520 int index = 0;
3521#endif
3522
Yinghai Lube5d5352008-12-05 18:58:33 -08003523 irq_want = nr_irqs_gsi;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003524 sub_handle = 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003525 list_for_each_entry(msidesc, &dev->msi_list, list) {
3526 irq = create_irq_nr(irq_want);
Yinghai Lube5d5352008-12-05 18:58:33 -08003527 irq_want++;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003528 if (irq == 0)
3529 return -1;
3530#ifdef CONFIG_INTR_REMAP
3531 if (!intr_remapping_enabled)
3532 goto no_ir;
3533
3534 if (!sub_handle) {
3535 /*
3536 * allocate the consecutive block of IRTE's
3537 * for 'nvec'
3538 */
3539 index = msi_alloc_irte(dev, irq, nvec);
3540 if (index < 0) {
3541 ret = index;
3542 goto error;
3543 }
3544 } else {
3545 iommu = map_dev_to_ir(dev);
3546 if (!iommu) {
3547 ret = -ENOENT;
3548 goto error;
3549 }
3550 /*
3551 * setup the mapping between the irq and the IRTE
3552 * base index, the sub_handle pointing to the
3553 * appropriate interrupt remap table entry.
3554 */
3555 set_irte_irq(irq, iommu, index, sub_handle);
3556 }
3557no_ir:
3558#endif
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003559 ret = setup_msi_irq(dev, msidesc, irq);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003560 if (ret < 0)
3561 goto error;
3562 sub_handle++;
3563 }
3564 return 0;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003565
3566error:
Ingo Molnar54168ed2008-08-20 09:07:45 +02003567 destroy_irq(irq);
3568 return ret;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003569}
3570
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003571void arch_teardown_msi_irq(unsigned int irq)
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003572{
Eric W. Biedermanf7feaca2007-01-28 12:56:37 -07003573 destroy_irq(irq);
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003574}
3575
Ingo Molnar54168ed2008-08-20 09:07:45 +02003576#ifdef CONFIG_DMAR
3577#ifdef CONFIG_SMP
Mike Travis22f65d32008-12-16 17:33:56 -08003578static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003579{
Yinghai Lu3145e942008-12-05 18:58:34 -08003580 struct irq_desc *desc = irq_to_desc(irq);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003581 struct irq_cfg *cfg;
3582 struct msi_msg msg;
3583 unsigned int dest;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003584
Mike Travis22f65d32008-12-16 17:33:56 -08003585 dest = set_desc_affinity(desc, mask);
3586 if (dest == BAD_APICID)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003587 return;
3588
Yinghai Lu3145e942008-12-05 18:58:34 -08003589 cfg = desc->chip_data;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003590
3591 dmar_msi_read(irq, &msg);
3592
3593 msg.data &= ~MSI_DATA_VECTOR_MASK;
3594 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3595 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3596 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3597
3598 dmar_msi_write(irq, &msg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003599}
Yinghai Lu3145e942008-12-05 18:58:34 -08003600
Ingo Molnar54168ed2008-08-20 09:07:45 +02003601#endif /* CONFIG_SMP */
3602
3603struct irq_chip dmar_msi_type = {
3604 .name = "DMAR_MSI",
3605 .unmask = dmar_msi_unmask,
3606 .mask = dmar_msi_mask,
3607 .ack = ack_apic_edge,
3608#ifdef CONFIG_SMP
3609 .set_affinity = dmar_msi_set_affinity,
3610#endif
3611 .retrigger = ioapic_retrigger_irq,
3612};
3613
3614int arch_setup_dmar_msi(unsigned int irq)
3615{
3616 int ret;
3617 struct msi_msg msg;
3618
3619 ret = msi_compose_msg(NULL, irq, &msg);
3620 if (ret < 0)
3621 return ret;
3622 dmar_msi_write(irq, &msg);
3623 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3624 "edge");
3625 return 0;
3626}
3627#endif
3628
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003629#ifdef CONFIG_HPET_TIMER
3630
3631#ifdef CONFIG_SMP
Mike Travis22f65d32008-12-16 17:33:56 -08003632static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003633{
Yinghai Lu3145e942008-12-05 18:58:34 -08003634 struct irq_desc *desc = irq_to_desc(irq);
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003635 struct irq_cfg *cfg;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003636 struct msi_msg msg;
3637 unsigned int dest;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003638
Mike Travis22f65d32008-12-16 17:33:56 -08003639 dest = set_desc_affinity(desc, mask);
3640 if (dest == BAD_APICID)
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003641 return;
3642
Yinghai Lu3145e942008-12-05 18:58:34 -08003643 cfg = desc->chip_data;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003644
3645 hpet_msi_read(irq, &msg);
3646
3647 msg.data &= ~MSI_DATA_VECTOR_MASK;
3648 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3649 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3650 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3651
3652 hpet_msi_write(irq, &msg);
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003653}
Yinghai Lu3145e942008-12-05 18:58:34 -08003654
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003655#endif /* CONFIG_SMP */
3656
3657struct irq_chip hpet_msi_type = {
3658 .name = "HPET_MSI",
3659 .unmask = hpet_msi_unmask,
3660 .mask = hpet_msi_mask,
3661 .ack = ack_apic_edge,
3662#ifdef CONFIG_SMP
3663 .set_affinity = hpet_msi_set_affinity,
3664#endif
3665 .retrigger = ioapic_retrigger_irq,
3666};
3667
3668int arch_setup_hpet_msi(unsigned int irq)
3669{
3670 int ret;
3671 struct msi_msg msg;
3672
3673 ret = msi_compose_msg(NULL, irq, &msg);
3674 if (ret < 0)
3675 return ret;
3676
3677 hpet_msi_write(irq, &msg);
3678 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3679 "edge");
Yinghai Luc81bba42008-09-25 11:53:11 -07003680
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003681 return 0;
3682}
3683#endif
3684
Ingo Molnar54168ed2008-08-20 09:07:45 +02003685#endif /* CONFIG_PCI_MSI */
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003686/*
3687 * Hypertransport interrupt support
3688 */
3689#ifdef CONFIG_HT_IRQ
3690
3691#ifdef CONFIG_SMP
3692
Yinghai Lu497c9a12008-08-19 20:50:28 -07003693static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003694{
Eric W. Biedermanec683072006-11-08 17:44:57 -08003695 struct ht_irq_msg msg;
3696 fetch_ht_irq_msg(irq, &msg);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003697
Yinghai Lu497c9a12008-08-19 20:50:28 -07003698 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
Eric W. Biedermanec683072006-11-08 17:44:57 -08003699 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003700
Yinghai Lu497c9a12008-08-19 20:50:28 -07003701 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
Eric W. Biedermanec683072006-11-08 17:44:57 -08003702 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003703
Eric W. Biedermanec683072006-11-08 17:44:57 -08003704 write_ht_irq_msg(irq, &msg);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003705}
3706
Mike Travis22f65d32008-12-16 17:33:56 -08003707static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003708{
Yinghai Lu3145e942008-12-05 18:58:34 -08003709 struct irq_desc *desc = irq_to_desc(irq);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003710 struct irq_cfg *cfg;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003711 unsigned int dest;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003712
Mike Travis22f65d32008-12-16 17:33:56 -08003713 dest = set_desc_affinity(desc, mask);
3714 if (dest == BAD_APICID)
Yinghai Lu497c9a12008-08-19 20:50:28 -07003715 return;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003716
Yinghai Lu3145e942008-12-05 18:58:34 -08003717 cfg = desc->chip_data;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003718
Yinghai Lu497c9a12008-08-19 20:50:28 -07003719 target_ht_irq(irq, dest, cfg->vector);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003720}
Yinghai Lu3145e942008-12-05 18:58:34 -08003721
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003722#endif
3723
Aneesh Kumar K.Vc37e1082006-10-11 01:20:43 -07003724static struct irq_chip ht_irq_chip = {
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003725 .name = "PCI-HT",
3726 .mask = mask_ht_irq,
3727 .unmask = unmask_ht_irq,
Yinghai Lu1d025192008-08-19 20:50:34 -07003728 .ack = ack_apic_edge,
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003729#ifdef CONFIG_SMP
3730 .set_affinity = set_ht_irq_affinity,
3731#endif
3732 .retrigger = ioapic_retrigger_irq,
3733};
3734
3735int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3736{
Yinghai Lu497c9a12008-08-19 20:50:28 -07003737 struct irq_cfg *cfg;
3738 int err;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003739
Yinghai Lu3145e942008-12-05 18:58:34 -08003740 cfg = irq_cfg(irq);
Mike Travise7986732008-12-16 17:33:52 -08003741 err = assign_irq_vector(irq, cfg, TARGET_CPUS);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003742 if (!err) {
Eric W. Biedermanec683072006-11-08 17:44:57 -08003743 struct ht_irq_msg msg;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003744 unsigned dest;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003745
Mike Travis22f65d32008-12-16 17:33:56 -08003746 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003747
Eric W. Biedermanec683072006-11-08 17:44:57 -08003748 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003749
Eric W. Biedermanec683072006-11-08 17:44:57 -08003750 msg.address_lo =
3751 HT_IRQ_LOW_BASE |
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003752 HT_IRQ_LOW_DEST_ID(dest) |
Yinghai Lu497c9a12008-08-19 20:50:28 -07003753 HT_IRQ_LOW_VECTOR(cfg->vector) |
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003754 ((INT_DEST_MODE == 0) ?
3755 HT_IRQ_LOW_DM_PHYSICAL :
3756 HT_IRQ_LOW_DM_LOGICAL) |
3757 HT_IRQ_LOW_RQEOI_EDGE |
3758 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3759 HT_IRQ_LOW_MT_FIXED :
3760 HT_IRQ_LOW_MT_ARBITRATED) |
3761 HT_IRQ_LOW_IRQ_MASKED;
3762
Eric W. Biedermanec683072006-11-08 17:44:57 -08003763 write_ht_irq_msg(irq, &msg);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003764
Ingo Molnara460e742006-10-17 00:10:03 -07003765 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3766 handle_edge_irq, "edge");
Yinghai Luc81bba42008-09-25 11:53:11 -07003767
3768 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003769 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07003770 return err;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003771}
3772#endif /* CONFIG_HT_IRQ */
3773
Dean Nelson4173a0e2008-10-02 12:18:21 -05003774#ifdef CONFIG_X86_64
3775/*
3776 * Re-target the irq to the specified CPU and enable the specified MMR located
3777 * on the specified blade to allow the sending of MSIs to the specified CPU.
3778 */
3779int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3780 unsigned long mmr_offset)
3781{
Mike Travis22f65d32008-12-16 17:33:56 -08003782 const struct cpumask *eligible_cpu = cpumask_of(cpu);
Dean Nelson4173a0e2008-10-02 12:18:21 -05003783 struct irq_cfg *cfg;
3784 int mmr_pnode;
3785 unsigned long mmr_value;
3786 struct uv_IO_APIC_route_entry *entry;
3787 unsigned long flags;
3788 int err;
3789
Yinghai Lu3145e942008-12-05 18:58:34 -08003790 cfg = irq_cfg(irq);
3791
Mike Travise7986732008-12-16 17:33:52 -08003792 err = assign_irq_vector(irq, cfg, eligible_cpu);
Dean Nelson4173a0e2008-10-02 12:18:21 -05003793 if (err != 0)
3794 return err;
3795
3796 spin_lock_irqsave(&vector_lock, flags);
3797 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3798 irq_name);
3799 spin_unlock_irqrestore(&vector_lock, flags);
3800
Dean Nelson4173a0e2008-10-02 12:18:21 -05003801 mmr_value = 0;
3802 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3803 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3804
3805 entry->vector = cfg->vector;
3806 entry->delivery_mode = INT_DELIVERY_MODE;
3807 entry->dest_mode = INT_DEST_MODE;
3808 entry->polarity = 0;
3809 entry->trigger = 0;
3810 entry->mask = 0;
Mike Travise7986732008-12-16 17:33:52 -08003811 entry->dest = cpu_mask_to_apicid(eligible_cpu);
Dean Nelson4173a0e2008-10-02 12:18:21 -05003812
3813 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3814 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3815
3816 return irq;
3817}
3818
3819/*
3820 * Disable the specified MMR located on the specified blade so that MSIs are
3821 * longer allowed to be sent.
3822 */
3823void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3824{
3825 unsigned long mmr_value;
3826 struct uv_IO_APIC_route_entry *entry;
3827 int mmr_pnode;
3828
3829 mmr_value = 0;
3830 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3831 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3832
3833 entry->mask = 1;
3834
3835 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3836 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3837}
3838#endif /* CONFIG_X86_64 */
3839
Yinghai Lu9d6a4d02008-08-19 20:50:52 -07003840int __init io_apic_get_redir_entries (int ioapic)
3841{
3842 union IO_APIC_reg_01 reg_01;
3843 unsigned long flags;
3844
3845 spin_lock_irqsave(&ioapic_lock, flags);
3846 reg_01.raw = io_apic_read(ioapic, 1);
3847 spin_unlock_irqrestore(&ioapic_lock, flags);
3848
3849 return reg_01.bits.entries;
3850}
3851
Yinghai Lube5d5352008-12-05 18:58:33 -08003852void __init probe_nr_irqs_gsi(void)
Yinghai Lu9d6a4d02008-08-19 20:50:52 -07003853{
Yinghai Lube5d5352008-12-05 18:58:33 -08003854 int idx;
3855 int nr = 0;
3856
3857 for (idx = 0; idx < nr_ioapics; idx++)
3858 nr += io_apic_get_redir_entries(idx) + 1;
3859
3860 if (nr > nr_irqs_gsi)
3861 nr_irqs_gsi = nr;
Yinghai Lu9d6a4d02008-08-19 20:50:52 -07003862}
3863
Linus Torvalds1da177e2005-04-16 15:20:36 -07003864/* --------------------------------------------------------------------------
Ingo Molnar54168ed2008-08-20 09:07:45 +02003865 ACPI-based IOAPIC Configuration
Linus Torvalds1da177e2005-04-16 15:20:36 -07003866 -------------------------------------------------------------------------- */
3867
Len Brown888ba6c2005-08-24 12:07:20 -04003868#ifdef CONFIG_ACPI
Linus Torvalds1da177e2005-04-16 15:20:36 -07003869
Ingo Molnar54168ed2008-08-20 09:07:45 +02003870#ifdef CONFIG_X86_32
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003871int __init io_apic_get_unique_id(int ioapic, int apic_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003872{
3873 union IO_APIC_reg_00 reg_00;
3874 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3875 physid_mask_t tmp;
3876 unsigned long flags;
3877 int i = 0;
3878
3879 /*
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003880 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3881 * buses (one for LAPICs, one for IOAPICs), where predecessors only
Linus Torvalds1da177e2005-04-16 15:20:36 -07003882 * supports up to 16 on one shared APIC bus.
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003883 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07003884 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3885 * advantage of new APIC bus architecture.
3886 */
3887
3888 if (physids_empty(apic_id_map))
3889 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3890
3891 spin_lock_irqsave(&ioapic_lock, flags);
3892 reg_00.raw = io_apic_read(ioapic, 0);
3893 spin_unlock_irqrestore(&ioapic_lock, flags);
3894
3895 if (apic_id >= get_physical_broadcast()) {
3896 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3897 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3898 apic_id = reg_00.bits.ID;
3899 }
3900
3901 /*
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003902 * Every APIC in a system must have a unique ID or we get lots of nice
Linus Torvalds1da177e2005-04-16 15:20:36 -07003903 * 'stuck on smp_invalidate_needed IPI wait' messages.
3904 */
3905 if (check_apicid_used(apic_id_map, apic_id)) {
3906
3907 for (i = 0; i < get_physical_broadcast(); i++) {
3908 if (!check_apicid_used(apic_id_map, i))
3909 break;
3910 }
3911
3912 if (i == get_physical_broadcast())
3913 panic("Max apic_id exceeded!\n");
3914
3915 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3916 "trying %d\n", ioapic, apic_id, i);
3917
3918 apic_id = i;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003919 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003920
3921 tmp = apicid_to_cpu_present(apic_id);
3922 physids_or(apic_id_map, apic_id_map, tmp);
3923
3924 if (reg_00.bits.ID != apic_id) {
3925 reg_00.bits.ID = apic_id;
3926
3927 spin_lock_irqsave(&ioapic_lock, flags);
3928 io_apic_write(ioapic, 0, reg_00.raw);
3929 reg_00.raw = io_apic_read(ioapic, 0);
3930 spin_unlock_irqrestore(&ioapic_lock, flags);
3931
3932 /* Sanity check */
Andreas Deresch6070f9e2006-02-26 04:18:34 +01003933 if (reg_00.bits.ID != apic_id) {
3934 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3935 return -1;
3936 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003937 }
3938
3939 apic_printk(APIC_VERBOSE, KERN_INFO
3940 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3941
3942 return apic_id;
3943}
3944
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003945int __init io_apic_get_version(int ioapic)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003946{
3947 union IO_APIC_reg_01 reg_01;
3948 unsigned long flags;
3949
3950 spin_lock_irqsave(&ioapic_lock, flags);
3951 reg_01.raw = io_apic_read(ioapic, 1);
3952 spin_unlock_irqrestore(&ioapic_lock, flags);
3953
3954 return reg_01.bits.version;
3955}
Ingo Molnar54168ed2008-08-20 09:07:45 +02003956#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003957
Ingo Molnar54168ed2008-08-20 09:07:45 +02003958int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003959{
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003960 struct irq_desc *desc;
3961 struct irq_cfg *cfg;
3962 int cpu = boot_cpu_id;
3963
Linus Torvalds1da177e2005-04-16 15:20:36 -07003964 if (!IO_APIC_IRQ(irq)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02003965 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07003966 ioapic);
3967 return -EINVAL;
3968 }
3969
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003970 desc = irq_to_desc_alloc_cpu(irq, cpu);
3971 if (!desc) {
3972 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3973 return 0;
3974 }
3975
Linus Torvalds1da177e2005-04-16 15:20:36 -07003976 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003977 * IRQs < 16 are already in the irq_2_pin[] map
3978 */
Yinghai Lu99d093d2008-12-05 18:58:32 -08003979 if (irq >= NR_IRQS_LEGACY) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003980 cfg = desc->chip_data;
Yinghai Lu3145e942008-12-05 18:58:34 -08003981 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003982 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003983
Yinghai Lu3145e942008-12-05 18:58:34 -08003984 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003985
3986 return 0;
3987}
3988
Ingo Molnar54168ed2008-08-20 09:07:45 +02003989
Shaohua Li61fd47e2007-11-17 01:05:28 -05003990int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3991{
3992 int i;
3993
3994 if (skip_ioapic_setup)
3995 return -1;
3996
3997 for (i = 0; i < mp_irq_entries; i++)
Alexey Starikovskiy2fddb6e282008-05-14 19:03:17 +04003998 if (mp_irqs[i].mp_irqtype == mp_INT &&
3999 mp_irqs[i].mp_srcbusirq == bus_irq)
Shaohua Li61fd47e2007-11-17 01:05:28 -05004000 break;
4001 if (i >= mp_irq_entries)
4002 return -1;
4003
4004 *trigger = irq_trigger(i);
4005 *polarity = irq_polarity(i);
4006 return 0;
4007}
4008
Len Brown888ba6c2005-08-24 12:07:20 -04004009#endif /* CONFIG_ACPI */
Rusty Russell1a3f2392006-09-26 10:52:32 +02004010
Yinghai Lu497c9a12008-08-19 20:50:28 -07004011/*
4012 * This function currently is only a helper for the i386 smp boot process where
4013 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4014 * so mask in all cases should simply be TARGET_CPUS
4015 */
4016#ifdef CONFIG_SMP
4017void __init setup_ioapic_dest(void)
4018{
4019 int pin, ioapic, irq, irq_entry;
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004020 struct irq_desc *desc;
Yinghai Lu497c9a12008-08-19 20:50:28 -07004021 struct irq_cfg *cfg;
Mike Travis22f65d32008-12-16 17:33:56 -08004022 const struct cpumask *mask;
Yinghai Lu497c9a12008-08-19 20:50:28 -07004023
4024 if (skip_ioapic_setup == 1)
4025 return;
4026
4027 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4028 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4029 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4030 if (irq_entry == -1)
4031 continue;
4032 irq = pin_2_irq(irq_entry, ioapic, pin);
4033
4034 /* setup_IO_APIC_irqs could fail to get vector for some device
4035 * when you have too many devices, because at that time only boot
4036 * cpu is online.
4037 */
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08004038 desc = irq_to_desc(irq);
4039 cfg = desc->chip_data;
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004040 if (!cfg->vector) {
Yinghai Lu3145e942008-12-05 18:58:34 -08004041 setup_IO_APIC_irq(ioapic, pin, irq, desc,
Yinghai Lu497c9a12008-08-19 20:50:28 -07004042 irq_trigger(irq_entry),
4043 irq_polarity(irq_entry));
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004044 continue;
4045
4046 }
4047
4048 /*
4049 * Honour affinities which have been set in early boot
4050 */
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004051 if (desc->status &
4052 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
Mike Travise7986732008-12-16 17:33:52 -08004053 mask = &desc->affinity;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004054 else
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004055 mask = TARGET_CPUS;
4056
4057#ifdef CONFIG_INTR_REMAP
4058 if (intr_remapping_enabled)
Mike Travise7986732008-12-16 17:33:52 -08004059 set_ir_ioapic_affinity_irq_desc(desc, mask);
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004060 else
4061#endif
Mike Travise7986732008-12-16 17:33:52 -08004062 set_ioapic_affinity_irq_desc(desc, mask);
Yinghai Lu497c9a12008-08-19 20:50:28 -07004063 }
4064
4065 }
4066}
4067#endif
4068
Ingo Molnar54168ed2008-08-20 09:07:45 +02004069#define IOAPIC_RESOURCE_NAME_SIZE 11
4070
4071static struct resource *ioapic_resources;
4072
4073static struct resource * __init ioapic_setup_resources(void)
4074{
4075 unsigned long n;
4076 struct resource *res;
4077 char *mem;
4078 int i;
4079
4080 if (nr_ioapics <= 0)
4081 return NULL;
4082
4083 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4084 n *= nr_ioapics;
4085
4086 mem = alloc_bootmem(n);
4087 res = (void *)mem;
4088
4089 if (mem != NULL) {
4090 mem += sizeof(struct resource) * nr_ioapics;
4091
4092 for (i = 0; i < nr_ioapics; i++) {
4093 res[i].name = mem;
4094 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4095 sprintf(mem, "IOAPIC %u", i);
4096 mem += IOAPIC_RESOURCE_NAME_SIZE;
4097 }
4098 }
4099
4100 ioapic_resources = res;
4101
4102 return res;
4103}
Ingo Molnar54168ed2008-08-20 09:07:45 +02004104
Yinghai Luf3294a32008-06-27 01:41:56 -07004105void __init ioapic_init_mappings(void)
4106{
4107 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004108 struct resource *ioapic_res;
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02004109 int i;
Yinghai Luf3294a32008-06-27 01:41:56 -07004110
Ingo Molnar54168ed2008-08-20 09:07:45 +02004111 ioapic_res = ioapic_setup_resources();
Yinghai Luf3294a32008-06-27 01:41:56 -07004112 for (i = 0; i < nr_ioapics; i++) {
4113 if (smp_found_config) {
4114 ioapic_phys = mp_ioapics[i].mp_apicaddr;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004115#ifdef CONFIG_X86_32
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02004116 if (!ioapic_phys) {
4117 printk(KERN_ERR
4118 "WARNING: bogus zero IO-APIC "
4119 "address found in MPTABLE, "
4120 "disabling IO/APIC support!\n");
4121 smp_found_config = 0;
4122 skip_ioapic_setup = 1;
4123 goto fake_ioapic_page;
4124 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02004125#endif
Yinghai Luf3294a32008-06-27 01:41:56 -07004126 } else {
Ingo Molnar54168ed2008-08-20 09:07:45 +02004127#ifdef CONFIG_X86_32
Yinghai Luf3294a32008-06-27 01:41:56 -07004128fake_ioapic_page:
Ingo Molnar54168ed2008-08-20 09:07:45 +02004129#endif
Yinghai Luf3294a32008-06-27 01:41:56 -07004130 ioapic_phys = (unsigned long)
Ingo Molnar54168ed2008-08-20 09:07:45 +02004131 alloc_bootmem_pages(PAGE_SIZE);
Yinghai Luf3294a32008-06-27 01:41:56 -07004132 ioapic_phys = __pa(ioapic_phys);
4133 }
4134 set_fixmap_nocache(idx, ioapic_phys);
Ingo Molnar54168ed2008-08-20 09:07:45 +02004135 apic_printk(APIC_VERBOSE,
4136 "mapped IOAPIC to %08lx (%08lx)\n",
4137 __fix_to_virt(idx), ioapic_phys);
Yinghai Luf3294a32008-06-27 01:41:56 -07004138 idx++;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004139
Ingo Molnar54168ed2008-08-20 09:07:45 +02004140 if (ioapic_res != NULL) {
4141 ioapic_res->start = ioapic_phys;
4142 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4143 ioapic_res++;
4144 }
Yinghai Luf3294a32008-06-27 01:41:56 -07004145 }
4146}
4147
Ingo Molnar54168ed2008-08-20 09:07:45 +02004148static int __init ioapic_insert_resources(void)
4149{
4150 int i;
4151 struct resource *r = ioapic_resources;
4152
4153 if (!r) {
4154 printk(KERN_ERR
4155 "IO APIC resources could be not be allocated.\n");
4156 return -1;
4157 }
4158
4159 for (i = 0; i < nr_ioapics; i++) {
4160 insert_resource(&iomem_resource, r);
4161 r++;
4162 }
4163
4164 return 0;
4165}
4166
4167/* Insert the IO APIC resources after PCI initialization has occured to handle
4168 * IO APICS that are mapped in on a BAR in PCI space. */
4169late_initcall(ioapic_insert_resources);