blob: 5b708208b607b4b1eeaf7411040c56784fd93df5 [file] [log] [blame]
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +02001/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
17 */
18
19/include/ "skeleton.dtsi"
20
21/ {
22 model = "Marvell Armada 370 and XP SoC";
Thomas Petazzoni92ece1c2012-11-09 16:29:17 +010023 compatible = "marvell,armada-370-xp";
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020024
25 cpus {
26 cpu@0 {
27 compatible = "marvell,sheeva-v7";
28 };
29 };
30
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020034 #size-cells = <1>;
35 interrupt-controller;
36 };
37
Gregory CLEMENT009f1312012-08-02 11:16:29 +030038 coherency-fabric@d0020200 {
39 compatible = "marvell,coherency-fabric";
Gregory CLEMENTe60304f2012-10-12 19:20:36 +020040 reg = <0xd0020200 0xb0>,
41 <0xd0021810 0x1c>;
Gregory CLEMENT009f1312012-08-02 11:16:29 +030042 };
43
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020044 soc {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "simple-bus";
48 interrupt-parent = <&mpic>;
49 ranges;
50
51 serial@d0012000 {
Gregory CLEMENTb24212f2012-12-04 18:04:59 +010052 compatible = "snps,dw-apb-uart";
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020053 reg = <0xd0012000 0x100>;
54 reg-shift = <2>;
55 interrupts = <41>;
Heikki Krogeruse3661542013-03-06 11:23:33 +010056 reg-io-width = <1>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020057 status = "disabled";
58 };
59 serial@d0012100 {
Gregory CLEMENTb24212f2012-12-04 18:04:59 +010060 compatible = "snps,dw-apb-uart";
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020061 reg = <0xd0012100 0x100>;
62 reg-shift = <2>;
63 interrupts = <42>;
Heikki Krogeruse3661542013-03-06 11:23:33 +010064 reg-io-width = <1>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020065 status = "disabled";
66 };
67
68 timer@d0020300 {
69 compatible = "marvell,armada-370-xp-timer";
Gregory CLEMENTe1dd4642013-01-25 18:32:44 +010070 reg = <0xd0020300 0x30>,
71 <0xd0021040 0x30>;
72 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
Gregory CLEMENT307c2bf2012-11-17 15:22:25 +010073 clocks = <&coreclk 2>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020074 };
Thomas Petazzoni5b40bae2012-09-11 14:27:30 +020075
76 addr-decoding@d0020000 {
77 compatible = "marvell,armada-addr-decoding-controller";
78 reg = <0xd0020000 0x258>;
79 };
Gregory CLEMENTa6a6de12012-10-26 14:30:47 +020080
81 sata@d00a0000 {
82 compatible = "marvell,orion-sata";
83 reg = <0xd00a0000 0x2400>;
84 interrupts = <55>;
85 clocks = <&gateclk 15>, <&gateclk 30>;
86 clock-names = "0", "1";
87 status = "disabled";
88 };
89
Thomas Petazzoni323c1012012-09-04 15:06:43 +020090 mdio {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "marvell,orion-mdio";
94 reg = <0xd0072004 0x4>;
95 };
96
97 ethernet@d0070000 {
98 compatible = "marvell,armada-370-neta";
99 reg = <0xd0070000 0x2500>;
100 interrupts = <8>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +0100101 clocks = <&gateclk 4>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200102 status = "disabled";
103 };
104
105 ethernet@d0074000 {
106 compatible = "marvell,armada-370-neta";
107 reg = <0xd0074000 0x2500>;
108 interrupts = <10>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +0100109 clocks = <&gateclk 3>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200110 status = "disabled";
111 };
Nobuhiro Iwamatsu539eb5b2012-10-30 19:41:23 +0900112
113 i2c0: i2c@d0011000 {
114 compatible = "marvell,mv64xxx-i2c";
115 reg = <0xd0011000 0x20>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 interrupts = <31>;
119 timeout-ms = <1000>;
120 clocks = <&coreclk 0>;
121 status = "disabled";
122 };
123
124 i2c1: i2c@d0011100 {
125 compatible = "marvell,mv64xxx-i2c";
126 reg = <0xd0011100 0x20>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 interrupts = <32>;
130 timeout-ms = <1000>;
131 clocks = <&coreclk 0>;
132 status = "disabled";
133 };
Gregory CLEMENT0db98542012-12-12 10:06:24 +0100134
135 rtc@10300 {
136 compatible = "marvell,orion-rtc";
137 reg = <0xd0010300 0x20>;
138 interrupts = <50>;
139 };
Thomas Petazzoni42bb5312012-12-21 15:49:04 +0100140
141 mvsdio@d00d4000 {
142 compatible = "marvell,orion-sdio";
143 reg = <0xd00d4000 0x200>;
144 interrupts = <54>;
145 clocks = <&gateclk 17>;
146 status = "disabled";
147 };
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300148
149 usb@d0050000 {
150 compatible = "marvell,orion-ehci";
151 reg = <0xd0050000 0x500>;
152 interrupts = <45>;
153 status = "disabled";
154 };
155
156 usb@d0051000 {
157 compatible = "marvell,orion-ehci";
158 reg = <0xd0051000 0x500>;
159 interrupts = <46>;
160 status = "disabled";
161 };
162
Ezequiel Garciad5dc0352013-02-06 10:06:21 -0300163 spi0: spi@d0010600 {
164 compatible = "marvell,orion-spi";
165 reg = <0xd0010600 0x28>;
166 #address-cells = <1>;
167 #size-cells = <0>;
168 cell-index = <0>;
169 interrupts = <30>;
170 clocks = <&coreclk 0>;
171 status = "disabled";
172 };
173
174 spi1: spi@d0010680 {
175 compatible = "marvell,orion-spi";
176 reg = <0xd0010680 0x28>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 cell-index = <1>;
180 interrupts = <92>;
181 clocks = <&coreclk 0>;
182 status = "disabled";
183 };
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200184 };
185};
186