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review.evervolv.com / android_kernel_oneplus_msm8996 / 8d82e180b51f8ecca9ae9d6a3e7f01d50ea34c20 / . / arch / arm / boot / dts / tegra30.dtsi
blob: dbf46c27256255fd35ffaf6501a314f50668af3c [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 serial4 = &uarte;
13 };
14
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]15 host1x {
16 compatible = "nvidia,tegra30-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */
19 0 67 0x04>; /* mpcore general */
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]20 clocks = <&tegra_car 28>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]21
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x54000000 0x54000000 0x04000000>;
26
27 mpe {
28 compatible = "nvidia,tegra30-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]31 clocks = <&tegra_car 60>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]32 };
33
34 vi {
35 compatible = "nvidia,tegra30-vi";
36 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]38 clocks = <&tegra_car 164>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]39 };
40
41 epp {
42 compatible = "nvidia,tegra30-epp";
43 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]45 clocks = <&tegra_car 19>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]46 };
47
48 isp {
49 compatible = "nvidia,tegra30-isp";
50 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]52 clocks = <&tegra_car 23>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]53 };
54
55 gr2d {
56 compatible = "nvidia,tegra30-gr2d";
57 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]59 clocks = <&tegra_car 21>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]60 };
61
62 gr3d {
63 compatible = "nvidia,tegra30-gr3d";
64 reg = <0x54180000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]65 clocks = <&tegra_car 24 &tegra_car 98>;
66 clock-names = "3d", "3d2";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]67 };
68
69 dc@54200000 {
70 compatible = "nvidia,tegra30-dc";
71 reg = <0x54200000 0x00040000>;
72 interrupts = <0 73 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]73 clocks = <&tegra_car 27>, <&tegra_car 179>;
74 clock-names = "disp1", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]75
76 rgb {
77 status = "disabled";
78 };
79 };
80
81 dc@54240000 {
82 compatible = "nvidia,tegra30-dc";
83 reg = <0x54240000 0x00040000>;
84 interrupts = <0 74 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]85 clocks = <&tegra_car 26>, <&tegra_car 179>;
86 clock-names = "disp2", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]87
88 rgb {
89 status = "disabled";
90 };
91 };
92
93 hdmi {
94 compatible = "nvidia,tegra30-hdmi";
95 reg = <0x54280000 0x00040000>;
96 interrupts = <0 75 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]97 clocks = <&tegra_car 51>, <&tegra_car 189>;
98 clock-names = "hdmi", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]99 status = "disabled";
100 };
101
102 tvo {
103 compatible = "nvidia,tegra30-tvo";
104 reg = <0x542c0000 0x00040000>;
105 interrupts = <0 76 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]106 clocks = <&tegra_car 169>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]107 status = "disabled";
108 };
109
110 dsi {
111 compatible = "nvidia,tegra30-dsi";
112 reg = <0x54300000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]113 clocks = <&tegra_car 48>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]114 status = "disabled";
115 };
116 };
117
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]118 timer@50004600 {
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0x50040600 0x20>;
121 interrupts = <1 13 0xf04>;
Prashant Gaikwaded3ced32013-03-01 11:32:24 -0700[diff] [blame]122 clocks = <&tegra_car 214>;
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]123 };
124
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]125 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]126 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]127 reg = <0x50041000 0x1000
128 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]129 interrupt-controller;
130 #interrupt-cells = <3>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]131 };
132
Stephen Warrenbb2c1de2013-01-14 10:09:16 -0700[diff] [blame]133 cache-controller {
134 compatible = "arm,pl310-cache";
135 reg = <0x50043000 0x1000>;
136 arm,data-latency = <6 6 2>;
137 arm,tag-latency = <5 5 2>;
138 cache-unified;
139 cache-level = <2>;
140 };
141
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]142 timer@60005000 {
143 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
144 reg = <0x60005000 0x400>;
145 interrupts = <0 0 0x04
146 0 1 0x04
147 0 41 0x04
148 0 42 0x04
149 0 121 0x04
150 0 122 0x04>;
151 };
152
Prashant Gaikwad95985662013-01-11 13:16:23 +0530[diff] [blame]153 tegra_car: clock {
154 compatible = "nvidia,tegra30-car";
155 reg = <0x60006000 0x1000>;
156 #clock-cells = <1>;
157 };
158
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]159 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]160 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
161 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]162 interrupts = <0 104 0x04
163 0 105 0x04
164 0 106 0x04
165 0 107 0x04
166 0 108 0x04
167 0 109 0x04
168 0 110 0x04
169 0 111 0x04
170 0 112 0x04
171 0 113 0x04
172 0 114 0x04
173 0 115 0x04
174 0 116 0x04
175 0 117 0x04
176 0 118 0x04
177 0 119 0x04
178 0 128 0x04
179 0 129 0x04
180 0 130 0x04
181 0 131 0x04
182 0 132 0x04
183 0 133 0x04
184 0 134 0x04
185 0 135 0x04
186 0 136 0x04
187 0 137 0x04
188 0 138 0x04
189 0 139 0x04
190 0 140 0x04
191 0 141 0x04
192 0 142 0x04
193 0 143 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]194 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]195 };
196
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]197 ahb: ahb {
198 compatible = "nvidia,tegra30-ahb";
199 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
200 };
201
202 gpio: gpio {
Laxman Dewangan35f210e2012-12-19 20:27:12 +0530[diff] [blame]203 compatible = "nvidia,tegra30-gpio";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]204 reg = <0x6000d000 0x1000>;
205 interrupts = <0 32 0x04
206 0 33 0x04
207 0 34 0x04
208 0 35 0x04
209 0 55 0x04
210 0 87 0x04
211 0 89 0x04
212 0 125 0x04>;
213 #gpio-cells = <2>;
214 gpio-controller;
215 #interrupt-cells = <2>;
216 interrupt-controller;
217 };
218
219 pinmux: pinmux {
220 compatible = "nvidia,tegra30-pinmux";
Pritesh Raithatha322337b2012-10-30 15:37:09 +0530[diff] [blame]221 reg = <0x70000868 0xd4 /* Pad control registers */
222 0x70003000 0x3e4>; /* Mux registers */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]223 };
224
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]225 /*
226 * There are two serial driver i.e. 8250 based simple serial
227 * driver and APB DMA based serial driver for higher baudrate
228 * and performace. To enable the 8250 based driver, the compatible
229 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
230 * the APB DMA based serial driver, the comptible is
231 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
232 */
233 uarta: serial@70006000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]234 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
235 reg = <0x70006000 0x40>;
236 reg-shift = <2>;
237 interrupts = <0 36 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]238 nvidia,dma-request-selector = <&apbdma 8>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]239 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]240 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]241 };
242
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]243 uartb: serial@70006040 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]244 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
245 reg = <0x70006040 0x40>;
246 reg-shift = <2>;
247 interrupts = <0 37 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]248 nvidia,dma-request-selector = <&apbdma 9>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]249 clocks = <&tegra_car 160>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]250 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]251 };
252
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]253 uartc: serial@70006200 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]254 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
255 reg = <0x70006200 0x100>;
256 reg-shift = <2>;
257 interrupts = <0 46 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]258 nvidia,dma-request-selector = <&apbdma 10>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]259 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]260 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]261 };
262
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]263 uartd: serial@70006300 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]264 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
265 reg = <0x70006300 0x100>;
266 reg-shift = <2>;
267 interrupts = <0 90 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]268 nvidia,dma-request-selector = <&apbdma 19>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]269 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]270 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]271 };
272
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]273 uarte: serial@70006400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]274 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
275 reg = <0x70006400 0x100>;
276 reg-shift = <2>;
277 interrupts = <0 91 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]278 nvidia,dma-request-selector = <&apbdma 20>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]279 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]280 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]281 };
282
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]283 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]284 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
285 reg = <0x7000a000 0x100>;
286 #pwm-cells = <2>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]287 clocks = <&tegra_car 17>;
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]288 };
289
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]290 rtc {
291 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
292 reg = <0x7000e000 0x100>;
293 interrupts = <0 2 0x04>;
294 };
295
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]296 i2c@7000c000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]297 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]298 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]299 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]300 #address-cells = <1>;
301 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]302 clocks = <&tegra_car 12>, <&tegra_car 182>;
303 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]304 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]305 };
306
307 i2c@7000c400 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]308 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]309 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]310 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]311 #address-cells = <1>;
312 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]313 clocks = <&tegra_car 54>, <&tegra_car 182>;
314 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]315 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]316 };
317
318 i2c@7000c500 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]319 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]320 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]321 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]322 #address-cells = <1>;
323 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]324 clocks = <&tegra_car 67>, <&tegra_car 182>;
325 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]326 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]327 };
328
329 i2c@7000c700 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]330 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
331 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]332 interrupts = <0 120 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]333 #address-cells = <1>;
334 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]335 clocks = <&tegra_car 103>, <&tegra_car 182>;
336 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]337 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]338 };
339
340 i2c@7000d000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]341 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]342 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]343 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]344 #address-cells = <1>;
345 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]346 clocks = <&tegra_car 47>, <&tegra_car 182>;
347 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]348 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]349 };
350
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]351 spi@7000d400 {
352 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
353 reg = <0x7000d400 0x200>;
354 interrupts = <0 59 0x04>;
355 nvidia,dma-request-selector = <&apbdma 15>;
356 #address-cells = <1>;
357 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]358 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]359 status = "disabled";
360 };
361
362 spi@7000d600 {
363 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
364 reg = <0x7000d600 0x200>;
365 interrupts = <0 82 0x04>;
366 nvidia,dma-request-selector = <&apbdma 16>;
367 #address-cells = <1>;
368 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]369 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]370 status = "disabled";
371 };
372
373 spi@7000d800 {
374 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
Laxman Dewangan57471c82013-03-22 12:35:06 -0600[diff] [blame]375 reg = <0x7000d800 0x200>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]376 interrupts = <0 83 0x04>;
377 nvidia,dma-request-selector = <&apbdma 17>;
378 #address-cells = <1>;
379 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]380 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]381 status = "disabled";
382 };
383
384 spi@7000da00 {
385 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
386 reg = <0x7000da00 0x200>;
387 interrupts = <0 93 0x04>;
388 nvidia,dma-request-selector = <&apbdma 18>;
389 #address-cells = <1>;
390 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]391 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]392 status = "disabled";
393 };
394
395 spi@7000dc00 {
396 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
397 reg = <0x7000dc00 0x200>;
398 interrupts = <0 94 0x04>;
399 nvidia,dma-request-selector = <&apbdma 27>;
400 #address-cells = <1>;
401 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]402 clocks = <&tegra_car 104>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]403 status = "disabled";
404 };
405
406 spi@7000de00 {
407 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
408 reg = <0x7000de00 0x200>;
409 interrupts = <0 79 0x04>;
410 nvidia,dma-request-selector = <&apbdma 28>;
411 #address-cells = <1>;
412 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]413 clocks = <&tegra_car 105>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]414 status = "disabled";
415 };
416
Laxman Dewangan699ed4b2013-01-11 19:03:03 +0530[diff] [blame]417 kbc {
418 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
419 reg = <0x7000e200 0x100>;
420 interrupts = <0 85 0x04>;
421 clocks = <&tegra_car 36>;
422 status = "disabled";
423 };
424
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]425 pmc {
426 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
427 reg = <0x7000e400 0x400>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]428 };
429
hdoyu@nvidia.coma9140aa2012-05-16 19:47:44 +0000[diff] [blame]430 memory-controller {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]431 compatible = "nvidia,tegra30-mc";
432 reg = <0x7000f000 0x010
433 0x7000f03c 0x1b4
434 0x7000f200 0x028
435 0x7000f284 0x17c>;
436 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]437 };
438
Hiroshi Doyu3fbf07d2013-01-29 10:30:29 +0200[diff] [blame]439 iommu {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]440 compatible = "nvidia,tegra30-smmu";
441 reg = <0x7000f010 0x02c
442 0x7000f1f0 0x010
443 0x7000f228 0x05c>;
444 nvidia,#asids = <4>; /* # of ASIDs */
445 dma-window = <0 0x40000000>; /* IOVA start & length */
446 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]447 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]448
449 ahub {
450 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]451 reg = <0x70080000 0x200
452 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]453 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]454 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]455 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
456 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
457 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
458 <&tegra_car 110>, <&tegra_car 162>;
459 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
460 "i2s3", "i2s4", "dam0", "dam1", "dam2",
461 "spdif_in";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]462 ranges;
463 #address-cells = <1>;
464 #size-cells = <1>;
465
466 tegra_i2s0: i2s@70080300 {
467 compatible = "nvidia,tegra30-i2s";
468 reg = <0x70080300 0x100>;
469 nvidia,ahub-cif-ids = <4 4>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]470 clocks = <&tegra_car 30>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]471 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]472 };
473
474 tegra_i2s1: i2s@70080400 {
475 compatible = "nvidia,tegra30-i2s";
476 reg = <0x70080400 0x100>;
477 nvidia,ahub-cif-ids = <5 5>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]478 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]479 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]480 };
481
482 tegra_i2s2: i2s@70080500 {
483 compatible = "nvidia,tegra30-i2s";
484 reg = <0x70080500 0x100>;
485 nvidia,ahub-cif-ids = <6 6>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]486 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]487 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]488 };
489
490 tegra_i2s3: i2s@70080600 {
491 compatible = "nvidia,tegra30-i2s";
492 reg = <0x70080600 0x100>;
493 nvidia,ahub-cif-ids = <7 7>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]494 clocks = <&tegra_car 101>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]495 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]496 };
497
498 tegra_i2s4: i2s@70080700 {
499 compatible = "nvidia,tegra30-i2s";
500 reg = <0x70080700 0x100>;
501 nvidia,ahub-cif-ids = <8 8>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]502 clocks = <&tegra_car 102>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]503 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]504 };
505 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]506
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]507 sdhci@78000000 {
508 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
509 reg = <0x78000000 0x200>;
510 interrupts = <0 14 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]511 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]512 status = "disabled";
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]513 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]514
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]515 sdhci@78000200 {
516 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
517 reg = <0x78000200 0x200>;
518 interrupts = <0 15 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]519 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]520 status = "disabled";
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]521 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]522
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]523 sdhci@78000400 {
524 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
525 reg = <0x78000400 0x200>;
526 interrupts = <0 19 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]527 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]528 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]529 };
530
531 sdhci@78000600 {
532 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
533 reg = <0x78000600 0x200>;
534 interrupts = <0 31 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]535 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]536 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]537 };
538
Hiroshi Doyu7d19a342013-01-11 15:11:54 +0200[diff] [blame]539 cpus {
540 #address-cells = <1>;
541 #size-cells = <0>;
542
543 cpu@0 {
544 device_type = "cpu";
545 compatible = "arm,cortex-a9";
546 reg = <0>;
547 };
548
549 cpu@1 {
550 device_type = "cpu";
551 compatible = "arm,cortex-a9";
552 reg = <1>;
553 };
554
555 cpu@2 {
556 device_type = "cpu";
557 compatible = "arm,cortex-a9";
558 reg = <2>;
559 };
560
561 cpu@3 {
562 device_type = "cpu";
563 compatible = "arm,cortex-a9";
564 reg = <3>;
565 };
566 };
567
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]568 pmu {
569 compatible = "arm,cortex-a9-pmu";
570 interrupts = <0 144 0x04
571 0 145 0x04
572 0 146 0x04
573 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]574 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]575};