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Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
Kevin Hilman8bd22942009-05-28 10:56:16 -07002 * (C) Copyright 2007
3 * Texas Instruments
4 * Karthik Dasu <karthik-dp@ti.com>
5 *
6 * (C) Copyright 2004
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25#include <linux/linkage.h>
26#include <asm/assembler.h>
Jean Pihetb4b36fd2010-12-18 16:44:42 +010027#include <plat/sram.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070028#include <mach/io.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070029
Paul Walmsley59fb6592010-12-21 15:30:55 -070030#include "cm2xxx_3xxx.h"
31#include "prm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070032#include "sdrc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060033#include "control.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070034
Jean Pihetfe360e12010-12-18 16:44:43 +010035/*
36 * Registers access definitions
37 */
38#define SDRC_SCRATCHPAD_SEM_OFFS 0xc
39#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
40 (SDRC_SCRATCHPAD_SEM_OFFS)
41#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
42 OMAP3430_PM_PREPWSTST
Abhijit Pagare37903002010-01-26 20:12:51 -070043#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +020044#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -060045#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
Jean Pihetfe360e12010-12-18 16:44:43 +010046#define SRAM_BASE_P OMAP3_SRAM_PA
47#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
48#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
49 OMAP36XX_CONTROL_MEM_RTA_CTRL)
50
51/* Move this as correct place is available */
52#define SCRATCHPAD_MEM_OFFS 0x310
53#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
54 OMAP343X_CONTROL_MEM_WKUP +\
55 SCRATCHPAD_MEM_OFFS)
Kevin Hilman8bd22942009-05-28 10:56:16 -070056#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
Tero Kristo0795a752008-10-13 17:58:50 +030057#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
58#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
59#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
60#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
61#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
62#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
63#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +020064#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
65#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
Kevin Hilman8bd22942009-05-28 10:56:16 -070066
Dave Martindd313942011-03-04 15:33:57 +000067/*
68 * This file needs be built unconditionally as ARM to interoperate correctly
69 * with non-Thumb-2-capable firmware.
70 */
71 .arm
Rajendra Nayaka89b6f02009-05-28 18:13:06 +053072
Jean Pihetd3cdfd22010-12-18 16:44:41 +010073/*
74 * API functions
75 */
Rajendra Nayaka89b6f02009-05-28 18:13:06 +053076
Jean Pihetf7dfe3d2010-12-18 16:44:45 +010077/*
78 * The "get_*restore_pointer" functions are used to provide a
79 * physical restore address where the ROM code jumps while waking
80 * up from MPU OFF/OSWR state.
81 * The restore pointer is stored into the scratchpad.
82 */
83
Kevin Hilman8bd22942009-05-28 10:56:16 -070084 .text
85/* Function call to get the restore pointer for resume from OFF */
86ENTRY(get_restore_pointer)
Jean Pihetbb1c9032010-12-18 16:49:57 +010087 stmfd sp!, {lr} @ save registers on stack
Kevin Hilman8bd22942009-05-28 10:56:16 -070088 adr r0, restore
Jean Pihetbb1c9032010-12-18 16:49:57 +010089 ldmfd sp!, {pc} @ restore regs and return
Dave Martindd313942011-03-04 15:33:57 +000090ENDPROC(get_restore_pointer)
91 .align
Kevin Hilman8bd22942009-05-28 10:56:16 -070092ENTRY(get_restore_pointer_sz)
Jean Pihetbb1c9032010-12-18 16:49:57 +010093 .word . - get_restore_pointer
Jean Pihet1e81bc02010-12-18 16:44:44 +010094
Nishanth Menon458e9992010-12-20 14:05:06 -060095 .text
96/* Function call to get the restore pointer for 3630 resume from OFF */
97ENTRY(get_omap3630_restore_pointer)
Jean Pihetbb1c9032010-12-18 16:49:57 +010098 stmfd sp!, {lr} @ save registers on stack
Nishanth Menon458e9992010-12-20 14:05:06 -060099 adr r0, restore_3630
Jean Pihetbb1c9032010-12-18 16:49:57 +0100100 ldmfd sp!, {pc} @ restore regs and return
Dave Martindd313942011-03-04 15:33:57 +0000101ENDPROC(get_omap3630_restore_pointer)
102 .align
Nishanth Menon458e9992010-12-20 14:05:06 -0600103ENTRY(get_omap3630_restore_pointer_sz)
Jean Pihetbb1c9032010-12-18 16:49:57 +0100104 .word . - get_omap3630_restore_pointer
Tero Kristo0795a752008-10-13 17:58:50 +0300105
106 .text
Jean Pihet1e81bc02010-12-18 16:44:44 +0100107/* Function call to get the restore pointer for ES3 to resume from OFF */
108ENTRY(get_es3_restore_pointer)
109 stmfd sp!, {lr} @ save registers on stack
110 adr r0, restore_es3
111 ldmfd sp!, {pc} @ restore regs and return
Dave Martindd313942011-03-04 15:33:57 +0000112ENDPROC(get_es3_restore_pointer)
113 .align
Jean Pihet1e81bc02010-12-18 16:44:44 +0100114ENTRY(get_es3_restore_pointer_sz)
115 .word . - get_es3_restore_pointer
116
117 .text
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600118/*
119 * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
Jean Pihet1e81bc02010-12-18 16:44:44 +0100120 * This function sets up a flag that will allow for this toggling to take
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100121 * place on 3630. Hopefully some version in the future may not need this.
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600122 */
123ENTRY(enable_omap3630_toggle_l2_on_restore)
Jean Pihetbb1c9032010-12-18 16:49:57 +0100124 stmfd sp!, {lr} @ save registers on stack
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600125 /* Setup so that we will disable and enable l2 */
126 mov r1, #0x1
Dave Martindd313942011-03-04 15:33:57 +0000127 adrl r2, l2dis_3630 @ may be too distant for plain adr
128 str r1, [r2]
Jean Pihetbb1c9032010-12-18 16:49:57 +0100129 ldmfd sp!, {pc} @ restore regs and return
Dave Martindd313942011-03-04 15:33:57 +0000130ENDPROC(enable_omap3630_toggle_l2_on_restore)
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600131
Jean Pihetbb1c9032010-12-18 16:49:57 +0100132 .text
Tero Kristo27d59a42008-10-13 13:15:00 +0300133/* Function to call rom code to save secure ram context */
134ENTRY(save_secure_ram_context)
135 stmfd sp!, {r1-r12, lr} @ save registers on stack
Tero Kristo27d59a42008-10-13 13:15:00 +0300136 adr r3, api_params @ r3 points to parameters
137 str r0, [r3,#0x4] @ r0 has sdram address
138 ldr r12, high_mask
139 and r3, r3, r12
140 ldr r12, sram_phy_addr_mask
141 orr r3, r3, r12
142 mov r0, #25 @ set service ID for PPA
143 mov r12, r0 @ copy secure service ID in r12
144 mov r1, #0 @ set task id for ROM code in r1
Kalle Jokiniemiba50ea72009-03-26 15:59:00 +0200145 mov r2, #4 @ set some flags in r2, r6
Tero Kristo27d59a42008-10-13 13:15:00 +0300146 mov r6, #0xff
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530147 dsb @ data write barrier
148 dmb @ data memory barrier
Dave Martin76d50012011-03-04 15:33:55 +0000149 smc #1 @ call SMI monitor (smi #1)
Tero Kristo27d59a42008-10-13 13:15:00 +0300150 nop
151 nop
152 nop
153 nop
154 ldmfd sp!, {r1-r12, pc}
Dave Martindd313942011-03-04 15:33:57 +0000155 .align
Tero Kristo27d59a42008-10-13 13:15:00 +0300156sram_phy_addr_mask:
157 .word SRAM_BASE_P
158high_mask:
159 .word 0xffff
160api_params:
161 .word 0x4, 0x0, 0x0, 0x1, 0x1
Dave Martindd313942011-03-04 15:33:57 +0000162ENDPROC(save_secure_ram_context)
Tero Kristo27d59a42008-10-13 13:15:00 +0300163ENTRY(save_secure_ram_context_sz)
164 .word . - save_secure_ram_context
165
Kevin Hilman8bd22942009-05-28 10:56:16 -0700166/*
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100167 * ======================
168 * == Idle entry point ==
169 * ======================
170 */
171
172/*
Kevin Hilman8bd22942009-05-28 10:56:16 -0700173 * Forces OMAP into idle state
174 *
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100175 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
176 * and executes the WFI instruction. Calling WFI effectively changes the
177 * power domains states to the desired target power states.
Kevin Hilman8bd22942009-05-28 10:56:16 -0700178 *
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100179 *
180 * Notes:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100181 * - this code gets copied to internal SRAM at boot and after wake-up
182 * from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100183 * - when the OMAP wakes up it continues at different execution points
184 * depending on the low power mode (non-OFF vs OFF modes),
185 * cf. 'Resume path for xxx mode' comments.
Kevin Hilman8bd22942009-05-28 10:56:16 -0700186 */
187ENTRY(omap34xx_cpu_suspend)
Jean Pihetbb1c9032010-12-18 16:49:57 +0100188 stmfd sp!, {r0-r12, lr} @ save registers on stack
Jean Pihetd3cdfd22010-12-18 16:44:41 +0100189
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100190 /*
Santosh Shilimkarc9749a32011-01-23 19:33:53 +0530191 * r0 contains CPU context save/restore pointer in sdram
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100192 * r1 contains information about saving context:
193 * 0 - No context lost
194 * 1 - Only L1 and logic lost
Santosh Shilimkarc9749a32011-01-23 19:33:53 +0530195 * 2 - Only L2 lost (Even L1 is retained we clean it along with L2)
196 * 3 - Both L1 and L2 lost and logic lost
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100197 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700198
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100199 /* Directly jump to WFI is the context save is not required */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700200 cmp r1, #0x0
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100201 beq omap3_do_wfi
202
203 /* Otherwise fall through to the save context code */
204save_context_wfi:
205 mov r8, r0 @ Store SDRAM address in r8
206 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
207 mov r4, #0x1 @ Number of parameters for restore call
208 stmia r8!, {r4-r5} @ Push parameters for restore call
209 mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
210 stmia r8!, {r4-r5} @ Push parameters for restore call
211
212 /* Check what that target sleep state is from r1 */
213 cmp r1, #0x2 @ Only L2 lost, no need to save context
214 beq clean_caches
215
216l1_logic_lost:
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530217 mov r4, sp @ Store sp
218 mrs r5, spsr @ Store spsr
219 mov r6, lr @ Store lr
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100220 stmia r8!, {r4-r6}
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100221
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530222 mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
223 mrc p15, 0, r5, c2, c0, 0 @ TTBR0
224 mrc p15, 0, r6, c2, c0, 1 @ TTBR1
225 mrc p15, 0, r7, c2, c0, 2 @ TTBCR
226 stmia r8!, {r4-r7}
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100227
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530228 mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
229 mrc p15, 0, r5, c10, c2, 0 @ PRRR
230 mrc p15, 0, r6, c10, c2, 1 @ NMRR
231 stmia r8!,{r4-r6}
232
233 mrc p15, 0, r4, c13, c0, 1 @ Context ID
234 mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
235 mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
236 mrs r7, cpsr @ Store current cpsr
237 stmia r8!, {r4-r7}
238
239 mrc p15, 0, r4, c1, c0, 0 @ save control register
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100240 stmia r8!, {r4}
241
242clean_caches:
243 /*
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100244 * jump out to kernel flush routine
245 * - reuse that code is better
246 * - it executes in a cached space so is faster than refetch per-block
247 * - should be faster and will change with kernel
248 * - 'might' have to copy address, load and jump to it
Santosh Shilimkar90625112011-01-23 22:51:09 +0530249 * Flush all data from the L1 data cache before disabling
250 * SCTLR.C bit.
251 */
252 ldr r1, kernel_flush
253 mov lr, pc
254 bx r1
255
256 /*
257 * Clear the SCTLR.C bit to prevent further data cache
258 * allocation. Clearing SCTLR.C would make all the data accesses
259 * strongly ordered and would not hit the cache.
260 */
261 mrc p15, 0, r0, c1, c0, 0
262 bic r0, r0, #(1 << 2) @ Disable the C bit
263 mcr p15, 0, r0, c1, c0, 0
264 isb
265
266 /*
267 * Invalidate L1 data cache. Even though only invalidate is
268 * necessary exported flush API is used here. Doing clean
269 * on already clean cache would be almost NOP.
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100270 */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100271 ldr r1, kernel_flush
Dave Martindd313942011-03-04 15:33:57 +0000272 blx r1
273 /*
274 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
275 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
276 * This sequence switches back to ARM. Note that .align may insert a
277 * nop: bx pc needs to be word-aligned in order to work.
278 */
279 THUMB( .thumb )
280 THUMB( .align )
281 THUMB( bx pc )
282 THUMB( nop )
283 .arm
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100284
285omap3_do_wfi:
286 ldr r4, sdrc_power @ read the SDRC_POWER register
287 ldr r5, [r4] @ read the contents of SDRC_POWER
288 orr r5, r5, #0x40 @ enable self refresh on idle req
289 str r5, [r4] @ write back to SDRC_POWER register
290
Kevin Hilman8bd22942009-05-28 10:56:16 -0700291 /* Data memory barrier and Data sync barrier */
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530292 dsb
293 dmb
Kevin Hilman8bd22942009-05-28 10:56:16 -0700294
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100295/*
296 * ===================================
297 * == WFI instruction => Enter idle ==
298 * ===================================
299 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700300 wfi @ wait for interrupt
301
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100302/*
303 * ===================================
304 * == Resume path for non-OFF modes ==
305 * ===================================
306 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700307 nop
308 nop
309 nop
310 nop
311 nop
312 nop
313 nop
314 nop
315 nop
316 nop
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +0200317 bl wait_sdrc_ok
Kevin Hilman8bd22942009-05-28 10:56:16 -0700318
Santosh Shilimkar90625112011-01-23 22:51:09 +0530319 mrc p15, 0, r0, c1, c0, 0
320 tst r0, #(1 << 2) @ Check C bit enabled?
321 orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
322 mcreq p15, 0, r0, c1, c0, 0
323 isb
324
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100325/*
326 * ===================================
327 * == Exit point from non-OFF modes ==
328 * ===================================
329 */
330 ldmfd sp!, {r0-r12, pc} @ restore regs and return
331
332
333/*
334 * ==============================
335 * == Resume path for OFF mode ==
336 * ==============================
337 */
338
339/*
340 * The restore_* functions are called by the ROM code
341 * when back from WFI in OFF mode.
342 * Cf. the get_*restore_pointer functions.
343 *
344 * restore_es3: applies to 34xx >= ES3.0
345 * restore_3630: applies to 36xx
346 * restore: common code for 3xxx
347 */
Tero Kristo0795a752008-10-13 17:58:50 +0300348restore_es3:
Tero Kristo0795a752008-10-13 17:58:50 +0300349 ldr r5, pm_prepwstst_core_p
350 ldr r4, [r5]
351 and r4, r4, #0x3
352 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
353 bne restore
354 adr r0, es3_sdrc_fix
355 ldr r1, sram_base
356 ldr r2, es3_sdrc_fix_sz
357 mov r2, r2, ror #2
358copy_to_sram:
359 ldmia r0!, {r3} @ val = *src
360 stmia r1!, {r3} @ *dst = val
361 subs r2, r2, #0x1 @ num_words--
362 bne copy_to_sram
363 ldr r1, sram_base
364 blx r1
Nishanth Menon458e9992010-12-20 14:05:06 -0600365 b restore
366
367restore_3630:
Nishanth Menon458e9992010-12-20 14:05:06 -0600368 ldr r1, pm_prepwstst_core_p
369 ldr r2, [r1]
370 and r2, r2, #0x3
371 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
372 bne restore
373 /* Disable RTA before giving control */
374 ldr r1, control_mem_rta
375 mov r2, #OMAP36XX_RTA_DISABLE
376 str r2, [r1]
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100377
378 /* Fall through to common code for the remaining logic */
379
Kevin Hilman8bd22942009-05-28 10:56:16 -0700380restore:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100381 /*
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100382 * Check what was the reason for mpu reset and store the reason in r9:
383 * 0 - No context lost
Jean Pihetbb1c9032010-12-18 16:49:57 +0100384 * 1 - Only L1 and logic lost
385 * 2 - Only L2 lost - In this case, we wont be here
386 * 3 - Both L1 and L2 lost
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100387 */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100388 ldr r1, pm_pwstctrl_mpu
Kevin Hilman8bd22942009-05-28 10:56:16 -0700389 ldr r2, [r1]
Jean Pihetbb1c9032010-12-18 16:49:57 +0100390 and r2, r2, #0x3
391 cmp r2, #0x0 @ Check if target power state was OFF or RET
392 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
Kevin Hilman8bd22942009-05-28 10:56:16 -0700393 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
394 bne logic_l1_restore
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600395
396 ldr r0, l2dis_3630
397 cmp r0, #0x1 @ should we disable L2 on 3630?
398 bne skipl2dis
399 mrc p15, 0, r0, c1, c0, 1
400 bic r0, r0, #2 @ disable L2 cache
401 mcr p15, 0, r0, c1, c0, 1
402skipl2dis:
Tero Kristo27d59a42008-10-13 13:15:00 +0300403 ldr r0, control_stat
404 ldr r1, [r0]
405 and r1, #0x700
406 cmp r1, #0x300
407 beq l2_inv_gp
Jean Pihetbb1c9032010-12-18 16:49:57 +0100408 mov r0, #40 @ set service ID for PPA
409 mov r12, r0 @ copy secure Service ID in r12
410 mov r1, #0 @ set task id for ROM code in r1
411 mov r2, #4 @ set some flags in r2, r6
Tero Kristo27d59a42008-10-13 13:15:00 +0300412 mov r6, #0xff
413 adr r3, l2_inv_api_params @ r3 points to dummy parameters
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530414 dsb @ data write barrier
415 dmb @ data memory barrier
Dave Martin76d50012011-03-04 15:33:55 +0000416 smc #1 @ call SMI monitor (smi #1)
Tero Kristo27d59a42008-10-13 13:15:00 +0300417 /* Write to Aux control register to set some bits */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100418 mov r0, #42 @ set service ID for PPA
419 mov r12, r0 @ copy secure Service ID in r12
420 mov r1, #0 @ set task id for ROM code in r1
421 mov r2, #4 @ set some flags in r2, r6
Tero Kristo27d59a42008-10-13 13:15:00 +0300422 mov r6, #0xff
Tero Kristoa087cad2009-11-12 12:07:20 +0200423 ldr r4, scratchpad_base
Jean Pihetbb1c9032010-12-18 16:49:57 +0100424 ldr r3, [r4, #0xBC] @ r3 points to parameters
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530425 dsb @ data write barrier
426 dmb @ data memory barrier
Dave Martin76d50012011-03-04 15:33:55 +0000427 smc #1 @ call SMI monitor (smi #1)
Tero Kristo27d59a42008-10-13 13:15:00 +0300428
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200429#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
430 /* Restore L2 aux control register */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100431 @ set service ID for PPA
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200432 mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
Jean Pihetbb1c9032010-12-18 16:49:57 +0100433 mov r12, r0 @ copy service ID in r12
434 mov r1, #0 @ set task ID for ROM code in r1
435 mov r2, #4 @ set some flags in r2, r6
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200436 mov r6, #0xff
437 ldr r4, scratchpad_base
438 ldr r3, [r4, #0xBC]
Jean Pihetbb1c9032010-12-18 16:49:57 +0100439 adds r3, r3, #8 @ r3 points to parameters
Santosh Shilimkar4444d712011-01-23 19:00:34 +0530440 dsb @ data write barrier
441 dmb @ data memory barrier
Dave Martin76d50012011-03-04 15:33:55 +0000442 smc #1 @ call SMI monitor (smi #1)
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200443#endif
Tero Kristo27d59a42008-10-13 13:15:00 +0300444 b logic_l1_restore
Jean Pihetbb1c9032010-12-18 16:49:57 +0100445
Dave Martindd313942011-03-04 15:33:57 +0000446 .align
Tero Kristo27d59a42008-10-13 13:15:00 +0300447l2_inv_api_params:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100448 .word 0x1, 0x00
Tero Kristo27d59a42008-10-13 13:15:00 +0300449l2_inv_gp:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700450 /* Execute smi to invalidate L2 cache */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100451 mov r12, #0x1 @ set up to invalidate L2
Dave Martin76d50012011-03-04 15:33:55 +0000452 smc #0 @ Call SMI monitor (smieq)
Tero Kristo27d59a42008-10-13 13:15:00 +0300453 /* Write to Aux control register to set some bits */
Tero Kristoa087cad2009-11-12 12:07:20 +0200454 ldr r4, scratchpad_base
455 ldr r3, [r4,#0xBC]
456 ldr r0, [r3,#4]
Tero Kristo27d59a42008-10-13 13:15:00 +0300457 mov r12, #0x3
Dave Martin76d50012011-03-04 15:33:55 +0000458 smc #0 @ Call SMI monitor (smieq)
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200459 ldr r4, scratchpad_base
460 ldr r3, [r4,#0xBC]
461 ldr r0, [r3,#12]
462 mov r12, #0x2
Dave Martin76d50012011-03-04 15:33:55 +0000463 smc #0 @ Call SMI monitor (smieq)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700464logic_l1_restore:
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600465 ldr r1, l2dis_3630
Jean Pihetbb1c9032010-12-18 16:49:57 +0100466 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600467 bne skipl2reen
468 mrc p15, 0, r1, c1, c0, 1
Jean Pihetbb1c9032010-12-18 16:49:57 +0100469 orr r1, r1, #2 @ re-enable L2 cache
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600470 mcr p15, 0, r1, c1, c0, 1
471skipl2reen:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700472 mov r1, #0
Jean Pihetbb1c9032010-12-18 16:49:57 +0100473 /*
474 * Invalidate all instruction caches to PoU
475 * and flush branch target cache
476 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700477 mcr p15, 0, r1, c7, c5, 0
478
479 ldr r4, scratchpad_base
480 ldr r3, [r4,#0xBC]
Tero Kristo79dcfdd2009-11-12 12:07:22 +0200481 adds r3, r3, #16
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530482
Kevin Hilman8bd22942009-05-28 10:56:16 -0700483 ldmia r3!, {r4-r6}
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530484 mov sp, r4 @ Restore sp
485 msr spsr_cxsf, r5 @ Restore spsr
486 mov lr, r6 @ Restore lr
Kevin Hilman8bd22942009-05-28 10:56:16 -0700487
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530488 ldmia r3!, {r4-r7}
489 mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
490 mcr p15, 0, r5, c2, c0, 0 @ TTBR0
491 mcr p15, 0, r6, c2, c0, 1 @ TTBR1
492 mcr p15, 0, r7, c2, c0, 2 @ TTBCR
Kevin Hilman8bd22942009-05-28 10:56:16 -0700493
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530494 ldmia r3!,{r4-r6}
495 mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
496 mcr p15, 0, r5, c10, c2, 0 @ PRRR
497 mcr p15, 0, r6, c10, c2, 1 @ NMRR
Kevin Hilman8bd22942009-05-28 10:56:16 -0700498
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530499
Jean Pihetbb1c9032010-12-18 16:49:57 +0100500 ldmia r3!,{r4-r7}
Santosh Shilimkar46f557c2011-01-23 21:37:03 +0530501 mcr p15, 0, r4, c13, c0, 1 @ Context ID
502 mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
503 mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
504 msr cpsr, r7 @ store cpsr
Kevin Hilman8bd22942009-05-28 10:56:16 -0700505
506 /* Enabling MMU here */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100507 mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
508 /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700509 and r7, #0x7
510 cmp r7, #0x0
511 beq usettbr0
512ttbr_error:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100513 /*
514 * More work needs to be done to support N[0:2] value other than 0
515 * So looping here so that the error can be detected
516 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700517 b ttbr_error
518usettbr0:
519 mrc p15, 0, r2, c2, c0, 0
520 ldr r5, ttbrbit_mask
521 and r2, r5
522 mov r4, pc
523 ldr r5, table_index_mask
Jean Pihetbb1c9032010-12-18 16:49:57 +0100524 and r4, r5 @ r4 = 31 to 20 bits of pc
Kevin Hilman8bd22942009-05-28 10:56:16 -0700525 /* Extract the value to be written to table entry */
526 ldr r1, table_entry
Jean Pihetbb1c9032010-12-18 16:49:57 +0100527 /* r1 has the value to be written to table entry*/
528 add r1, r1, r4
Kevin Hilman8bd22942009-05-28 10:56:16 -0700529 /* Getting the address of table entry to modify */
530 lsr r4, #18
Jean Pihetbb1c9032010-12-18 16:49:57 +0100531 /* r2 has the location which needs to be modified */
532 add r2, r4
Kevin Hilman8bd22942009-05-28 10:56:16 -0700533 /* Storing previous entry of location being modified */
534 ldr r5, scratchpad_base
535 ldr r4, [r2]
536 str r4, [r5, #0xC0]
537 /* Modify the table entry */
538 str r1, [r2]
Jean Pihetbb1c9032010-12-18 16:49:57 +0100539 /*
540 * Storing address of entry being modified
541 * - will be restored after enabling MMU
542 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700543 ldr r5, scratchpad_base
544 str r2, [r5, #0xC4]
545
546 mov r0, #0
547 mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
548 mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
549 mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
550 mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
Jean Pihetbb1c9032010-12-18 16:49:57 +0100551 /*
552 * Restore control register. This enables the MMU.
553 * The caches and prediction are not enabled here, they
554 * will be enabled after restoring the MMU table entry.
555 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700556 ldmia r3!, {r4}
557 /* Store previous value of control register in scratchpad */
558 str r4, [r5, #0xC8]
559 ldr r2, cache_pred_disable_mask
560 and r4, r2
561 mcr p15, 0, r4, c1, c0, 0
Santosh Shilimkar8409d572011-01-23 16:04:39 +0530562 dsb
563 isb
564 ldr r0, =restoremmu_on
565 bx r0
Kevin Hilman8bd22942009-05-28 10:56:16 -0700566
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100567/*
568 * ==============================
569 * == Exit point from OFF mode ==
570 * ==============================
571 */
Santosh Shilimkar8409d572011-01-23 16:04:39 +0530572restoremmu_on:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100573 ldmfd sp!, {r0-r12, pc} @ restore regs and return
Kevin Hilman8bd22942009-05-28 10:56:16 -0700574
Jean Pihet1e81bc02010-12-18 16:44:44 +0100575
576/*
577 * Internal functions
578 */
579
Jean Pihet83521292010-12-18 16:44:46 +0100580/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
Jean Pihet1e81bc02010-12-18 16:44:44 +0100581 .text
Dave Martindd313942011-03-04 15:33:57 +0000582 .align 3
Jean Pihet1e81bc02010-12-18 16:44:44 +0100583ENTRY(es3_sdrc_fix)
584 ldr r4, sdrc_syscfg @ get config addr
585 ldr r5, [r4] @ get value
586 tst r5, #0x100 @ is part access blocked
587 it eq
588 biceq r5, r5, #0x100 @ clear bit if set
589 str r5, [r4] @ write back change
590 ldr r4, sdrc_mr_0 @ get config addr
591 ldr r5, [r4] @ get value
592 str r5, [r4] @ write back change
593 ldr r4, sdrc_emr2_0 @ get config addr
594 ldr r5, [r4] @ get value
595 str r5, [r4] @ write back change
596 ldr r4, sdrc_manual_0 @ get config addr
597 mov r5, #0x2 @ autorefresh command
598 str r5, [r4] @ kick off refreshes
599 ldr r4, sdrc_mr_1 @ get config addr
600 ldr r5, [r4] @ get value
601 str r5, [r4] @ write back change
602 ldr r4, sdrc_emr2_1 @ get config addr
603 ldr r5, [r4] @ get value
604 str r5, [r4] @ write back change
605 ldr r4, sdrc_manual_1 @ get config addr
606 mov r5, #0x2 @ autorefresh command
607 str r5, [r4] @ kick off refreshes
608 bx lr
609
Dave Martindd313942011-03-04 15:33:57 +0000610 .align
Jean Pihet1e81bc02010-12-18 16:44:44 +0100611sdrc_syscfg:
612 .word SDRC_SYSCONFIG_P
613sdrc_mr_0:
614 .word SDRC_MR_0_P
615sdrc_emr2_0:
616 .word SDRC_EMR2_0_P
617sdrc_manual_0:
618 .word SDRC_MANUAL_0_P
619sdrc_mr_1:
620 .word SDRC_MR_1_P
621sdrc_emr2_1:
622 .word SDRC_EMR2_1_P
623sdrc_manual_1:
624 .word SDRC_MANUAL_1_P
Dave Martindd313942011-03-04 15:33:57 +0000625ENDPROC(es3_sdrc_fix)
Jean Pihet1e81bc02010-12-18 16:44:44 +0100626ENTRY(es3_sdrc_fix_sz)
627 .word . - es3_sdrc_fix
628
Jean Pihet83521292010-12-18 16:44:46 +0100629/*
630 * This function implements the erratum ID i581 WA:
631 * SDRC state restore before accessing the SDRAM
632 *
633 * Only used at return from non-OFF mode. For OFF
634 * mode the ROM code configures the SDRC and
635 * the DPLL before calling the restore code directly
636 * from DDR.
637 */
638
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +0200639/* Make sure SDRC accesses are ok */
640wait_sdrc_ok:
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600641
Jean Pihetbb1c9032010-12-18 16:49:57 +0100642/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600643 ldr r4, cm_idlest_ckgen
644wait_dpll3_lock:
645 ldr r5, [r4]
646 tst r5, #1
647 beq wait_dpll3_lock
648
Jean Pihetbb1c9032010-12-18 16:49:57 +0100649 ldr r4, cm_idlest1_core
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600650wait_sdrc_ready:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100651 ldr r5, [r4]
652 tst r5, #0x2
653 bne wait_sdrc_ready
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600654 /* allow DLL powerdown upon hw idle req */
Jean Pihetbb1c9032010-12-18 16:49:57 +0100655 ldr r4, sdrc_power
656 ldr r5, [r4]
657 bic r5, r5, #0x40
658 str r5, [r4]
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600659
Dave Martindd313942011-03-04 15:33:57 +0000660/*
661 * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
662 * base instead.
663 * Be careful not to clobber r7 when maintaing this code.
664 */
665
Jean Pihetbb1c9032010-12-18 16:49:57 +0100666is_dll_in_lock_mode:
667 /* Is dll in lock mode? */
668 ldr r4, sdrc_dlla_ctrl
669 ldr r5, [r4]
670 tst r5, #0x4
671 bxne lr @ Return if locked
672 /* wait till dll locks */
Dave Martindd313942011-03-04 15:33:57 +0000673 adr r7, kick_counter
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600674wait_dll_lock_timed:
675 ldr r4, wait_dll_lock_counter
676 add r4, r4, #1
Dave Martindd313942011-03-04 15:33:57 +0000677 str r4, [r7, #wait_dll_lock_counter - kick_counter]
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600678 ldr r4, sdrc_dlla_status
Jean Pihetbb1c9032010-12-18 16:49:57 +0100679 /* Wait 20uS for lock */
680 mov r6, #8
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600681wait_dll_lock:
682 subs r6, r6, #0x1
683 beq kick_dll
Jean Pihetbb1c9032010-12-18 16:49:57 +0100684 ldr r5, [r4]
685 and r5, r5, #0x4
686 cmp r5, #0x4
687 bne wait_dll_lock
688 bx lr @ Return when locked
Kevin Hilman8bd22942009-05-28 10:56:16 -0700689
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600690 /* disable/reenable DLL if not locked */
691kick_dll:
692 ldr r4, sdrc_dlla_ctrl
693 ldr r5, [r4]
694 mov r6, r5
Jean Pihetbb1c9032010-12-18 16:49:57 +0100695 bic r6, #(1<<3) @ disable dll
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600696 str r6, [r4]
697 dsb
Jean Pihetbb1c9032010-12-18 16:49:57 +0100698 orr r6, r6, #(1<<3) @ enable dll
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600699 str r6, [r4]
700 dsb
701 ldr r4, kick_counter
702 add r4, r4, #1
Dave Martindd313942011-03-04 15:33:57 +0000703 str r4, [r7] @ kick_counter
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600704 b wait_dll_lock_timed
705
Dave Martindd313942011-03-04 15:33:57 +0000706 .align
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +0200707cm_idlest1_core:
708 .word CM_IDLEST1_CORE_V
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600709cm_idlest_ckgen:
710 .word CM_IDLEST_CKGEN_V
Peter 'p2' De Schrijver89139dc2009-01-16 18:53:48 +0200711sdrc_dlla_status:
712 .word SDRC_DLLA_STATUS_V
713sdrc_dlla_ctrl:
714 .word SDRC_DLLA_CTRL_V
Tero Kristo0795a752008-10-13 17:58:50 +0300715pm_prepwstst_core_p:
716 .word PM_PREPWSTST_CORE_P
Kevin Hilman8bd22942009-05-28 10:56:16 -0700717pm_pwstctrl_mpu:
718 .word PM_PWSTCTRL_MPU_P
719scratchpad_base:
720 .word SCRATCHPAD_BASE_P
Tero Kristo0795a752008-10-13 17:58:50 +0300721sram_base:
722 .word SRAM_BASE_P + 0x8000
Kevin Hilman8bd22942009-05-28 10:56:16 -0700723sdrc_power:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100724 .word SDRC_POWER_V
Kevin Hilman8bd22942009-05-28 10:56:16 -0700725ttbrbit_mask:
726 .word 0xFFFFC000
727table_index_mask:
728 .word 0xFFF00000
729table_entry:
730 .word 0x00000C02
731cache_pred_disable_mask:
732 .word 0xFFFFE7FB
Tero Kristo27d59a42008-10-13 13:15:00 +0300733control_stat:
734 .word CONTROL_STAT
Nishanth Menon458e9992010-12-20 14:05:06 -0600735control_mem_rta:
736 .word CONTROL_MEM_RTA_CTRL
Richard Woodruff0bd40532010-12-20 14:05:03 -0600737kernel_flush:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100738 .word v7_flush_dcache_all
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600739l2dis_3630:
Jean Pihetbb1c9032010-12-18 16:49:57 +0100740 .word 0
Peter 'p2' De Schrijver9d93b8a22010-12-20 14:05:04 -0600741 /*
742 * When exporting to userspace while the counters are in SRAM,
743 * these 2 words need to be at the end to facilitate retrival!
744 */
745kick_counter:
746 .word 0
747wait_dll_lock_counter:
748 .word 0
Dave Martindd313942011-03-04 15:33:57 +0000749ENDPROC(omap34xx_cpu_suspend)
Jean Pihetf7dfe3d2010-12-18 16:44:45 +0100750
Kevin Hilman8bd22942009-05-28 10:56:16 -0700751ENTRY(omap34xx_cpu_suspend_sz)
752 .word . - omap34xx_cpu_suspend