blob: f6849c8b6a90996a4f407dbc02c6e1967f63f29d [file] [log] [blame]
Michael Henneriche31166f2012-05-29 12:41:20 +02001/*
2 * ADF4350/ADF4351 SPI Wideband Synthesizer driver
3 *
Michael Hennerich9404fa12013-06-03 14:30:00 +01004 * Copyright 2012-2013 Analog Devices Inc.
Michael Henneriche31166f2012-05-29 12:41:20 +02005 *
6 * Licensed under the GPL-2.
7 */
8
9#include <linux/device.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sysfs.h>
13#include <linux/spi/spi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/gcd.h>
18#include <linux/gpio.h>
19#include <asm/div64.h>
Michael Hennerich9404fa12013-06-03 14:30:00 +010020#include <linux/clk.h>
Michael Henneriche31166f2012-05-29 12:41:20 +020021
22#include <linux/iio/iio.h>
23#include <linux/iio/sysfs.h>
24#include <linux/iio/frequency/adf4350.h>
25
26enum {
27 ADF4350_FREQ,
28 ADF4350_FREQ_REFIN,
29 ADF4350_FREQ_RESOLUTION,
30 ADF4350_PWRDOWN,
31};
32
33struct adf4350_state {
34 struct spi_device *spi;
35 struct regulator *reg;
36 struct adf4350_platform_data *pdata;
Michael Hennerich9404fa12013-06-03 14:30:00 +010037 struct clk *clk;
Michael Henneriche31166f2012-05-29 12:41:20 +020038 unsigned long clkin;
39 unsigned long chspc; /* Channel Spacing */
40 unsigned long fpfd; /* Phase Frequency Detector */
41 unsigned long min_out_freq;
42 unsigned r0_fract;
43 unsigned r0_int;
44 unsigned r1_mod;
45 unsigned r4_rf_div_sel;
46 unsigned long regs[6];
47 unsigned long regs_hw[6];
Michael Hennerich9404fa12013-06-03 14:30:00 +010048 unsigned long long freq_req;
Michael Henneriche31166f2012-05-29 12:41:20 +020049 /*
50 * DMA (thus cache coherency maintenance) requires the
51 * transfer buffers to live in their own cache lines.
52 */
53 __be32 val ____cacheline_aligned;
54};
55
56static struct adf4350_platform_data default_pdata = {
Michael Henneriche31166f2012-05-29 12:41:20 +020057 .channel_spacing = 10000,
Dan Carpentere86ee142012-06-08 09:55:37 +030058 .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
Michael Henneriche31166f2012-05-29 12:41:20 +020059 ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
60 .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
61 .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
62 ADF4350_REG4_MUTE_TILL_LOCK_EN,
63 .gpio_lock_detect = -1,
64};
65
66static int adf4350_sync_config(struct adf4350_state *st)
67{
68 int ret, i, doublebuf = 0;
69
70 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
71 if ((st->regs_hw[i] != st->regs[i]) ||
72 ((i == ADF4350_REG0) && doublebuf)) {
73
74 switch (i) {
75 case ADF4350_REG1:
76 case ADF4350_REG4:
77 doublebuf = 1;
78 break;
79 }
80
81 st->val = cpu_to_be32(st->regs[i] | i);
82 ret = spi_write(st->spi, &st->val, 4);
83 if (ret < 0)
84 return ret;
85 st->regs_hw[i] = st->regs[i];
86 dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
87 i, (u32)st->regs[i] | i);
88 }
89 }
90 return 0;
91}
92
93static int adf4350_reg_access(struct iio_dev *indio_dev,
94 unsigned reg, unsigned writeval,
95 unsigned *readval)
96{
97 struct adf4350_state *st = iio_priv(indio_dev);
98 int ret;
99
100 if (reg > ADF4350_REG5)
101 return -EINVAL;
102
103 mutex_lock(&indio_dev->mlock);
104 if (readval == NULL) {
105 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
106 ret = adf4350_sync_config(st);
107 } else {
108 *readval = st->regs_hw[reg];
109 ret = 0;
110 }
111 mutex_unlock(&indio_dev->mlock);
112
113 return ret;
114}
115
116static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
117{
118 struct adf4350_platform_data *pdata = st->pdata;
119
120 do {
121 r_cnt++;
122 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
123 (r_cnt * (pdata->ref_div2_en ? 2 : 1));
124 } while (st->fpfd > ADF4350_MAX_FREQ_PFD);
125
126 return r_cnt;
127}
128
129static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
130{
131 struct adf4350_platform_data *pdata = st->pdata;
132 u64 tmp;
Michael Hennerich8857df32012-07-20 09:31:00 +0100133 u32 div_gcd, prescaler, chspc;
Michael Henneriche31166f2012-05-29 12:41:20 +0200134 u16 mdiv, r_cnt = 0;
135 u8 band_sel_div;
136
137 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
138 return -EINVAL;
139
140 if (freq > ADF4350_MAX_FREQ_45_PRESC) {
141 prescaler = ADF4350_REG1_PRESCALER;
142 mdiv = 75;
143 } else {
144 prescaler = 0;
145 mdiv = 23;
146 }
147
148 st->r4_rf_div_sel = 0;
149
150 while (freq < ADF4350_MIN_VCO_FREQ) {
151 freq <<= 1;
152 st->r4_rf_div_sel++;
153 }
154
155 /*
156 * Allow a predefined reference division factor
157 * if not set, compute our own
158 */
159 if (pdata->ref_div_factor)
160 r_cnt = pdata->ref_div_factor - 1;
161
Michael Hennerich8857df32012-07-20 09:31:00 +0100162 chspc = st->chspc;
Michael Henneriche31166f2012-05-29 12:41:20 +0200163
Michael Hennerich8857df32012-07-20 09:31:00 +0100164 do {
165 do {
166 do {
167 r_cnt = adf4350_tune_r_cnt(st, r_cnt);
168 st->r1_mod = st->fpfd / chspc;
169 if (r_cnt > ADF4350_MAX_R_CNT) {
170 /* try higher spacing values */
171 chspc++;
172 r_cnt = 0;
173 }
174 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
175 } while (r_cnt == 0);
Michael Henneriche31166f2012-05-29 12:41:20 +0200176
Michael Hennerich16909702012-12-06 16:09:00 +0000177 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
Michael Henneriche31166f2012-05-29 12:41:20 +0200178 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
179 st->r0_fract = do_div(tmp, st->r1_mod);
180 st->r0_int = tmp;
181 } while (mdiv > st->r0_int);
182
183 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
184
185 if (st->r0_fract && st->r1_mod) {
186 div_gcd = gcd(st->r1_mod, st->r0_fract);
187 st->r1_mod /= div_gcd;
188 st->r0_fract /= div_gcd;
189 } else {
190 st->r0_fract = 0;
191 st->r1_mod = 1;
192 }
193
194 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
195 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
196 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
197 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
198 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
199 band_sel_div);
200
201 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
202 ADF4350_REG0_FRACT(st->r0_fract);
203
Michael Hennerich8857df32012-07-20 09:31:00 +0100204 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) |
Michael Henneriche31166f2012-05-29 12:41:20 +0200205 ADF4350_REG1_MOD(st->r1_mod) |
206 prescaler;
207
208 st->regs[ADF4350_REG2] =
209 ADF4350_REG2_10BIT_R_CNT(r_cnt) |
210 ADF4350_REG2_DOUBLE_BUFF_EN |
211 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
212 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
213 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
214 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
215 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
Michael Hennerich2eb3a812013-06-03 14:30:00 +0100216 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
Michael Henneriche31166f2012-05-29 12:41:20 +0200217
218 st->regs[ADF4350_REG3] = pdata->r3_user_settings &
219 (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
220 ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
221 ADF4350_REG3_12BIT_CSR_EN |
222 ADF4351_REG3_CHARGE_CANCELLATION_EN |
223 ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
224 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
225
226 st->regs[ADF4350_REG4] =
227 ADF4350_REG4_FEEDBACK_FUND |
228 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
229 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
230 ADF4350_REG4_RF_OUT_EN |
231 (pdata->r4_user_settings &
232 (ADF4350_REG4_OUTPUT_PWR(0x3) |
233 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
234 ADF4350_REG4_AUX_OUTPUT_EN |
235 ADF4350_REG4_AUX_OUTPUT_FUND |
236 ADF4350_REG4_MUTE_TILL_LOCK_EN));
237
238 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
Michael Hennerich9404fa12013-06-03 14:30:00 +0100239 st->freq_req = freq;
Michael Henneriche31166f2012-05-29 12:41:20 +0200240
241 return adf4350_sync_config(st);
242}
243
244static ssize_t adf4350_write(struct iio_dev *indio_dev,
245 uintptr_t private,
246 const struct iio_chan_spec *chan,
247 const char *buf, size_t len)
248{
249 struct adf4350_state *st = iio_priv(indio_dev);
250 unsigned long long readin;
Michael Hennerich9404fa12013-06-03 14:30:00 +0100251 unsigned long tmp;
Michael Henneriche31166f2012-05-29 12:41:20 +0200252 int ret;
253
254 ret = kstrtoull(buf, 10, &readin);
255 if (ret)
256 return ret;
257
258 mutex_lock(&indio_dev->mlock);
259 switch ((u32)private) {
260 case ADF4350_FREQ:
261 ret = adf4350_set_freq(st, readin);
262 break;
263 case ADF4350_FREQ_REFIN:
Michael Hennerich9404fa12013-06-03 14:30:00 +0100264 if (readin > ADF4350_MAX_FREQ_REFIN) {
Michael Henneriche31166f2012-05-29 12:41:20 +0200265 ret = -EINVAL;
Michael Hennerich9404fa12013-06-03 14:30:00 +0100266 break;
267 }
268
269 if (st->clk) {
270 tmp = clk_round_rate(st->clk, readin);
271 if (tmp != readin) {
272 ret = -EINVAL;
273 break;
274 }
275 ret = clk_set_rate(st->clk, tmp);
276 if (ret < 0)
277 break;
278 }
279 st->clkin = readin;
280 ret = adf4350_set_freq(st, st->freq_req);
Michael Henneriche31166f2012-05-29 12:41:20 +0200281 break;
282 case ADF4350_FREQ_RESOLUTION:
283 if (readin == 0)
284 ret = -EINVAL;
285 else
286 st->chspc = readin;
287 break;
288 case ADF4350_PWRDOWN:
289 if (readin)
290 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
291 else
292 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
293
294 adf4350_sync_config(st);
295 break;
296 default:
Dan Carpenter1a135d12012-06-08 09:54:32 +0300297 ret = -EINVAL;
Michael Henneriche31166f2012-05-29 12:41:20 +0200298 }
299 mutex_unlock(&indio_dev->mlock);
300
301 return ret ? ret : len;
302}
303
304static ssize_t adf4350_read(struct iio_dev *indio_dev,
305 uintptr_t private,
306 const struct iio_chan_spec *chan,
307 char *buf)
308{
309 struct adf4350_state *st = iio_priv(indio_dev);
310 unsigned long long val;
311 int ret = 0;
312
313 mutex_lock(&indio_dev->mlock);
314 switch ((u32)private) {
315 case ADF4350_FREQ:
316 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
317 (u64)st->fpfd;
318 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
319 /* PLL unlocked? return error */
320 if (gpio_is_valid(st->pdata->gpio_lock_detect))
321 if (!gpio_get_value(st->pdata->gpio_lock_detect)) {
322 dev_dbg(&st->spi->dev, "PLL un-locked\n");
323 ret = -EBUSY;
324 }
325 break;
326 case ADF4350_FREQ_REFIN:
Michael Hennerich9404fa12013-06-03 14:30:00 +0100327 if (st->clk)
328 st->clkin = clk_get_rate(st->clk);
329
Michael Henneriche31166f2012-05-29 12:41:20 +0200330 val = st->clkin;
331 break;
332 case ADF4350_FREQ_RESOLUTION:
333 val = st->chspc;
334 break;
335 case ADF4350_PWRDOWN:
336 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
337 break;
Michael Hennericha21e6bf2012-06-05 11:52:18 +0200338 default:
Dan Carpenter1a135d12012-06-08 09:54:32 +0300339 ret = -EINVAL;
Michael Hennerich9404fa12013-06-03 14:30:00 +0100340 val = 0;
Michael Henneriche31166f2012-05-29 12:41:20 +0200341 }
342 mutex_unlock(&indio_dev->mlock);
343
344 return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
345}
346
347#define _ADF4350_EXT_INFO(_name, _ident) { \
348 .name = _name, \
349 .read = adf4350_read, \
350 .write = adf4350_write, \
351 .private = _ident, \
352}
353
354static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
355 /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
356 * values > 2^32 in order to support the entire frequency range
357 * in Hz. Using scale is a bit ugly.
358 */
359 _ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
360 _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
361 _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
362 _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
363 { },
364};
365
366static const struct iio_chan_spec adf4350_chan = {
367 .type = IIO_ALTVOLTAGE,
368 .indexed = 1,
369 .output = 1,
370 .ext_info = adf4350_ext_info,
371};
372
373static const struct iio_info adf4350_info = {
374 .debugfs_reg_access = &adf4350_reg_access,
375 .driver_module = THIS_MODULE,
376};
377
Greg Kroah-Hartmanfc526922012-12-21 13:21:43 -0800378static int adf4350_probe(struct spi_device *spi)
Michael Henneriche31166f2012-05-29 12:41:20 +0200379{
380 struct adf4350_platform_data *pdata = spi->dev.platform_data;
381 struct iio_dev *indio_dev;
382 struct adf4350_state *st;
Michael Hennerich9404fa12013-06-03 14:30:00 +0100383 struct clk *clk = NULL;
Michael Henneriche31166f2012-05-29 12:41:20 +0200384 int ret;
385
386 if (!pdata) {
387 dev_warn(&spi->dev, "no platform data? using default\n");
Michael Henneriche31166f2012-05-29 12:41:20 +0200388 pdata = &default_pdata;
389 }
390
Michael Hennerich9404fa12013-06-03 14:30:00 +0100391 if (!pdata->clkin) {
392 clk = clk_get(&spi->dev, "clkin");
393 if (IS_ERR(clk))
394 return -EPROBE_DEFER;
395
396 ret = clk_prepare_enable(clk);
397 if (ret < 0)
398 return ret;
399 }
400
Michael Henneriche31166f2012-05-29 12:41:20 +0200401 indio_dev = iio_device_alloc(sizeof(*st));
402 if (indio_dev == NULL)
403 return -ENOMEM;
404
405 st = iio_priv(indio_dev);
406
407 st->reg = regulator_get(&spi->dev, "vcc");
408 if (!IS_ERR(st->reg)) {
409 ret = regulator_enable(st->reg);
410 if (ret)
411 goto error_put_reg;
412 }
413
414 spi_set_drvdata(spi, indio_dev);
415 st->spi = spi;
416 st->pdata = pdata;
417
418 indio_dev->dev.parent = &spi->dev;
419 indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
420 spi_get_device_id(spi)->name;
421
422 indio_dev->info = &adf4350_info;
423 indio_dev->modes = INDIO_DIRECT_MODE;
424 indio_dev->channels = &adf4350_chan;
425 indio_dev->num_channels = 1;
426
427 st->chspc = pdata->channel_spacing;
Michael Hennerich9404fa12013-06-03 14:30:00 +0100428 if (clk) {
429 st->clk = clk;
430 st->clkin = clk_get_rate(clk);
431 } else {
432 st->clkin = pdata->clkin;
433 }
Michael Henneriche31166f2012-05-29 12:41:20 +0200434
435 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
436 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
437
438 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
439
440 if (gpio_is_valid(pdata->gpio_lock_detect)) {
441 ret = gpio_request(pdata->gpio_lock_detect, indio_dev->name);
442 if (ret) {
443 dev_err(&spi->dev, "fail to request lock detect GPIO-%d",
444 pdata->gpio_lock_detect);
445 goto error_disable_reg;
446 }
447 gpio_direction_input(pdata->gpio_lock_detect);
448 }
449
450 if (pdata->power_up_frequency) {
451 ret = adf4350_set_freq(st, pdata->power_up_frequency);
452 if (ret)
453 goto error_free_gpio;
454 }
455
456 ret = iio_device_register(indio_dev);
457 if (ret)
458 goto error_free_gpio;
459
460 return 0;
461
462error_free_gpio:
463 if (gpio_is_valid(pdata->gpio_lock_detect))
464 gpio_free(pdata->gpio_lock_detect);
465
466error_disable_reg:
467 if (!IS_ERR(st->reg))
468 regulator_disable(st->reg);
469error_put_reg:
470 if (!IS_ERR(st->reg))
471 regulator_put(st->reg);
472
Michael Hennerich9404fa12013-06-03 14:30:00 +0100473 if (clk)
474 clk_disable_unprepare(clk);
Michael Henneriche31166f2012-05-29 12:41:20 +0200475 iio_device_free(indio_dev);
476
477 return ret;
478}
479
Greg Kroah-Hartmanfc526922012-12-21 13:21:43 -0800480static int adf4350_remove(struct spi_device *spi)
Michael Henneriche31166f2012-05-29 12:41:20 +0200481{
482 struct iio_dev *indio_dev = spi_get_drvdata(spi);
483 struct adf4350_state *st = iio_priv(indio_dev);
484 struct regulator *reg = st->reg;
485
486 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
487 adf4350_sync_config(st);
488
489 iio_device_unregister(indio_dev);
490
Michael Hennerich9404fa12013-06-03 14:30:00 +0100491 if (st->clk)
492 clk_disable_unprepare(st->clk);
493
Michael Henneriche31166f2012-05-29 12:41:20 +0200494 if (!IS_ERR(reg)) {
495 regulator_disable(reg);
496 regulator_put(reg);
497 }
498
499 if (gpio_is_valid(st->pdata->gpio_lock_detect))
500 gpio_free(st->pdata->gpio_lock_detect);
501
502 iio_device_free(indio_dev);
503
504 return 0;
505}
506
507static const struct spi_device_id adf4350_id[] = {
508 {"adf4350", 4350},
509 {"adf4351", 4351},
510 {}
511};
512
513static struct spi_driver adf4350_driver = {
514 .driver = {
515 .name = "adf4350",
516 .owner = THIS_MODULE,
517 },
518 .probe = adf4350_probe,
Greg Kroah-Hartmanfc526922012-12-21 13:21:43 -0800519 .remove = adf4350_remove,
Michael Henneriche31166f2012-05-29 12:41:20 +0200520 .id_table = adf4350_id,
521};
522module_spi_driver(adf4350_driver);
523
Michael Hennerich9404fa12013-06-03 14:30:00 +0100524MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
Michael Henneriche31166f2012-05-29 12:41:20 +0200525MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
526MODULE_LICENSE("GPL v2");