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review.evervolv.com / android_kernel_oneplus_msm8996 / 9598566721fe7524cca575975ea7e8ea2e27a71b / . / arch / arm / boot / dts / tegra30.dtsi
blob: 6765646c2248bb36541a407ba64a54cac1a0dd02 [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]7 host1x {
8 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0xf04>;
98 };
99
Joseph Lo5ab134a2012-10-29 18:25:45 +0800[diff] [blame]100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <6 6 2>;
104 arm,tag-latency = <5 5 2>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]109 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]110 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]111 reg = <0x50041000 0x1000
112 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]113 interrupt-controller;
114 #interrupt-cells = <3>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]115 };
116
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]117 timer@60005000 {
118 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
119 reg = <0x60005000 0x400>;
120 interrupts = <0 0 0x04
121 0 1 0x04
122 0 41 0x04
123 0 42 0x04
124 0 121 0x04
125 0 122 0x04>;
126 };
127
Prashant Gaikwad95985662013-01-11 13:16:23 +0530[diff] [blame^]128 tegra_car: clock {
129 compatible = "nvidia,tegra30-car";
130 reg = <0x60006000 0x1000>;
131 #clock-cells = <1>;
132 };
133
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]134 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]135 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
136 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]137 interrupts = <0 104 0x04
138 0 105 0x04
139 0 106 0x04
140 0 107 0x04
141 0 108 0x04
142 0 109 0x04
143 0 110 0x04
144 0 111 0x04
145 0 112 0x04
146 0 113 0x04
147 0 114 0x04
148 0 115 0x04
149 0 116 0x04
150 0 117 0x04
151 0 118 0x04
152 0 119 0x04
153 0 128 0x04
154 0 129 0x04
155 0 130 0x04
156 0 131 0x04
157 0 132 0x04
158 0 133 0x04
159 0 134 0x04
160 0 135 0x04
161 0 136 0x04
162 0 137 0x04
163 0 138 0x04
164 0 139 0x04
165 0 140 0x04
166 0 141 0x04
167 0 142 0x04
168 0 143 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]169 };
170
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]171 ahb: ahb {
172 compatible = "nvidia,tegra30-ahb";
173 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
174 };
175
176 gpio: gpio {
177 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
178 reg = <0x6000d000 0x1000>;
179 interrupts = <0 32 0x04
180 0 33 0x04
181 0 34 0x04
182 0 35 0x04
183 0 55 0x04
184 0 87 0x04
185 0 89 0x04
186 0 125 0x04>;
187 #gpio-cells = <2>;
188 gpio-controller;
189 #interrupt-cells = <2>;
190 interrupt-controller;
191 };
192
193 pinmux: pinmux {
194 compatible = "nvidia,tegra30-pinmux";
Pritesh Raithatha322337b2012-10-30 15:37:09 +0530[diff] [blame]195 reg = <0x70000868 0xd4 /* Pad control registers */
196 0x70003000 0x3e4>; /* Mux registers */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]197 };
198
199 serial@70006000 {
200 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
201 reg = <0x70006000 0x40>;
202 reg-shift = <2>;
203 interrupts = <0 36 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]204 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]205 };
206
207 serial@70006040 {
208 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
209 reg = <0x70006040 0x40>;
210 reg-shift = <2>;
211 interrupts = <0 37 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]212 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]213 };
214
215 serial@70006200 {
216 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
217 reg = <0x70006200 0x100>;
218 reg-shift = <2>;
219 interrupts = <0 46 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]220 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]221 };
222
223 serial@70006300 {
224 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
225 reg = <0x70006300 0x100>;
226 reg-shift = <2>;
227 interrupts = <0 90 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]228 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]229 };
230
231 serial@70006400 {
232 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
233 reg = <0x70006400 0x100>;
234 reg-shift = <2>;
235 interrupts = <0 91 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]236 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]237 };
238
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]239 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]240 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
241 reg = <0x7000a000 0x100>;
242 #pwm-cells = <2>;
243 };
244
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]245 rtc {
246 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
247 reg = <0x7000e000 0x100>;
248 interrupts = <0 2 0x04>;
249 };
250
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]251 i2c@7000c000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]252 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]253 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]254 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]255 #address-cells = <1>;
256 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]257 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]258 };
259
260 i2c@7000c400 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]261 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]262 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]263 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]264 #address-cells = <1>;
265 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]266 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]267 };
268
269 i2c@7000c500 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]270 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]271 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]272 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]273 #address-cells = <1>;
274 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]275 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]276 };
277
278 i2c@7000c700 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]279 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
280 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]281 interrupts = <0 120 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]282 #address-cells = <1>;
283 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]284 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]285 };
286
287 i2c@7000d000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]288 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]289 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]290 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]291 #address-cells = <1>;
292 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]293 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]294 };
295
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]296 spi@7000d400 {
297 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
298 reg = <0x7000d400 0x200>;
299 interrupts = <0 59 0x04>;
300 nvidia,dma-request-selector = <&apbdma 15>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 status = "disabled";
304 };
305
306 spi@7000d600 {
307 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
308 reg = <0x7000d600 0x200>;
309 interrupts = <0 82 0x04>;
310 nvidia,dma-request-selector = <&apbdma 16>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 status = "disabled";
314 };
315
316 spi@7000d800 {
317 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
318 reg = <0x7000d480 0x200>;
319 interrupts = <0 83 0x04>;
320 nvidia,dma-request-selector = <&apbdma 17>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323 status = "disabled";
324 };
325
326 spi@7000da00 {
327 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
328 reg = <0x7000da00 0x200>;
329 interrupts = <0 93 0x04>;
330 nvidia,dma-request-selector = <&apbdma 18>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 status = "disabled";
334 };
335
336 spi@7000dc00 {
337 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
338 reg = <0x7000dc00 0x200>;
339 interrupts = <0 94 0x04>;
340 nvidia,dma-request-selector = <&apbdma 27>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 status = "disabled";
344 };
345
346 spi@7000de00 {
347 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
348 reg = <0x7000de00 0x200>;
349 interrupts = <0 79 0x04>;
350 nvidia,dma-request-selector = <&apbdma 28>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 status = "disabled";
354 };
355
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]356 pmc {
357 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
358 reg = <0x7000e400 0x400>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]359 };
360
hdoyu@nvidia.coma9140aa2012-05-16 19:47:44 +0000[diff] [blame]361 memory-controller {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]362 compatible = "nvidia,tegra30-mc";
363 reg = <0x7000f000 0x010
364 0x7000f03c 0x1b4
365 0x7000f200 0x028
366 0x7000f284 0x17c>;
367 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]368 };
369
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]370 smmu {
371 compatible = "nvidia,tegra30-smmu";
372 reg = <0x7000f010 0x02c
373 0x7000f1f0 0x010
374 0x7000f228 0x05c>;
375 nvidia,#asids = <4>; /* # of ASIDs */
376 dma-window = <0 0x40000000>; /* IOVA start & length */
377 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]378 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]379
380 ahub {
381 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]382 reg = <0x70080000 0x200
383 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]384 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]385 nvidia,dma-request-selector = <&apbdma 1>;
386
387 ranges;
388 #address-cells = <1>;
389 #size-cells = <1>;
390
391 tegra_i2s0: i2s@70080300 {
392 compatible = "nvidia,tegra30-i2s";
393 reg = <0x70080300 0x100>;
394 nvidia,ahub-cif-ids = <4 4>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]395 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]396 };
397
398 tegra_i2s1: i2s@70080400 {
399 compatible = "nvidia,tegra30-i2s";
400 reg = <0x70080400 0x100>;
401 nvidia,ahub-cif-ids = <5 5>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]402 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]403 };
404
405 tegra_i2s2: i2s@70080500 {
406 compatible = "nvidia,tegra30-i2s";
407 reg = <0x70080500 0x100>;
408 nvidia,ahub-cif-ids = <6 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]409 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]410 };
411
412 tegra_i2s3: i2s@70080600 {
413 compatible = "nvidia,tegra30-i2s";
414 reg = <0x70080600 0x100>;
415 nvidia,ahub-cif-ids = <7 7>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]416 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]417 };
418
419 tegra_i2s4: i2s@70080700 {
420 compatible = "nvidia,tegra30-i2s";
421 reg = <0x70080700 0x100>;
422 nvidia,ahub-cif-ids = <8 8>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]423 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]424 };
425 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]426
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]427 sdhci@78000000 {
428 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
429 reg = <0x78000000 0x200>;
430 interrupts = <0 14 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]431 status = "disabled";
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]432 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]433
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]434 sdhci@78000200 {
435 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
436 reg = <0x78000200 0x200>;
437 interrupts = <0 15 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]438 status = "disabled";
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]439 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]440
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]441 sdhci@78000400 {
442 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
443 reg = <0x78000400 0x200>;
444 interrupts = <0 19 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]445 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]446 };
447
448 sdhci@78000600 {
449 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
450 reg = <0x78000600 0x200>;
451 interrupts = <0 31 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]452 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]453 };
454
455 pmu {
456 compatible = "arm,cortex-a9-pmu";
457 interrupts = <0 144 0x04
458 0 145 0x04
459 0 146 0x04
460 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]461 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]462};