blob: 284038d4be863915ffe8c02c3dc92abfb193e3c8 [file] [log] [blame]
Mike Frysinger5d1617b2008-04-24 05:03:26 +08001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Copyright 2004-2009 Analog Devices Inc.
3 * 2007 David Rowe
4 * 2006 Intratrade Ltd.
5 * Ivan Danov <idanov@gmail.com>
6 * 2005 National ICT Australia (NICTA)
7 * Aidan Williams <aidan@nicta.com.au>
Mike Frysinger5d1617b2008-04-24 05:03:26 +08008 *
Robin Getz96f10502009-09-24 14:11:24 +00009 * Licensed under the GPL-2 or later.
Mike Frysinger5d1617b2008-04-24 05:03:26 +080010 */
11
12#include <linux/device.h>
13#include <linux/platform_device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h>
16#include <linux/spi/spi.h>
17#include <linux/spi/flash.h>
18#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
19#include <linux/usb/isp1362.h>
20#endif
21#include <asm/irq.h>
22#include <asm/bfin5xx_spi.h>
23
24/*
25 * Name the Board for the /proc/cpuinfo
26 */
27const char bfin_board_name[] = "IP04/IP08";
28
29/*
30 * Driver needs to know address, irq and flag pin.
31 */
32#if defined(CONFIG_BFIN532_IP0X)
33#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
34
35#include <linux/dm9000.h>
36
37static struct resource dm9000_resource1[] = {
38 {
39 .start = 0x20100000,
40 .end = 0x20100000 + 1,
41 .flags = IORESOURCE_MEM
42 },{
43 .start = 0x20100000 + 2,
44 .end = 0x20100000 + 3,
45 .flags = IORESOURCE_MEM
46 },{
47 .start = IRQ_PF15,
48 .end = IRQ_PF15,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
50 }
51};
52
53static struct resource dm9000_resource2[] = {
54 {
55 .start = 0x20200000,
56 .end = 0x20200000 + 1,
57 .flags = IORESOURCE_MEM
58 },{
59 .start = 0x20200000 + 2,
60 .end = 0x20200000 + 3,
61 .flags = IORESOURCE_MEM
62 },{
63 .start = IRQ_PF14,
64 .end = IRQ_PF14,
65 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
66 }
67};
68
69/*
70* for the moment we limit ourselves to 16bit IO until some
71* better IO routines can be written and tested
72*/
73static struct dm9000_plat_data dm9000_platdata1 = {
74 .flags = DM9000_PLATF_16BITONLY,
75};
76
77static struct platform_device dm9000_device1 = {
78 .name = "dm9000",
79 .id = 0,
80 .num_resources = ARRAY_SIZE(dm9000_resource1),
81 .resource = dm9000_resource1,
82 .dev = {
83 .platform_data = &dm9000_platdata1,
84 }
85};
86
87static struct dm9000_plat_data dm9000_platdata2 = {
88 .flags = DM9000_PLATF_16BITONLY,
89};
90
91static struct platform_device dm9000_device2 = {
92 .name = "dm9000",
93 .id = 1,
94 .num_resources = ARRAY_SIZE(dm9000_resource2),
95 .resource = dm9000_resource2,
96 .dev = {
97 .platform_data = &dm9000_platdata2,
98 }
99};
100
101#endif
102#endif
103
104
105#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
106/* all SPI peripherals info goes here */
107
Michael Hennerichf3f704d2009-03-06 00:27:57 +0800108#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
109static struct bfin5xx_spi_chip mmc_spi_chip_info = {
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800110/*
111 * CPOL (Clock Polarity)
112 * 0 - Active high SCK
113 * 1 - Active low SCK
114 * CPHA (Clock Phase) Selects transfer format and operation mode
115 * 0 - SCLK toggles from middle of the first data bit, slave select
116 * pins controlled by hardware.
117 * 1 - SCLK toggles from beginning of first data bit, slave select
118 * pins controller by user software.
119 * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work
120 * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0
121 * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1
122 */
123 .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */
124 .enable_dma = 0, /* if 1 - block!!! */
125 .bits_per_word = 8,
126 .cs_change_per_word = 0,
127};
128#endif
129
130/* Notice: for blackfin, the speed_hz is the value of register
131 * SPI_BAUD, not the real baudrate */
132static struct spi_board_info bfin_spi_board_info[] __initdata = {
Michael Hennerichf3f704d2009-03-06 00:27:57 +0800133#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800134 {
Michael Hennerichf3f704d2009-03-06 00:27:57 +0800135 .modalias = "mmc_spi",
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800136 .max_speed_hz = 2,
137 .bus_num = 1,
Michael Hennerichf3f704d2009-03-06 00:27:57 +0800138 .chip_select = 5,
139 .controller_data = &mmc_spi_chip_info,
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800140 },
141#endif
142};
143
144/* SPI controller data */
145static struct bfin5xx_spi_master spi_bfin_master_info = {
146 .num_chipselect = 8,
147 .enable_dma = 1, /* master has the ability to do dma transfer */
148};
149
150static struct platform_device spi_bfin_master_device = {
151 .name = "bfin-spi-master",
152 .id = 1, /* Bus number */
153 .dev = {
154 .platform_data = &spi_bfin_master_info, /* Passed to driver */
155 },
156};
157#endif /* spi master and devices */
158
159#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
160static struct resource bfin_uart_resources[] = {
161 {
162 .start = 0xFFC00400,
163 .end = 0xFFC004FF,
164 .flags = IORESOURCE_MEM,
165 },
166};
167
168static struct platform_device bfin_uart_device = {
169 .name = "bfin-uart",
170 .id = 1,
171 .num_resources = ARRAY_SIZE(bfin_uart_resources),
172 .resource = bfin_uart_resources,
173};
174#endif
175
Graf Yang5be36d22008-04-25 03:09:15 +0800176#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
Graf Yang5be36d22008-04-25 03:09:15 +0800177#ifdef CONFIG_BFIN_SIR0
Graf Yang42bd8bc2009-01-07 23:14:39 +0800178static struct resource bfin_sir0_resources[] = {
Graf Yang5be36d22008-04-25 03:09:15 +0800179 {
180 .start = 0xFFC00400,
181 .end = 0xFFC004FF,
182 .flags = IORESOURCE_MEM,
183 },
Graf Yang42bd8bc2009-01-07 23:14:39 +0800184 {
185 .start = IRQ_UART0_RX,
186 .end = IRQ_UART0_RX+1,
187 .flags = IORESOURCE_IRQ,
188 },
189 {
190 .start = CH_UART0_RX,
191 .end = CH_UART0_RX+1,
192 .flags = IORESOURCE_DMA,
193 },
Graf Yang5be36d22008-04-25 03:09:15 +0800194};
195
Graf Yang42bd8bc2009-01-07 23:14:39 +0800196static struct platform_device bfin_sir0_device = {
Graf Yang5be36d22008-04-25 03:09:15 +0800197 .name = "bfin_sir",
198 .id = 0,
Graf Yang42bd8bc2009-01-07 23:14:39 +0800199 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
200 .resource = bfin_sir0_resources,
Graf Yang5be36d22008-04-25 03:09:15 +0800201};
202#endif
Graf Yang42bd8bc2009-01-07 23:14:39 +0800203#endif
Graf Yang5be36d22008-04-25 03:09:15 +0800204
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800205#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
206static struct resource isp1362_hcd_resources[] = {
207 {
208 .start = 0x20300000,
209 .end = 0x20300000 + 1,
210 .flags = IORESOURCE_MEM,
211 },{
212 .start = 0x20300000 + 2,
213 .end = 0x20300000 + 3,
214 .flags = IORESOURCE_MEM,
215 },{
216 .start = IRQ_PF11,
217 .end = IRQ_PF11,
218 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
219 },
220};
221
222static struct isp1362_platform_data isp1362_priv = {
223 .sel15Kres = 1,
224 .clknotstop = 0,
225 .oc_enable = 0, /* external OC */
226 .int_act_high = 0,
227 .int_edge_triggered = 0,
228 .remote_wakeup_connected = 0,
229 .no_power_switching = 1,
230 .power_switching_mode = 0,
231};
232
233static struct platform_device isp1362_hcd_device = {
234 .name = "isp1362-hcd",
235 .id = 0,
236 .dev = {
237 .platform_data = &isp1362_priv,
238 },
239 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
240 .resource = isp1362_hcd_resources,
241};
242#endif
243
244
245static struct platform_device *ip0x_devices[] __initdata = {
246#if defined(CONFIG_BFIN532_IP0X)
247#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
248 &dm9000_device1,
249 &dm9000_device2,
250#endif
251#endif
252
253#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
254 &spi_bfin_master_device,
255#endif
256
257#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
258 &bfin_uart_device,
259#endif
Graf Yang5be36d22008-04-25 03:09:15 +0800260
261#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
Graf Yang42bd8bc2009-01-07 23:14:39 +0800262#ifdef CONFIG_BFIN_SIR0
263 &bfin_sir0_device,
264#endif
Graf Yang5be36d22008-04-25 03:09:15 +0800265#endif
266
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800267#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
268 &isp1362_hcd_device,
269#endif
270};
271
272static int __init ip0x_init(void)
273{
274 int i;
275
276 printk(KERN_INFO "%s(): registering device resources\n", __func__);
277 platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
278
279#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
280 for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
281 int j = 1 << bfin_spi_board_info[i].chip_select;
282 /* set spi cs to 1 */
283 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
284 bfin_write_FIO_FLAG_S(j);
285 }
286 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
287#endif
288
289 return 0;
290}
291
292arch_initcall(ip0x_init);