| Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * OMAP4 clock function prototypes and macros |
| 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 5 | */ |
| 6 | |
| 7 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H |
| 8 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H |
| 9 | |
| 10 | unsigned long omap3_dpll_recalc(struct clk *clk); |
| 11 | unsigned long omap3_clkoutx2_recalc(struct clk *clk); |
| 12 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); |
| 13 | |
| 14 | /* DPLL modes */ |
| 15 | #define DPLL_LOW_POWER_STOP 0x1 |
| 16 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| 17 | #define DPLL_LOCKED 0x7 |
| 18 | #define OMAP4430_MAX_DPLL_MULT 2048 |
| 19 | #define OMAP4430_MAX_DPLL_DIV 128 |
| 20 | |
| 21 | extern const struct clkops clkops_noncore_dpll_ops; |
| 22 | |
| 23 | #endif |