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review.evervolv.com / android_kernel_oneplus_msm8996 / 97a53092a148e6c70aabf13835143cc3dd4b524c / . / arch / arm / boot / dts / imx6q.dtsi
blob: 35e5895ba3df31856c73193a6bf79f791d54f985 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40
41 cpu@1 {
42 compatible = "arm,cortex-a9";
43 reg = <1>;
44 next-level-cache = <&L2>;
45 };
46
47 cpu@2 {
48 compatible = "arm,cortex-a9";
49 reg = <2>;
50 next-level-cache = <&L2>;
51 };
52
53 cpu@3 {
54 compatible = "arm,cortex-a9";
55 reg = <3>;
56 next-level-cache = <&L2>;
57 };
58 };
59
60 intc: interrupt-controller@00a01000 {
61 compatible = "arm,cortex-a9-gic";
62 #interrupt-cells = <3>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 interrupt-controller;
66 reg = <0x00a01000 0x1000>,
67 <0x00a00100 0x100>;
68 };
69
70 clocks {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 ckil {
75 compatible = "fsl,imx-ckil", "fixed-clock";
76 clock-frequency = <32768>;
77 };
78
79 ckih1 {
80 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <0>;
82 };
83
84 osc {
85 compatible = "fsl,imx-osc", "fixed-clock";
86 clock-frequency = <24000000>;
87 };
88 };
89
90 soc {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
94 interrupt-parent = <&intc>;
95 ranges;
96
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]97 dma-apbh@00110000 {
98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
99 reg = <0x00110000 0x2000>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]100 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]101 };
102
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]103 gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]104 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
108 reg-names = "gpmi-nand", "bch";
109 interrupts = <0 13 0x04>, <0 15 0x04>;
110 interrupt-names = "gpmi-dma", "bch";
111 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
112 <&clks 150>, <&clks 149>;
113 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
114 "gpmi_bch_apb", "per1_bch";
115 fsl,gpmi-dma-channel = <0>;
116 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]117 };
118
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]119 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]120 compatible = "arm,cortex-a9-twd-timer";
121 reg = <0x00a00600 0x20>;
122 interrupts = <1 13 0xf01>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]123 };
124
125 L2: l2-cache@00a02000 {
126 compatible = "arm,pl310-cache";
127 reg = <0x00a02000 0x1000>;
128 interrupts = <0 92 0x04>;
129 cache-unified;
130 cache-level = <2>;
131 };
132
133 aips-bus@02000000 { /* AIPS1 */
134 compatible = "fsl,aips-bus", "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 reg = <0x02000000 0x100000>;
138 ranges;
139
140 spba-bus@02000000 {
141 compatible = "fsl,spba-bus", "simple-bus";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 reg = <0x02000000 0x40000>;
145 ranges;
146
147 spdif@02004000 {
148 reg = <0x02004000 0x4000>;
149 interrupts = <0 52 0x04>;
150 };
151
152 ecspi@02008000 { /* eCSPI1 */
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
156 reg = <0x02008000 0x4000>;
157 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]158 clocks = <&clks 112>, <&clks 112>;
159 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]160 status = "disabled";
161 };
162
163 ecspi@0200c000 { /* eCSPI2 */
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
167 reg = <0x0200c000 0x4000>;
168 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]169 clocks = <&clks 113>, <&clks 113>;
170 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]171 status = "disabled";
172 };
173
174 ecspi@02010000 { /* eCSPI3 */
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02010000 0x4000>;
179 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]180 clocks = <&clks 114>, <&clks 114>;
181 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]182 status = "disabled";
183 };
184
185 ecspi@02014000 { /* eCSPI4 */
186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
189 reg = <0x02014000 0x4000>;
190 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]191 clocks = <&clks 115>, <&clks 115>;
192 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]193 status = "disabled";
194 };
195
196 ecspi@02018000 { /* eCSPI5 */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02018000 0x4000>;
201 interrupts = <0 35 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]202 clocks = <&clks 116>, <&clks 116>;
203 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]204 status = "disabled";
205 };
206
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]207 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]208 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
209 reg = <0x02020000 0x4000>;
210 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]211 clocks = <&clks 160>, <&clks 161>;
212 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]213 status = "disabled";
214 };
215
216 esai@02024000 {
217 reg = <0x02024000 0x4000>;
218 interrupts = <0 51 0x04>;
219 };
220
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]221 ssi1: ssi@02028000 {
222 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]223 reg = <0x02028000 0x4000>;
224 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]225 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]226 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <38 37>;
228 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]229 };
230
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]231 ssi2: ssi@0202c000 {
232 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]233 reg = <0x0202c000 0x4000>;
234 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]235 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]236 fsl,fifo-depth = <15>;
237 fsl,ssi-dma-events = <42 41>;
238 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]239 };
240
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]241 ssi3: ssi@02030000 {
242 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]243 reg = <0x02030000 0x4000>;
244 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]245 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]246 fsl,fifo-depth = <15>;
247 fsl,ssi-dma-events = <46 45>;
248 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]249 };
250
251 asrc@02034000 {
252 reg = <0x02034000 0x4000>;
253 interrupts = <0 50 0x04>;
254 };
255
256 spba@0203c000 {
257 reg = <0x0203c000 0x4000>;
258 };
259 };
260
261 vpu@02040000 {
262 reg = <0x02040000 0x3c000>;
263 interrupts = <0 3 0x04 0 12 0x04>;
264 };
265
266 aipstz@0207c000 { /* AIPSTZ1 */
267 reg = <0x0207c000 0x4000>;
268 };
269
270 pwm@02080000 { /* PWM1 */
271 reg = <0x02080000 0x4000>;
272 interrupts = <0 83 0x04>;
273 };
274
275 pwm@02084000 { /* PWM2 */
276 reg = <0x02084000 0x4000>;
277 interrupts = <0 84 0x04>;
278 };
279
280 pwm@02088000 { /* PWM3 */
281 reg = <0x02088000 0x4000>;
282 interrupts = <0 85 0x04>;
283 };
284
285 pwm@0208c000 { /* PWM4 */
286 reg = <0x0208c000 0x4000>;
287 interrupts = <0 86 0x04>;
288 };
289
290 flexcan@02090000 { /* CAN1 */
291 reg = <0x02090000 0x4000>;
292 interrupts = <0 110 0x04>;
293 };
294
295 flexcan@02094000 { /* CAN2 */
296 reg = <0x02094000 0x4000>;
297 interrupts = <0 111 0x04>;
298 };
299
300 gpt@02098000 {
301 compatible = "fsl,imx6q-gpt";
302 reg = <0x02098000 0x4000>;
303 interrupts = <0 55 0x04>;
304 };
305
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]306 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]307 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]308 reg = <0x0209c000 0x4000>;
309 interrupts = <0 66 0x04 0 67 0x04>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]313 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]314 };
315
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]316 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]317 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]318 reg = <0x020a0000 0x4000>;
319 interrupts = <0 68 0x04 0 69 0x04>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]323 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]324 };
325
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]326 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]327 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]328 reg = <0x020a4000 0x4000>;
329 interrupts = <0 70 0x04 0 71 0x04>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]333 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]334 };
335
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]336 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]338 reg = <0x020a8000 0x4000>;
339 interrupts = <0 72 0x04 0 73 0x04>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]343 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]344 };
345
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]346 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]348 reg = <0x020ac000 0x4000>;
349 interrupts = <0 74 0x04 0 75 0x04>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]353 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]354 };
355
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]356 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]357 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]358 reg = <0x020b0000 0x4000>;
359 interrupts = <0 76 0x04 0 77 0x04>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]363 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]364 };
365
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]366 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]367 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]368 reg = <0x020b4000 0x4000>;
369 interrupts = <0 78 0x04 0 79 0x04>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]373 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]374 };
375
376 kpp@020b8000 {
377 reg = <0x020b8000 0x4000>;
378 interrupts = <0 82 0x04>;
379 };
380
381 wdog@020bc000 { /* WDOG1 */
382 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
383 reg = <0x020bc000 0x4000>;
384 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]385 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]386 };
387
388 wdog@020c0000 { /* WDOG2 */
389 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
390 reg = <0x020c0000 0x4000>;
391 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]392 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]393 status = "disabled";
394 };
395
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]396 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]397 compatible = "fsl,imx6q-ccm";
398 reg = <0x020c4000 0x4000>;
399 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]400 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]401 };
402
403 anatop@020c8000 {
404 compatible = "fsl,imx6q-anatop";
405 reg = <0x020c8000 0x1000>;
406 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]407
408 regulator-1p1@110 {
409 compatible = "fsl,anatop-regulator";
410 regulator-name = "vdd1p1";
411 regulator-min-microvolt = <800000>;
412 regulator-max-microvolt = <1375000>;
413 regulator-always-on;
414 anatop-reg-offset = <0x110>;
415 anatop-vol-bit-shift = <8>;
416 anatop-vol-bit-width = <5>;
417 anatop-min-bit-val = <4>;
418 anatop-min-voltage = <800000>;
419 anatop-max-voltage = <1375000>;
420 };
421
422 regulator-3p0@120 {
423 compatible = "fsl,anatop-regulator";
424 regulator-name = "vdd3p0";
425 regulator-min-microvolt = <2800000>;
426 regulator-max-microvolt = <3150000>;
427 regulator-always-on;
428 anatop-reg-offset = <0x120>;
429 anatop-vol-bit-shift = <8>;
430 anatop-vol-bit-width = <5>;
431 anatop-min-bit-val = <0>;
432 anatop-min-voltage = <2625000>;
433 anatop-max-voltage = <3400000>;
434 };
435
436 regulator-2p5@130 {
437 compatible = "fsl,anatop-regulator";
438 regulator-name = "vdd2p5";
439 regulator-min-microvolt = <2000000>;
440 regulator-max-microvolt = <2750000>;
441 regulator-always-on;
442 anatop-reg-offset = <0x130>;
443 anatop-vol-bit-shift = <8>;
444 anatop-vol-bit-width = <5>;
445 anatop-min-bit-val = <0>;
446 anatop-min-voltage = <2000000>;
447 anatop-max-voltage = <2750000>;
448 };
449
450 regulator-vddcore@140 {
451 compatible = "fsl,anatop-regulator";
452 regulator-name = "cpu";
453 regulator-min-microvolt = <725000>;
454 regulator-max-microvolt = <1450000>;
455 regulator-always-on;
456 anatop-reg-offset = <0x140>;
457 anatop-vol-bit-shift = <0>;
458 anatop-vol-bit-width = <5>;
459 anatop-min-bit-val = <1>;
460 anatop-min-voltage = <725000>;
461 anatop-max-voltage = <1450000>;
462 };
463
464 regulator-vddpu@140 {
465 compatible = "fsl,anatop-regulator";
466 regulator-name = "vddpu";
467 regulator-min-microvolt = <725000>;
468 regulator-max-microvolt = <1450000>;
469 regulator-always-on;
470 anatop-reg-offset = <0x140>;
471 anatop-vol-bit-shift = <9>;
472 anatop-vol-bit-width = <5>;
473 anatop-min-bit-val = <1>;
474 anatop-min-voltage = <725000>;
475 anatop-max-voltage = <1450000>;
476 };
477
478 regulator-vddsoc@140 {
479 compatible = "fsl,anatop-regulator";
480 regulator-name = "vddsoc";
481 regulator-min-microvolt = <725000>;
482 regulator-max-microvolt = <1450000>;
483 regulator-always-on;
484 anatop-reg-offset = <0x140>;
485 anatop-vol-bit-shift = <18>;
486 anatop-vol-bit-width = <5>;
487 anatop-min-bit-val = <1>;
488 anatop-min-voltage = <725000>;
489 anatop-max-voltage = <1450000>;
490 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]491 };
492
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]493 usbphy1: usbphy@020c9000 {
494 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]495 reg = <0x020c9000 0x1000>;
496 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]497 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]498 };
499
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]500 usbphy2: usbphy@020ca000 {
501 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]502 reg = <0x020ca000 0x1000>;
503 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]504 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]505 };
506
507 snvs@020cc000 {
508 reg = <0x020cc000 0x4000>;
509 interrupts = <0 19 0x04 0 20 0x04>;
510 };
511
512 epit@020d0000 { /* EPIT1 */
513 reg = <0x020d0000 0x4000>;
514 interrupts = <0 56 0x04>;
515 };
516
517 epit@020d4000 { /* EPIT2 */
518 reg = <0x020d4000 0x4000>;
519 interrupts = <0 57 0x04>;
520 };
521
522 src@020d8000 {
523 compatible = "fsl,imx6q-src";
524 reg = <0x020d8000 0x4000>;
525 interrupts = <0 91 0x04 0 96 0x04>;
526 };
527
528 gpc@020dc000 {
529 compatible = "fsl,imx6q-gpc";
530 reg = <0x020dc000 0x4000>;
531 interrupts = <0 89 0x04 0 90 0x04>;
532 };
533
534 iomuxc@020e0000 {
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]535 compatible = "fsl,imx6q-iomuxc";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]536 reg = <0x020e0000 0x4000>;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]537
538 /* shared pinctrl settings */
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]539 audmux {
540 pinctrl_audmux_1: audmux-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]541 fsl,pins = <
542 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
543 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
544 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
545 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
546 >;
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]547 };
548 };
549
Shawn Guo52ccd492012-08-11 11:17:42 +0800[diff] [blame]550 ecspi1 {
551 pinctrl_ecspi1_1: ecspi1grp-1 {
552 fsl,pins = <
553 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
554 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
555 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
556 >;
557 };
558 };
559
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]560 enet {
561 pinctrl_enet_1: enetgrp-1 {
562 fsl,pins = <
563 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
564 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
565 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
566 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
567 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
568 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
569 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
570 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
571 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
572 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
573 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
574 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
575 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
576 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
577 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
578 >;
579 };
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]580
581 pinctrl_enet_2: enetgrp-2 {
582 fsl,pins = <
583 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
584 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
585 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
586 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
587 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
588 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
589 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
590 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
591 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
592 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
593 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
594 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
595 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
596 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
597 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
598 >;
599 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]600 };
601
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]602 gpmi-nand {
603 pinctrl_gpmi_nand_1: gpmi-nand-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]604 fsl,pins = <
605 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
606 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
607 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
608 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
609 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
610 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
611 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
612 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
613 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
614 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
615 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
616 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
617 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
618 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
619 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
620 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
621 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
622 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
623 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
624 >;
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]625 };
626 };
627
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]628 i2c1 {
629 pinctrl_i2c1_1: i2c1grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]630 fsl,pins = <
631 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
632 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
633 >;
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]634 };
635 };
636
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]637 uart1 {
638 pinctrl_uart1_1: uart1grp-1 {
639 fsl,pins = <
640 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
641 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
642 >;
643 };
644 };
645
Shawn Guoe30ba892012-08-11 12:33:51 +0800[diff] [blame]646 uart2 {
647 pinctrl_uart2_1: uart2grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]648 fsl,pins = <
649 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
650 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
651 >;
Richard Zhaoc3001b22012-05-09 14:44:47 +0800[diff] [blame]652 };
653 };
654
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]655 uart4 {
656 pinctrl_uart4_1: uart4grp-1 {
657 fsl,pins = <
658 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
659 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
660 >;
661 };
662 };
663
Richard Zhao97a53092012-09-19 11:25:16 +0800[diff] [blame^]664 usbotg {
665 pinctrl_usbotg_1: usbotggrp-1 {
666 fsl,pins = <
667 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
668 >;
669 };
670 };
671
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]672 usdhc2 {
673 pinctrl_usdhc2_1: usdhc2grp-1 {
674 fsl,pins = <
675 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
676 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
677 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
678 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
679 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
680 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
681 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
682 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
683 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
684 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
685 >;
686 };
687 };
688
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]689 usdhc3 {
690 pinctrl_usdhc3_1: usdhc3grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]691 fsl,pins = <
692 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
693 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
694 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
695 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
696 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
697 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
698 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
699 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
700 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
701 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
702 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]703 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]704
705 pinctrl_usdhc3_2: usdhc3grp-2 {
706 fsl,pins = <
707 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
708 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
709 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
710 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
711 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
712 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
713 >;
714 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]715 };
716
717 usdhc4 {
718 pinctrl_usdhc4_1: usdhc4grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]719 fsl,pins = <
720 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
721 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
722 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
723 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
724 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
725 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
726 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
727 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
728 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
729 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
730 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]731 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]732
733 pinctrl_usdhc4_2: usdhc4grp-2 {
734 fsl,pins = <
735 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
736 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
737 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
738 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
739 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
740 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
741 >;
742 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]743 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]744 };
745
746 dcic@020e4000 { /* DCIC1 */
747 reg = <0x020e4000 0x4000>;
748 interrupts = <0 124 0x04>;
749 };
750
751 dcic@020e8000 { /* DCIC2 */
752 reg = <0x020e8000 0x4000>;
753 interrupts = <0 125 0x04>;
754 };
755
756 sdma@020ec000 {
757 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
758 reg = <0x020ec000 0x4000>;
759 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]760 clocks = <&clks 155>, <&clks 155>;
761 clock-names = "ipg", "ahb";
762 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]763 };
764 };
765
766 aips-bus@02100000 { /* AIPS2 */
767 compatible = "fsl,aips-bus", "simple-bus";
768 #address-cells = <1>;
769 #size-cells = <1>;
770 reg = <0x02100000 0x100000>;
771 ranges;
772
773 caam@02100000 {
774 reg = <0x02100000 0x40000>;
775 interrupts = <0 105 0x04 0 106 0x04>;
776 };
777
778 aipstz@0217c000 { /* AIPSTZ2 */
779 reg = <0x0217c000 0x4000>;
780 };
781
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]782 usb@02184000 { /* USB OTG */
783 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
784 reg = <0x02184000 0x200>;
785 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]786 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]787 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]788 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]789 status = "disabled";
790 };
791
792 usb@02184200 { /* USB1 */
793 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
794 reg = <0x02184200 0x200>;
795 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]796 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]797 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]798 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]799 status = "disabled";
800 };
801
802 usb@02184400 { /* USB2 */
803 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
804 reg = <0x02184400 0x200>;
805 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]806 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]807 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]808 status = "disabled";
809 };
810
811 usb@02184600 { /* USB3 */
812 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
813 reg = <0x02184600 0x200>;
814 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]815 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]816 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]817 status = "disabled";
818 };
819
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]820 usbmisc: usbmisc@02184800 {
821 #index-cells = <1>;
822 compatible = "fsl,imx6q-usbmisc";
823 reg = <0x02184800 0x200>;
824 clocks = <&clks 162>;
825 };
826
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]827 ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]828 compatible = "fsl,imx6q-fec";
829 reg = <0x02188000 0x4000>;
830 interrupts = <0 118 0x04 0 119 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]831 clocks = <&clks 117>, <&clks 117>;
832 clock-names = "ipg", "ahb";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]833 status = "disabled";
834 };
835
836 mlb@0218c000 {
837 reg = <0x0218c000 0x4000>;
838 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
839 };
840
841 usdhc@02190000 { /* uSDHC1 */
842 compatible = "fsl,imx6q-usdhc";
843 reg = <0x02190000 0x4000>;
844 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]845 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
846 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]847 status = "disabled";
848 };
849
850 usdhc@02194000 { /* uSDHC2 */
851 compatible = "fsl,imx6q-usdhc";
852 reg = <0x02194000 0x4000>;
853 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]854 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
855 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]856 status = "disabled";
857 };
858
859 usdhc@02198000 { /* uSDHC3 */
860 compatible = "fsl,imx6q-usdhc";
861 reg = <0x02198000 0x4000>;
862 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]863 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
864 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]865 status = "disabled";
866 };
867
868 usdhc@0219c000 { /* uSDHC4 */
869 compatible = "fsl,imx6q-usdhc";
870 reg = <0x0219c000 0x4000>;
871 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]872 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
873 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]874 status = "disabled";
875 };
876
877 i2c@021a0000 { /* I2C1 */
878 #address-cells = <1>;
879 #size-cells = <0>;
880 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
881 reg = <0x021a0000 0x4000>;
882 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]883 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]884 status = "disabled";
885 };
886
887 i2c@021a4000 { /* I2C2 */
888 #address-cells = <1>;
889 #size-cells = <0>;
890 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
891 reg = <0x021a4000 0x4000>;
892 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]893 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]894 status = "disabled";
895 };
896
897 i2c@021a8000 { /* I2C3 */
898 #address-cells = <1>;
899 #size-cells = <0>;
900 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
901 reg = <0x021a8000 0x4000>;
902 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]903 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]904 status = "disabled";
905 };
906
907 romcp@021ac000 {
908 reg = <0x021ac000 0x4000>;
909 };
910
911 mmdc@021b0000 { /* MMDC0 */
912 compatible = "fsl,imx6q-mmdc";
913 reg = <0x021b0000 0x4000>;
914 };
915
916 mmdc@021b4000 { /* MMDC1 */
917 reg = <0x021b4000 0x4000>;
918 };
919
920 weim@021b8000 {
921 reg = <0x021b8000 0x4000>;
922 interrupts = <0 14 0x04>;
923 };
924
925 ocotp@021bc000 {
926 reg = <0x021bc000 0x4000>;
927 };
928
929 ocotp@021c0000 {
930 reg = <0x021c0000 0x4000>;
931 interrupts = <0 21 0x04>;
932 };
933
934 tzasc@021d0000 { /* TZASC1 */
935 reg = <0x021d0000 0x4000>;
936 interrupts = <0 108 0x04>;
937 };
938
939 tzasc@021d4000 { /* TZASC2 */
940 reg = <0x021d4000 0x4000>;
941 interrupts = <0 109 0x04>;
942 };
943
944 audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]945 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]946 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]947 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]948 };
949
950 mipi@021dc000 { /* MIPI-CSI */
951 reg = <0x021dc000 0x4000>;
952 };
953
954 mipi@021e0000 { /* MIPI-DSI */
955 reg = <0x021e0000 0x4000>;
956 };
957
958 vdoa@021e4000 {
959 reg = <0x021e4000 0x4000>;
960 interrupts = <0 18 0x04>;
961 };
962
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]963 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]964 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
965 reg = <0x021e8000 0x4000>;
966 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]967 clocks = <&clks 160>, <&clks 161>;
968 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]969 status = "disabled";
970 };
971
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]972 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]973 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
974 reg = <0x021ec000 0x4000>;
975 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]976 clocks = <&clks 160>, <&clks 161>;
977 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]978 status = "disabled";
979 };
980
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]981 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]982 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
983 reg = <0x021f0000 0x4000>;
984 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]985 clocks = <&clks 160>, <&clks 161>;
986 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]987 status = "disabled";
988 };
989
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]990 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]991 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
992 reg = <0x021f4000 0x4000>;
993 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]994 clocks = <&clks 160>, <&clks 161>;
995 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]996 status = "disabled";
997 };
998 };
999 };
1000};