blob: e3d3b29abbb3d44d9a13e75018719dff6de4b42f [file] [log] [blame]
Peter De Schrijveradd29e62011-10-12 14:53:05 +03001/dts-v1/;
2
Peter De Schrijveradd29e62011-10-12 14:53:05 +03003/include/ "tegra20.dtsi"
4
5/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00006 model = "NVIDIA Tegra20 Ventana evaluation board";
Peter De Schrijveradd29e62011-10-12 14:53:05 +03007 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Peter De Schrijveradd29e62011-10-12 14:53:05 +03009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +030011 };
12
Stephen Warren97d55202013-01-02 14:53:21 -070013 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060025 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060026 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata";
32 nvidia,function = "ide";
33 };
34 atb {
35 nvidia,pins = "atb", "gma", "gme";
36 nvidia,function = "sdio4";
37 };
38 atc {
39 nvidia,pins = "atc";
40 nvidia,function = "nand";
41 };
42 atd {
43 nvidia,pins = "atd", "ate", "gmb", "spia",
44 "spib", "spic";
45 nvidia,function = "gmi";
46 };
47 cdev1 {
48 nvidia,pins = "cdev1";
49 nvidia,function = "plla_out";
50 };
51 cdev2 {
52 nvidia,pins = "cdev2";
53 nvidia,function = "pllp_out4";
54 };
55 crtp {
56 nvidia,pins = "crtp", "lm1";
57 nvidia,function = "crt";
58 };
59 csus {
60 nvidia,pins = "csus";
61 nvidia,function = "vi_sensor_clk";
62 };
63 dap1 {
64 nvidia,pins = "dap1";
65 nvidia,function = "dap1";
66 };
67 dap2 {
68 nvidia,pins = "dap2";
69 nvidia,function = "dap2";
70 };
71 dap3 {
72 nvidia,pins = "dap3";
73 nvidia,function = "dap3";
74 };
75 dap4 {
76 nvidia,pins = "dap4";
77 nvidia,function = "dap4";
78 };
Stephen Warrenecc295b2012-03-15 16:27:36 -060079 dta {
80 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
81 nvidia,function = "vi";
82 };
83 dtf {
84 nvidia,pins = "dtf";
85 nvidia,function = "i2c3";
86 };
87 gmc {
88 nvidia,pins = "gmc";
89 nvidia,function = "uartd";
90 };
91 gmd {
92 nvidia,pins = "gmd";
93 nvidia,function = "sflash";
94 };
95 gpu {
96 nvidia,pins = "gpu";
97 nvidia,function = "pwm";
98 };
99 gpu7 {
100 nvidia,pins = "gpu7";
101 nvidia,function = "rtck";
102 };
103 gpv {
104 nvidia,pins = "gpv", "slxa", "slxk";
105 nvidia,function = "pcie";
106 };
107 hdint {
Mark Zhangcf633462012-10-25 14:52:30 +0800108 nvidia,pins = "hdint";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600109 nvidia,function = "hdmi";
110 };
111 i2cp {
112 nvidia,pins = "i2cp";
113 nvidia,function = "i2cp";
114 };
115 irrx {
116 nvidia,pins = "irrx", "irtx";
117 nvidia,function = "uartb";
118 };
119 kbca {
120 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
121 "kbce", "kbcf";
122 nvidia,function = "kbc";
123 };
124 lcsn {
125 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
126 "lsdi", "lvp0";
127 nvidia,function = "rsvd4";
128 };
129 ld0 {
130 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
131 "ld5", "ld6", "ld7", "ld8", "ld9",
132 "ld10", "ld11", "ld12", "ld13", "ld14",
133 "ld15", "ld16", "ld17", "ldi", "lhp0",
134 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
135 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
136 "lspi", "lvp1", "lvs";
137 nvidia,function = "displaya";
138 };
Mark Zhangcf633462012-10-25 14:52:30 +0800139 owc {
140 nvidia,pins = "owc", "spdi", "spdo", "uac";
141 nvidia,function = "rsvd2";
142 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600143 pmc {
144 nvidia,pins = "pmc";
145 nvidia,function = "pwr_on";
146 };
147 rm {
148 nvidia,pins = "rm";
149 nvidia,function = "i2c1";
150 };
151 sdb {
152 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
153 nvidia,function = "sdio3";
154 };
155 sdio1 {
156 nvidia,pins = "sdio1";
157 nvidia,function = "sdio1";
158 };
159 slxd {
160 nvidia,pins = "slxd";
161 nvidia,function = "spdif";
162 };
163 spid {
164 nvidia,pins = "spid", "spie", "spif";
165 nvidia,function = "spi1";
166 };
167 spig {
168 nvidia,pins = "spig", "spih";
169 nvidia,function = "spi2_alt";
170 };
171 uaa {
172 nvidia,pins = "uaa", "uab", "uda";
173 nvidia,function = "ulpi";
174 };
175 uad {
176 nvidia,pins = "uad";
177 nvidia,function = "irda";
178 };
179 uca {
180 nvidia,pins = "uca", "ucb";
181 nvidia,function = "uartc";
182 };
183 conf_ata {
184 nvidia,pins = "ata", "atb", "atc", "atd",
185 "cdev1", "cdev2", "dap1", "dap2",
186 "dap4", "ddc", "dtf", "gma", "gmc",
187 "gme", "gpu", "gpu7", "i2cp", "irrx",
188 "irtx", "pta", "rm", "sdc", "sdd",
189 "slxc", "slxd", "slxk", "spdi", "spdo",
190 "uac", "uad", "uca", "ucb", "uda";
191 nvidia,pull = <0>;
192 nvidia,tristate = <0>;
193 };
194 conf_ate {
195 nvidia,pins = "ate", "csus", "dap3", "gmd",
196 "gpv", "owc", "spia", "spib", "spic",
197 "spid", "spie", "spig";
198 nvidia,pull = <0>;
199 nvidia,tristate = <1>;
200 };
201 conf_ck32 {
202 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
203 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
204 nvidia,pull = <0>;
205 };
206 conf_crtp {
207 nvidia,pins = "crtp", "gmb", "slxa", "spih";
208 nvidia,pull = <2>;
209 nvidia,tristate = <1>;
210 };
211 conf_dta {
212 nvidia,pins = "dta", "dtb", "dtc", "dtd";
213 nvidia,pull = <1>;
214 nvidia,tristate = <0>;
215 };
216 conf_dte {
217 nvidia,pins = "dte", "spif";
218 nvidia,pull = <1>;
219 nvidia,tristate = <1>;
220 };
221 conf_hdint {
222 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
223 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
224 nvidia,tristate = <1>;
225 };
226 conf_kbca {
227 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
228 "kbce", "kbcf", "sdio1", "uaa", "uab";
229 nvidia,pull = <2>;
230 nvidia,tristate = <0>;
231 };
232 conf_lc {
233 nvidia,pins = "lc", "ls";
234 nvidia,pull = <2>;
235 };
236 conf_ld0 {
237 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
238 "ld5", "ld6", "ld7", "ld8", "ld9",
239 "ld10", "ld11", "ld12", "ld13", "ld14",
240 "ld15", "ld16", "ld17", "ldi", "lhp0",
241 "lhp1", "lhp2", "lhs", "lm0", "lpp",
242 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
243 "lvp1", "lvs", "pmc", "sdb";
244 nvidia,tristate = <0>;
245 };
246 conf_ld17_0 {
247 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
248 "ld23_22";
249 nvidia,pull = <1>;
250 };
Wei Nic7294292012-09-21 16:54:58 +0800251 drive_sdio1 {
252 nvidia,pins = "drive_sdio1";
253 nvidia,high-speed-mode = <0>;
254 nvidia,schmitt = <1>;
255 nvidia,low-power-mode = <3>;
256 nvidia,pull-down-strength = <31>;
257 nvidia,pull-up-strength = <31>;
258 nvidia,slew-rate-rising = <3>;
259 nvidia,slew-rate-falling = <3>;
260 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600261 };
Mark Zhangcf633462012-10-25 14:52:30 +0800262
263 state_i2cmux_ddc: pinmux_i2cmux_ddc {
264 ddc {
265 nvidia,pins = "ddc";
266 nvidia,function = "i2c2";
267 };
268 pta {
269 nvidia,pins = "pta";
270 nvidia,function = "rsvd4";
271 };
272 };
273
274 state_i2cmux_pta: pinmux_i2cmux_pta {
275 ddc {
276 nvidia,pins = "ddc";
277 nvidia,function = "rsvd4";
278 };
279 pta {
280 nvidia,pins = "pta";
281 nvidia,function = "i2c2";
282 };
283 };
284
285 state_i2cmux_idle: pinmux_i2cmux_idle {
286 ddc {
287 nvidia,pins = "ddc";
288 nvidia,function = "rsvd4";
289 };
290 pta {
291 nvidia,pins = "pta";
292 nvidia,function = "rsvd4";
293 };
294 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600295 };
296
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600297 i2s@70002800 {
298 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600299 };
300
301 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600302 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600303 clock-frequency = <216000000>;
304 };
305
Stephen Warren88950f32011-11-21 14:44:09 -0700306 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600307 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700308 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700309
310 wm8903: wm8903@1a {
311 compatible = "wlf,wm8903";
312 reg = <0x1a>;
313 interrupt-parent = <&gpio>;
Stephen Warren95decf82012-05-11 16:11:38 -0600314 interrupts = <187 0x04>;
Stephen Warren797acf72012-01-11 16:09:57 -0700315
316 gpio-controller;
317 #gpio-cells = <2>;
318
319 micdet-cfg = <0>;
320 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600321 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700322 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530323
324 /* ALS and proximity sensor */
325 isl29018@44 {
326 compatible = "isil,isl29018";
327 reg = <0x44>;
328 interrupt-parent = <&gpio>;
329 interrupts = <202 0x04>; /*gpio PZ2 */
330 };
Stephen Warren88950f32011-11-21 14:44:09 -0700331 };
332
333 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600334 status = "okay";
Stephen Warren97d55202013-01-02 14:53:21 -0700335 clock-frequency = <100000>;
Stephen Warren88950f32011-11-21 14:44:09 -0700336 };
337
Mark Zhangcf633462012-10-25 14:52:30 +0800338 i2cmux {
339 compatible = "i2c-mux-pinctrl";
340 #address-cells = <1>;
341 #size-cells = <0>;
342
343 i2c-parent = <&{/i2c@7000c400}>;
344
345 pinctrl-names = "ddc", "pta", "idle";
346 pinctrl-0 = <&state_i2cmux_ddc>;
347 pinctrl-1 = <&state_i2cmux_pta>;
348 pinctrl-2 = <&state_i2cmux_idle>;
349
Stephen Warren97d55202013-01-02 14:53:21 -0700350 hdmi_ddc: i2c@0 {
Mark Zhangcf633462012-10-25 14:52:30 +0800351 reg = <0>;
352 #address-cells = <1>;
353 #size-cells = <0>;
354 };
355
356 i2c@1 {
357 reg = <1>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 };
361 };
362
Stephen Warren88950f32011-11-21 14:44:09 -0700363 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600364 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700365 clock-frequency = <400000>;
366 };
367
368 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600369 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700370 clock-frequency = <400000>;
Stephen Warren017a0102012-06-20 16:53:41 -0600371
372 pmic: tps6586x@34 {
373 compatible = "ti,tps6586x";
374 reg = <0x34>;
375 interrupts = <0 86 0x4>;
376
Stephen Warren44b12ef2012-09-11 11:42:26 -0600377 ti,system-power-controller;
378
Stephen Warren017a0102012-06-20 16:53:41 -0600379 #gpio-cells = <2>;
380 gpio-controller;
381
382 sys-supply = <&vdd_5v0_reg>;
383 vin-sm0-supply = <&sys_reg>;
384 vin-sm1-supply = <&sys_reg>;
385 vin-sm2-supply = <&sys_reg>;
386 vinldo01-supply = <&sm2_reg>;
387 vinldo23-supply = <&sm2_reg>;
388 vinldo4-supply = <&sm2_reg>;
389 vinldo678-supply = <&sm2_reg>;
390 vinldo9-supply = <&sm2_reg>;
391
392 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600393 sys_reg: sys {
Stephen Warren017a0102012-06-20 16:53:41 -0600394 regulator-name = "vdd_sys";
395 regulator-always-on;
396 };
397
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600398 sm0 {
Stephen Warren017a0102012-06-20 16:53:41 -0600399 regulator-name = "vdd_sm0,vdd_core";
400 regulator-min-microvolt = <1200000>;
401 regulator-max-microvolt = <1200000>;
402 regulator-always-on;
403 };
404
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600405 sm1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600406 regulator-name = "vdd_sm1,vdd_cpu";
407 regulator-min-microvolt = <1000000>;
408 regulator-max-microvolt = <1000000>;
409 regulator-always-on;
410 };
411
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600412 sm2_reg: sm2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600413 regulator-name = "vdd_sm2,vin_ldo*";
414 regulator-min-microvolt = <3700000>;
415 regulator-max-microvolt = <3700000>;
416 regulator-always-on;
417 };
418
419 /* LDO0 is not connected to anything */
420
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600421 ldo1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600422 regulator-name = "vdd_ldo1,avdd_pll*";
423 regulator-min-microvolt = <1100000>;
424 regulator-max-microvolt = <1100000>;
425 regulator-always-on;
426 };
427
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600428 ldo2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600429 regulator-name = "vdd_ldo2,vdd_rtc";
430 regulator-min-microvolt = <1200000>;
431 regulator-max-microvolt = <1200000>;
432 };
433
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600434 ldo3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600435 regulator-name = "vdd_ldo3,avdd_usb*";
436 regulator-min-microvolt = <3300000>;
437 regulator-max-microvolt = <3300000>;
438 regulator-always-on;
439 };
440
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600441 ldo4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600442 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
443 regulator-min-microvolt = <1800000>;
444 regulator-max-microvolt = <1800000>;
445 regulator-always-on;
446 };
447
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600448 ldo5 {
Stephen Warren017a0102012-06-20 16:53:41 -0600449 regulator-name = "vdd_ldo5,vcore_mmc";
450 regulator-min-microvolt = <2850000>;
451 regulator-max-microvolt = <2850000>;
452 regulator-always-on;
453 };
454
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600455 ldo6 {
Stephen Warren017a0102012-06-20 16:53:41 -0600456 regulator-name = "vdd_ldo6,avdd_vdac";
457 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>;
459 };
460
Stephen Warren97d55202013-01-02 14:53:21 -0700461 hdmi_vdd_reg: ldo7 {
Stephen Warren017a0102012-06-20 16:53:41 -0600462 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
463 regulator-min-microvolt = <3300000>;
464 regulator-max-microvolt = <3300000>;
465 };
466
Stephen Warren97d55202013-01-02 14:53:21 -0700467 hdmi_pll_reg: ldo8 {
Stephen Warren017a0102012-06-20 16:53:41 -0600468 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
469 regulator-min-microvolt = <1800000>;
470 regulator-max-microvolt = <1800000>;
471 };
472
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600473 ldo9 {
Stephen Warren017a0102012-06-20 16:53:41 -0600474 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
475 regulator-min-microvolt = <2850000>;
476 regulator-max-microvolt = <2850000>;
477 regulator-always-on;
478 };
479
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600480 ldo_rtc {
Stephen Warren017a0102012-06-20 16:53:41 -0600481 regulator-name = "vdd_rtc_out,vdd_cell";
482 regulator-min-microvolt = <3300000>;
483 regulator-max-microvolt = <3300000>;
484 regulator-always-on;
485 };
486 };
487 };
Thierry Redingee9f7262012-11-09 23:01:21 +0100488
489 temperature-sensor@4c {
490 compatible = "onnn,nct1008";
491 reg = <0x4c>;
492 };
Stephen Warren017a0102012-06-20 16:53:41 -0600493 };
494
495 pmc {
496 nvidia,invert-interrupt;
Stephen Warren88950f32011-11-21 14:44:09 -0700497 };
498
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600499 usb@c5000000 {
500 status = "okay";
501 };
502
Stephen Warrenc04abb32012-05-11 17:03:26 -0600503 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600504 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600505 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
506 };
507
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600508 usb@c5008000 {
509 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600510 };
511
Wei Nic7294292012-09-21 16:54:58 +0800512 sdhci@c8000000 {
513 status = "okay";
514 power-gpios = <&gpio 86 0>; /* gpio PK6 */
515 bus-width = <4>;
516 };
517
Stephen Warrenc04abb32012-05-11 17:03:26 -0600518 sdhci@c8000400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600519 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600520 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
521 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
522 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200523 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600524 };
525
526 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600527 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200528 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600529 };
530
Stephen Warren017a0102012-06-20 16:53:41 -0600531 regulators {
532 compatible = "simple-bus";
533 #address-cells = <1>;
534 #size-cells = <0>;
535
536 vdd_5v0_reg: regulator@0 {
537 compatible = "regulator-fixed";
538 reg = <0>;
539 regulator-name = "vdd_5v0";
540 regulator-min-microvolt = <5000000>;
541 regulator-max-microvolt = <5000000>;
542 regulator-always-on;
543 };
544
545 regulator@1 {
546 compatible = "regulator-fixed";
547 reg = <1>;
548 regulator-name = "vdd_1v5";
549 regulator-min-microvolt = <1500000>;
550 regulator-max-microvolt = <1500000>;
551 gpio = <&pmic 0 0>;
552 };
553
554 regulator@2 {
555 compatible = "regulator-fixed";
556 reg = <2>;
557 regulator-name = "vdd_1v2";
558 regulator-min-microvolt = <1200000>;
559 regulator-max-microvolt = <1200000>;
560 gpio = <&pmic 1 0>;
561 enable-active-high;
562 };
563
564 regulator@3 {
565 compatible = "regulator-fixed";
566 reg = <3>;
567 regulator-name = "vdd_pnl";
568 regulator-min-microvolt = <2800000>;
569 regulator-max-microvolt = <2800000>;
570 gpio = <&gpio 22 0>; /* gpio PC6 */
571 enable-active-high;
572 };
573
574 regulator@4 {
575 compatible = "regulator-fixed";
576 reg = <4>;
577 regulator-name = "vdd_bl";
578 regulator-min-microvolt = <2800000>;
579 regulator-max-microvolt = <2800000>;
580 gpio = <&gpio 176 0>; /* gpio PW0 */
581 enable-active-high;
582 };
583 };
584
Stephen Warren797acf72012-01-11 16:09:57 -0700585 sound {
586 compatible = "nvidia,tegra-audio-wm8903-ventana",
587 "nvidia,tegra-audio-wm8903";
588 nvidia,model = "NVIDIA Tegra Ventana";
589
590 nvidia,audio-routing =
591 "Headphone Jack", "HPOUTR",
592 "Headphone Jack", "HPOUTL",
593 "Int Spk", "ROP",
594 "Int Spk", "RON",
595 "Int Spk", "LOP",
596 "Int Spk", "LON",
597 "Mic Jack", "MICBIAS",
598 "IN1L", "Mic Jack";
599
600 nvidia,i2s-controller = <&tegra_i2s1>;
601 nvidia,audio-codec = <&wm8903>;
602
603 nvidia,spkr-en-gpios = <&wm8903 2 0>;
604 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
Stephen Warrenc44e4382012-05-11 16:21:10 -0600605 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
Stephen Warren797acf72012-01-11 16:09:57 -0700606 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
607 };
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300608};