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dmitry pervushinbc19d892009-04-22 23:57:28 +01001/*
2 * Freescale STMP378X platform support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22
23#include <asm/dma.h>
24#include <asm/setup.h>
25#include <asm/mach-types.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/irq.h>
29#include <asm/mach/map.h>
30#include <asm/mach/time.h>
31
32#include <mach/pins.h>
33#include <mach/pinmux.h>
34#include <mach/dma.h>
35#include <mach/hardware.h>
36#include <mach/system.h>
37#include <mach/platform.h>
38#include <mach/stmp3xxx.h>
39#include <mach/regs-icoll.h>
40#include <mach/regs-apbh.h>
41#include <mach/regs-apbx.h>
42
43#include "stmp378x.h"
44/*
45 * IRQ handling
46 */
47static void stmp378x_ack_irq(unsigned int irq)
48{
49 /* Tell ICOLL to release IRQ line */
dmitry pervushin98f420b2009-05-31 13:32:11 +010050 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
dmitry pervushinbc19d892009-04-22 23:57:28 +010051
52 /* ACK current interrupt */
dmitry pervushin98f420b2009-05-31 13:32:11 +010053 __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
54 REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
dmitry pervushinbc19d892009-04-22 23:57:28 +010055
56 /* Barrier */
dmitry pervushin98f420b2009-05-31 13:32:11 +010057 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
dmitry pervushinbc19d892009-04-22 23:57:28 +010058}
59
60static void stmp378x_mask_irq(unsigned int irq)
61{
62 /* IRQ disable */
dmitry pervushin98f420b2009-05-31 13:32:11 +010063 stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
64 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
dmitry pervushinbc19d892009-04-22 23:57:28 +010065}
66
67static void stmp378x_unmask_irq(unsigned int irq)
68{
69 /* IRQ enable */
dmitry pervushin98f420b2009-05-31 13:32:11 +010070 stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
71 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
dmitry pervushinbc19d892009-04-22 23:57:28 +010072}
73
74static struct irq_chip stmp378x_chip = {
75 .ack = stmp378x_ack_irq,
76 .mask = stmp378x_mask_irq,
77 .unmask = stmp378x_unmask_irq,
78};
79
80void __init stmp378x_init_irq(void)
81{
82 stmp3xxx_init_irq(&stmp378x_chip);
83}
84
85/*
86 * DMA interrupt handling
87 */
88void stmp3xxx_arch_dma_enable_interrupt(int channel)
89{
dmitry pervushin98f420b2009-05-31 13:32:11 +010090 void __iomem *c1, *c2;
dmitry pervushinbc19d892009-04-22 23:57:28 +010091
dmitry pervushin98f420b2009-05-31 13:32:11 +010092 switch (STMP3XXX_DMA_BUS(channel)) {
dmitry pervushinbc19d892009-04-22 23:57:28 +010093 case STMP3XXX_BUS_APBH:
dmitry pervushin98f420b2009-05-31 13:32:11 +010094 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
95 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
dmitry pervushinbc19d892009-04-22 23:57:28 +010096 break;
97
98 case STMP3XXX_BUS_APBX:
dmitry pervushin98f420b2009-05-31 13:32:11 +010099 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
100 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100101 break;
dmitry pervushin98f420b2009-05-31 13:32:11 +0100102
103 default:
104 return;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100105 }
dmitry pervushin98f420b2009-05-31 13:32:11 +0100106 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
107 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
dmitry pervushinbc19d892009-04-22 23:57:28 +0100108}
109EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
110
111void stmp3xxx_arch_dma_clear_interrupt(int channel)
112{
dmitry pervushin98f420b2009-05-31 13:32:11 +0100113 void __iomem *c1, *c2;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100114
dmitry pervushin98f420b2009-05-31 13:32:11 +0100115 switch (STMP3XXX_DMA_BUS(channel)) {
dmitry pervushinbc19d892009-04-22 23:57:28 +0100116 case STMP3XXX_BUS_APBH:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100117 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
118 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100119 break;
120
121 case STMP3XXX_BUS_APBX:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100122 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
123 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100124 break;
dmitry pervushin98f420b2009-05-31 13:32:11 +0100125
126 default:
127 return;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100128 }
dmitry pervushin98f420b2009-05-31 13:32:11 +0100129 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
130 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
dmitry pervushinbc19d892009-04-22 23:57:28 +0100131}
132EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
133
134int stmp3xxx_arch_dma_is_interrupt(int channel)
135{
dmitry pervushinbc19d892009-04-22 23:57:28 +0100136 int r = 0;
137
dmitry pervushin98f420b2009-05-31 13:32:11 +0100138 switch (STMP3XXX_DMA_BUS(channel)) {
dmitry pervushinbc19d892009-04-22 23:57:28 +0100139 case STMP3XXX_BUS_APBH:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100140 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
141 (1 << STMP3XXX_DMA_CHANNEL(channel));
dmitry pervushinbc19d892009-04-22 23:57:28 +0100142 break;
143
144 case STMP3XXX_BUS_APBX:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100145 r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
146 (1 << STMP3XXX_DMA_CHANNEL(channel));
dmitry pervushinbc19d892009-04-22 23:57:28 +0100147 break;
148 }
149 return r;
150}
151EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
152
153void stmp3xxx_arch_dma_reset_channel(int channel)
154{
dmitry pervushin98f420b2009-05-31 13:32:11 +0100155 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
156 void __iomem *c0;
157 u32 mask;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100158
dmitry pervushin98f420b2009-05-31 13:32:11 +0100159 switch (STMP3XXX_DMA_BUS(channel)) {
dmitry pervushinbc19d892009-04-22 23:57:28 +0100160 case STMP3XXX_BUS_APBH:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100161 c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
162 mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100163 break;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100164 case STMP3XXX_BUS_APBX:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100165 c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
166 mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100167 break;
dmitry pervushin98f420b2009-05-31 13:32:11 +0100168 default:
169 return;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100170 }
dmitry pervushin98f420b2009-05-31 13:32:11 +0100171
172 /* Reset channel and wait for it to complete */
173 stmp3xxx_setl(mask, c0);
174 while (__raw_readl(c0) & mask)
175 cpu_relax();
dmitry pervushinbc19d892009-04-22 23:57:28 +0100176}
177EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
178
179void stmp3xxx_arch_dma_freeze(int channel)
180{
dmitry pervushin98f420b2009-05-31 13:32:11 +0100181 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
182 u32 mask = 1 << chbit;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100183
dmitry pervushin98f420b2009-05-31 13:32:11 +0100184 switch (STMP3XXX_DMA_BUS(channel)) {
dmitry pervushinbc19d892009-04-22 23:57:28 +0100185 case STMP3XXX_BUS_APBH:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100186 stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
dmitry pervushinbc19d892009-04-22 23:57:28 +0100187 break;
188 case STMP3XXX_BUS_APBX:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100189 stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
dmitry pervushinbc19d892009-04-22 23:57:28 +0100190 break;
191 }
192}
193EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
194
195void stmp3xxx_arch_dma_unfreeze(int channel)
196{
dmitry pervushin98f420b2009-05-31 13:32:11 +0100197 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
198 u32 mask = 1 << chbit;
dmitry pervushinbc19d892009-04-22 23:57:28 +0100199
dmitry pervushin98f420b2009-05-31 13:32:11 +0100200 switch (STMP3XXX_DMA_BUS(channel)) {
dmitry pervushinbc19d892009-04-22 23:57:28 +0100201 case STMP3XXX_BUS_APBH:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100202 stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
dmitry pervushinbc19d892009-04-22 23:57:28 +0100203 break;
204 case STMP3XXX_BUS_APBX:
dmitry pervushin98f420b2009-05-31 13:32:11 +0100205 stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
dmitry pervushinbc19d892009-04-22 23:57:28 +0100206 break;
207 }
208}
209EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
210
211/*
212 * The registers are all very closely mapped, so we might as well map them all
213 * with a single mapping
214 *
215 * Logical Physical
216 * f0000000 80000000 On-chip registers
dmitry pervushin98f420b2009-05-31 13:32:11 +0100217 * f1000000 00000000 32k on-chip SRAM
dmitry pervushinbc19d892009-04-22 23:57:28 +0100218 */
219
220static struct map_desc stmp378x_io_desc[] __initdata = {
221 {
222 .virtual = (u32)STMP3XXX_REGS_BASE,
223 .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
224 .length = STMP3XXX_REGS_SIZE,
225 .type = MT_DEVICE,
226 },
227 {
228 .virtual = (u32)STMP3XXX_OCRAM_BASE,
229 .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
230 .length = STMP3XXX_OCRAM_SIZE,
231 .type = MT_DEVICE,
232 },
233};
234
235void __init stmp378x_map_io(void)
236{
237 iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
238}