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review.evervolv.com / android_kernel_oneplus_msm8996 / 99b0d4b7b09edeacf4542bced5c01239375b51a9 / . / arch / sh / include / asm / dma-sh.h
blob: f3acb8e34c6bef0b07e9dc65db0c8adc5a4502ef [file] [log] [blame]
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]1/*
2 * arch/sh/include/asm/dma-sh.h
3 *
4 * Copyright (C) 2000 Takashi YOSHII
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __DMA_SH_H
12#define __DMA_SH_H
13
Guennadi Liakhovetski8b1935e2010-02-11 16:50:14 +0000[diff] [blame]14#include <asm/dma-register.h>
15#include <cpu/dma-register.h>
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]16#include <cpu/dma.h>
17
18/* DMAOR contorl: The DMAOR access size is different by CPU.*/
19#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
Kuninori Morimotoedc67b22009-08-03 04:52:24 +0000[diff] [blame]20 defined(CONFIG_CPU_SUBTYPE_SH7724) || \
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]21 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
22 defined(CONFIG_CPU_SUBTYPE_SH7785)
23#define dmaor_read_reg(n) \
Paul Mundt9d56dd32010-01-26 12:58:40 +0900[diff] [blame]24 (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
25 : __raw_readw(SH_DMAC_BASE0 + DMAOR))
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]26#define dmaor_write_reg(n, data) \
Paul Mundt9d56dd32010-01-26 12:58:40 +0900[diff] [blame]27 (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
28 : __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]29#else /* Other CPU */
Paul Mundt9d56dd32010-01-26 12:58:40 +0900[diff] [blame]30#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
31#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]32#endif
33
34static int dmte_irq_map[] __maybe_unused = {
Nobuhiro Iwamatsu039a7182009-03-12 06:34:39 +0000[diff] [blame]35#if (MAX_DMA_CHANNELS >= 4)
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]36 DMTE0_IRQ,
37 DMTE0_IRQ + 1,
38 DMTE0_IRQ + 2,
39 DMTE0_IRQ + 3,
40#endif
Nobuhiro Iwamatsu039a7182009-03-12 06:34:39 +0000[diff] [blame]41#if (MAX_DMA_CHANNELS >= 6)
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]42 DMTE4_IRQ,
43 DMTE4_IRQ + 1,
44#endif
Nobuhiro Iwamatsu039a7182009-03-12 06:34:39 +0000[diff] [blame]45#if (MAX_DMA_CHANNELS >= 8)
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]46 DMTE6_IRQ,
47 DMTE6_IRQ + 1,
48#endif
Nobuhiro Iwamatsu039a7182009-03-12 06:34:39 +0000[diff] [blame]49#if (MAX_DMA_CHANNELS >= 12)
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]50 DMTE8_IRQ,
51 DMTE9_IRQ,
52 DMTE10_IRQ,
53 DMTE11_IRQ,
54#endif
55};
56
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]57/*
58 * Define the default configuration for dual address memory-memory transfer.
59 * The 0x400 value represents auto-request, external->external.
60 */
Guennadi Liakhovetski623b4ac2010-02-03 14:44:12 +0000[diff] [blame]61#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]62
63/* DMA base address */
64static u32 dma_base_addr[] __maybe_unused = {
Nobuhiro Iwamatsu039a7182009-03-12 06:34:39 +0000[diff] [blame]65#if (MAX_DMA_CHANNELS >= 4)
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]66 SH_DMAC_BASE0 + 0x00, /* channel 0 */
67 SH_DMAC_BASE0 + 0x10,
68 SH_DMAC_BASE0 + 0x20,
69 SH_DMAC_BASE0 + 0x30,
70#endif
Nobuhiro Iwamatsu039a7182009-03-12 06:34:39 +0000[diff] [blame]71#if (MAX_DMA_CHANNELS >= 6)
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]72 SH_DMAC_BASE0 + 0x50,
73 SH_DMAC_BASE0 + 0x60,
74#endif
Nobuhiro Iwamatsu039a7182009-03-12 06:34:39 +0000[diff] [blame]75#if (MAX_DMA_CHANNELS >= 8)
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]76 SH_DMAC_BASE1 + 0x00,
77 SH_DMAC_BASE1 + 0x10,
78#endif
Nobuhiro Iwamatsu039a7182009-03-12 06:34:39 +0000[diff] [blame]79#if (MAX_DMA_CHANNELS >= 12)
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]80 SH_DMAC_BASE1 + 0x20,
81 SH_DMAC_BASE1 + 0x30,
82 SH_DMAC_BASE1 + 0x50,
83 SH_DMAC_BASE1 + 0x60, /* channel 11 */
84#endif
85};
86
Nobuhiro Iwamatsu71b973a2009-03-10 17:26:49 +0900[diff] [blame]87#endif /* __DMA_SH_H */