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review.evervolv.com / android_kernel_oneplus_msm8996 / 9b7fc907d9378f86eb6b823bbe84ec9ed584b091 / . / arch / arm / mach-omap2 / powerdomain44xx.c
blob: 123a25f3b96f8085c76c1fada663baf61f7c36e6 [file] [log] [blame]
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]1/*
2 * OMAP4 powerdomain control
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/io.h>
16#include <linux/errno.h>
17#include <linux/delay.h>
18#include <plat/powerdomain.h>
19#include <plat/prcm.h>
20#include "prm.h"
21#include "prm-regbits-44xx.h"
22#include "powerdomains.h"
23
24static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
25{
26 prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
27 (pwrst << OMAP_POWERSTATE_SHIFT),
28 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
29 return 0;
30}
31
32static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
33{
34 return prm_read_mod_bits_shift(pwrdm->prcm_offs,
35 OMAP4_PM_PWSTCTRL, OMAP_POWERSTATE_MASK);
36}
37
38static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
39{
40 return prm_read_mod_bits_shift(pwrdm->prcm_offs,
41 OMAP4_PM_PWSTST, OMAP_POWERSTATEST_MASK);
42}
43
44static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
45{
46 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
47 OMAP4430_LASTPOWERSTATEENTERED_MASK);
48}
49
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame^]50static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
51{
52 prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
53 (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
54 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
55 return 0;
56}
57
Rajendra Nayak12627572010-12-21 20:01:18 -0700[diff] [blame]58static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
59{
60 u32 v;
61
62 v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
63 prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
64 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
65
66 return 0;
67}
68
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame^]69static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
70 u8 pwrst)
71{
72 u32 m;
73
74 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
75
76 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
77 OMAP4_PM_PWSTCTRL);
78
79 return 0;
80}
81
82static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
83 u8 pwrst)
84{
85 u32 m;
86
87 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
88
89 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
90 OMAP4_PM_PWSTCTRL);
91
92 return 0;
93}
94
Rajendra Nayak12627572010-12-21 20:01:18 -0700[diff] [blame]95static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
96{
97 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST,
98 OMAP4430_LOGICSTATEST_MASK);
99}
100
101static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
102{
103 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL,
104 OMAP4430_LOGICRETSTATE_MASK);
105}
106
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame^]107static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
108{
109 u32 m;
110
111 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
112
113 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, m);
114}
115
116static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
117{
118 u32 m;
119
120 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
121
122 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, m);
123}
124
125static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
126{
127 u32 c = 0;
128
129 /*
130 * REVISIT: pwrdm_wait_transition() may be better implemented
131 * via a callback and a periodic timer check -- how long do we expect
132 * powerdomain transitions to take?
133 */
134
135 /* XXX Is this udelay() value meaningful? */
136 while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) &
137 OMAP_INTRANSITION_MASK) &&
138 (c++ < PWRDM_TRANSITION_BAILOUT))
139 udelay(1);
140
141 if (c > PWRDM_TRANSITION_BAILOUT) {
142 printk(KERN_ERR "powerdomain: waited too long for "
143 "powerdomain %s to complete transition\n", pwrdm->name);
144 return -EAGAIN;
145 }
146
147 pr_debug("powerdomain: completed transition in %d loops\n", c);
148
149 return 0;
150}
151
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]152struct pwrdm_ops omap4_pwrdm_operations = {
153 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
154 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
155 .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst,
156 .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst,
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame^]157 .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange,
Rajendra Nayak12627572010-12-21 20:01:18 -0700[diff] [blame]158 .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst,
159 .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
160 .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
Rajendra Nayak9b7fc902010-12-21 20:01:19 -0700[diff] [blame^]161 .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst,
162 .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst,
163 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
164 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
165 .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
Rajendra Nayakf327e072010-12-21 20:01:18 -0700[diff] [blame]166};