| Paul Walmsley | a5ffef6 | 2011-09-14 16:01:21 -0600 | [diff] [blame] | 1 | /* |
| 2 | * OMAP2420 clockdomains |
| 3 | * |
| 4 | * Copyright (C) 2008-2011 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2008-2010 Nokia Corporation |
| 6 | * |
| 7 | * Paul Walmsley, Jouni Högander |
| 8 | * |
| 9 | * This file contains clockdomains and clockdomain wakeup dependencies |
| 10 | * for OMAP2420 chips. Some notes: |
| 11 | * |
| 12 | * A useful validation rule for struct clockdomain: Any clockdomain |
| 13 | * referenced by a wkdep_srcs must have a dep_bit assigned. So |
| 14 | * wkdep_srcs are really just software-controllable dependencies. |
| 15 | * Non-software-controllable dependencies do exist, but they are not |
| 16 | * encoded below (yet). |
| 17 | * |
| 18 | * 24xx does not support programmable sleep dependencies (SLEEPDEP) |
| 19 | * |
| 20 | * The overly-specific dep_bit names are due to a bit name collision |
| 21 | * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift |
| 22 | * value are the same for all powerdomains: 2 |
| 23 | * |
| 24 | * XXX should dep_bit be a mask, so we can test to see if it is 0 as a |
| 25 | * sanity check? |
| 26 | * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * To-Do List |
| 31 | * -> Port the Sleep/Wakeup dependencies for the domains |
| 32 | * from the Power domain framework |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/io.h> |
| 37 | |
| 38 | #include "clockdomain.h" |
| 39 | #include "prm2xxx_3xxx.h" |
| 40 | #include "cm2xxx_3xxx.h" |
| 41 | #include "cm-regbits-24xx.h" |
| 42 | #include "prm-regbits-24xx.h" |
| 43 | |
| 44 | /* |
| 45 | * Clockdomain dependencies for wkdeps |
| 46 | * |
| 47 | * XXX Hardware dependencies (e.g., dependencies that cannot be |
| 48 | * changed in software) are not included here yet, but should be. |
| 49 | */ |
| 50 | |
| 51 | /* Wakeup dependency source arrays */ |
| 52 | |
| 53 | /* 2420-specific possible wakeup dependencies */ |
| 54 | |
| 55 | /* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */ |
| 56 | static struct clkdm_dep mpu_2420_wkdeps[] = { |
| 57 | { .clkdm_name = "core_l3_clkdm" }, |
| 58 | { .clkdm_name = "core_l4_clkdm" }, |
| 59 | { .clkdm_name = "dsp_clkdm" }, |
| 60 | { .clkdm_name = "wkup_clkdm" }, |
| 61 | { NULL }, |
| 62 | }; |
| 63 | |
| 64 | /* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */ |
| 65 | static struct clkdm_dep core_2420_wkdeps[] = { |
| 66 | { .clkdm_name = "dsp_clkdm" }, |
| 67 | { .clkdm_name = "gfx_clkdm" }, |
| 68 | { .clkdm_name = "mpu_clkdm" }, |
| 69 | { .clkdm_name = "wkup_clkdm" }, |
| 70 | { NULL }, |
| 71 | }; |
| 72 | |
| 73 | /* |
| 74 | * 2420-only clockdomains |
| 75 | */ |
| 76 | |
| 77 | static struct clockdomain mpu_2420_clkdm = { |
| 78 | .name = "mpu_clkdm", |
| 79 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 80 | .flags = CLKDM_CAN_HWSUP, |
| 81 | .wkdep_srcs = mpu_2420_wkdeps, |
| 82 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
| 83 | }; |
| 84 | |
| 85 | static struct clockdomain iva1_2420_clkdm = { |
| 86 | .name = "iva1_clkdm", |
| 87 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 88 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 89 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, |
| 90 | .wkdep_srcs = dsp_24xx_wkdeps, |
| 91 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, |
| 92 | }; |
| 93 | |
| 94 | static struct clockdomain dsp_2420_clkdm = { |
| 95 | .name = "dsp_clkdm", |
| 96 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 97 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 98 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, |
| 99 | }; |
| 100 | |
| 101 | static struct clockdomain gfx_2420_clkdm = { |
| 102 | .name = "gfx_clkdm", |
| 103 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 104 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 105 | .wkdep_srcs = gfx_24xx_wkdeps, |
| 106 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, |
| 107 | }; |
| 108 | |
| 109 | static struct clockdomain core_l3_2420_clkdm = { |
| 110 | .name = "core_l3_clkdm", |
| 111 | .pwrdm = { .name = "core_pwrdm" }, |
| 112 | .flags = CLKDM_CAN_HWSUP, |
| 113 | .wkdep_srcs = core_2420_wkdeps, |
| 114 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, |
| 115 | }; |
| 116 | |
| 117 | static struct clockdomain core_l4_2420_clkdm = { |
| 118 | .name = "core_l4_clkdm", |
| 119 | .pwrdm = { .name = "core_pwrdm" }, |
| 120 | .flags = CLKDM_CAN_HWSUP, |
| 121 | .wkdep_srcs = core_2420_wkdeps, |
| 122 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, |
| 123 | }; |
| 124 | |
| 125 | static struct clockdomain dss_2420_clkdm = { |
| 126 | .name = "dss_clkdm", |
| 127 | .pwrdm = { .name = "core_pwrdm" }, |
| 128 | .flags = CLKDM_CAN_HWSUP, |
| 129 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, |
| 130 | }; |
| 131 | |
| 132 | static struct clockdomain *clockdomains_omap242x[] __initdata = { |
| 133 | &wkup_common_clkdm, |
| 134 | &cm_common_clkdm, |
| 135 | &prm_common_clkdm, |
| 136 | &mpu_2420_clkdm, |
| 137 | &iva1_2420_clkdm, |
| 138 | &dsp_2420_clkdm, |
| 139 | &gfx_2420_clkdm, |
| 140 | &core_l3_2420_clkdm, |
| 141 | &core_l4_2420_clkdm, |
| 142 | &dss_2420_clkdm, |
| 143 | NULL, |
| 144 | }; |
| 145 | |
| 146 | void __init omap242x_clockdomains_init(void) |
| 147 | { |
| 148 | if (!cpu_is_omap242x()) |
| 149 | return; |
| 150 | |
| 151 | clkdm_register_platform_funcs(&omap2_clkdm_operations); |
| 152 | clkdm_register_clkdms(clockdomains_omap242x); |
| 153 | clkdm_complete_init(); |
| 154 | } |