| H. J. Lu | 36d57ac | 2005-09-06 15:16:49 -0700 | [diff] [blame] | 1 | #ifndef __ASM_SH_AUXVEC_H | 
|  | 2 | #define __ASM_SH_AUXVEC_H | 
|  | 3 |  | 
| Paul Mundt | 19f9a34 | 2006-09-27 18:33:49 +0900 | [diff] [blame] | 4 | /* | 
|  | 5 | * Architecture-neutral AT_ values in 0-17, leave some room | 
|  | 6 | * for more of them. | 
|  | 7 | */ | 
|  | 8 |  | 
| Paul Mundt | 98c4ecd | 2007-12-10 16:21:57 +0900 | [diff] [blame] | 9 | /* | 
|  | 10 | * This entry gives some information about the FPU initialization | 
|  | 11 | * performed by the kernel. | 
|  | 12 | */ | 
|  | 13 | #define AT_FPUCW		18	/* Used FPU control word.  */ | 
|  | 14 |  | 
| Paul Mundt | c170f86 | 2008-07-29 23:12:25 +0900 | [diff] [blame] | 15 | #if defined(CONFIG_VSYSCALL) || !defined(__KERNEL__) | 
| Paul Mundt | 19f9a34 | 2006-09-27 18:33:49 +0900 | [diff] [blame] | 16 | /* | 
|  | 17 | * Only define this in the vsyscall case, the entry point to | 
|  | 18 | * the vsyscall page gets placed here. The kernel will attempt | 
|  | 19 | * to build a gate VMA we don't care about otherwise.. | 
|  | 20 | */ | 
|  | 21 | #define AT_SYSINFO_EHDR		33 | 
|  | 22 | #endif | 
|  | 23 |  | 
| Paul Mundt | cd01204 | 2007-12-10 15:50:28 +0900 | [diff] [blame] | 24 | /* | 
|  | 25 | * More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the | 
|  | 26 | * value is -1, then the cache doesn't exist.  Otherwise: | 
|  | 27 | * | 
|  | 28 | *    bit 0-3:	  Cache set-associativity; 0 means fully associative. | 
|  | 29 | *    bit 4-7:	  Log2 of cacheline size. | 
|  | 30 | *    bit 8-31:	  Size of the entire cache >> 8. | 
|  | 31 | */ | 
|  | 32 | #define AT_L1I_CACHESHAPE	34 | 
|  | 33 | #define AT_L1D_CACHESHAPE	35 | 
|  | 34 | #define AT_L2_CACHESHAPE	36 | 
|  | 35 |  | 
| H. J. Lu | 36d57ac | 2005-09-06 15:16:49 -0700 | [diff] [blame] | 36 | #endif /* __ASM_SH_AUXVEC_H */ |