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review.evervolv.com / android_kernel_oneplus_msm8996 / 9feded1ed36551391979c3ba5e880fd70c68f93f / . / arch / arm / boot / dts / imx6dl.dtsi
blob: 2ecbcbcabdc25f3981d71440a27baae87a35351c [file] [log] [blame]
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]11#include "imx6qdl.dtsi"
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]12#include "imx6dl-pinfunc.h"
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 };
24
25 cpu@1 {
26 compatible = "arm,cortex-a9";
27 reg = <1>;
28 next-level-cache = <&L2>;
29 };
30 };
31
32 soc {
33 aips1: aips-bus@02000000 {
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]34 iomuxc: iomuxc@020e0000 {
35 compatible = "fsl,imx6dl-iomuxc";
36 reg = <0x020e0000 0x4000>;
37
Huang Shijie32d77d12013-05-09 11:29:00 +0800[diff] [blame]38 ecspi1 {
39 pinctrl_ecspi1_1: ecspi1grp-1 {
40 fsl,pins = <
41 MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
42 MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
43 MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
44 >;
45 };
46 };
47
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]48 enet {
49 pinctrl_enet_1: enetgrp-1 {
50 fsl,pins = <
51 MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
52 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
53 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
54 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
55 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
56 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
57 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
58 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
59 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
60 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
61 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
62 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
63 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
64 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
65 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
66 MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
67 >;
68 };
Shawn Guo1aa8b3e2013-04-02 14:38:11 +0800[diff] [blame]69
70 pinctrl_enet_2: enetgrp-2 {
71 fsl,pins = <
72 MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
73 MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
74 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
75 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
76 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
77 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
78 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
79 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
80 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
81 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
82 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
83 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
84 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
85 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
86 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
87 >;
88 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]89 };
90
Huang Shijiedb372422013-05-07 15:39:19 +0800[diff] [blame]91 gpmi-nand {
92 pinctrl_gpmi_nand_1: gpmi-nand-1 {
93 fsl,pins = <
94 MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
95 MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
96 MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
97 MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
98 MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
99 MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
100 MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
101 MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
102 MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
103 MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
104 MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
105 MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
106 MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
107 MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
108 MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
109 MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
110 MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
111 >;
112 };
113 };
114
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]115 uart1 {
116 pinctrl_uart1_1: uart1grp-1 {
117 fsl,pins = <
118 MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
119 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
120 >;
121 };
122 };
123
Shawn Guo1aa8b3e2013-04-02 14:38:11 +0800[diff] [blame]124 uart4 {
125 pinctrl_uart4_1: uart4grp-1 {
126 fsl,pins = <
127 MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
128 MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
129 >;
130 };
131 };
132
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]133 usbotg {
134 pinctrl_usbotg_2: usbotggrp-2 {
135 fsl,pins = <
136 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
137 >;
138 };
139 };
140
141 usdhc2 {
142 pinctrl_usdhc2_1: usdhc2grp-1 {
143 fsl,pins = <
144 MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
145 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
146 MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
147 MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
148 MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
149 MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
150 MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
151 MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
152 MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
153 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
154 >;
155 };
156 };
157
158 usdhc3 {
159 pinctrl_usdhc3_1: usdhc3grp-1 {
160 fsl,pins = <
161 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
162 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
163 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
164 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
165 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
166 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
167 MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
168 MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
169 MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
170 MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
171 >;
172 };
Fabio Estevam89b82912013-04-03 09:29:16 -0300[diff] [blame]173
174 pinctrl_usdhc3_2: usdhc3grp_2 {
175 fsl,pins = <
176 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
177 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
178 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
179 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
180 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
181 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
182 >;
183 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]184 };
185
Huang Shijie9feded12013-05-28 14:20:11 +0800[diff] [blame^]186 weim {
187 pinctrl_weim_cs0_1: weim_cs0grp-1 {
188 fsl,pins = <
189 MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
190 >;
191 };
192
193 pinctrl_weim_nor_1: weim_norgrp-1 {
194 fsl,pins = <
195 MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
196 MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
197 MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
198 /* data */
199 MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
200 MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
201 MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
202 MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
203 MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
204 MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
205 MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
206 MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
207 MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
208 MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
209 MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
210 MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
211 MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
212 MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
213 MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
214 MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
215 /* address */
216 MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
217 MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
218 MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
219 MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
220 MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
221 MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
222 MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
223 MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
224 MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
225 MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
226 MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
227 MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
228 MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
229 MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
230 MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
231 MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
232 MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
233 MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
234 MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
235 MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
236 MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
237 MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
238 MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
239 MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
240 >;
241 };
242
243 };
Shawn Guo9a8d6d52013-04-02 14:04:45 +0800[diff] [blame]244
245 };
246
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]247 pxp: pxp@020f0000 {
248 reg = <0x020f0000 0x4000>;
249 interrupts = <0 98 0x04>;
250 };
251
252 epdc: epdc@020f4000 {
253 reg = <0x020f4000 0x4000>;
254 interrupts = <0 97 0x04>;
255 };
256
257 lcdif: lcdif@020f8000 {
258 reg = <0x020f8000 0x4000>;
259 interrupts = <0 39 0x04>;
260 };
261 };
262
263 aips2: aips-bus@02100000 {
264 i2c4: i2c@021f8000 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "fsl,imx1-i2c";
268 reg = <0x021f8000 0x4000>;
269 interrupts = <0 35 0x04>;
270 status = "disabled";
271 };
272 };
273 };
274};