blob: f9cecdfd05c5523cb6298a27a3d03706e92fb21a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Local APIC handling, local APIC timers
3 *
Ingo Molnar8f47e162009-01-31 02:03:42 +01004 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/kernel_stat.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010018#include <linux/mc146818rtc.h>
Thomas Gleixner70a20022008-01-30 13:30:18 +010019#include <linux/acpi_pmtmr.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010020#include <linux/clockchips.h>
21#include <linux/interrupt.h>
22#include <linux/bootmem.h>
Frederic Weisbeckerbcbc4f22008-12-09 23:54:20 +010023#include <linux/ftrace.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010024#include <linux/ioport.h>
25#include <linux/module.h>
26#include <linux/sysdev.h>
27#include <linux/delay.h>
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +053028#include <linux/timex.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010029#include <linux/dmar.h>
30#include <linux/init.h>
31#include <linux/cpu.h>
32#include <linux/dmi.h>
33#include <linux/nmi.h>
34#include <linux/smp.h>
35#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <asm/pgalloc.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010038#include <asm/atomic.h>
39#include <asm/mpspec.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070040#include <asm/i8253.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010041#include <asm/i8259.h>
Andi Kleen73dea472006-02-03 21:50:50 +010042#include <asm/proto.h>
Andi Kleen2c8c0e62006-09-26 10:52:32 +020043#include <asm/apic.h>
Ingo Molnard1de36f2009-01-31 01:59:14 +010044#include <asm/desc.h>
45#include <asm/hpet.h>
46#include <asm/idle.h>
47#include <asm/mtrr.h>
Jaswinder Singh Rajput2bc13792009-01-11 20:34:47 +053048#include <asm/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
Brian Gerstec70de82009-01-27 12:56:47 +090050unsigned int num_processors;
Ingo Molnarfdbecd92009-01-31 03:57:12 +010051
Brian Gerstec70de82009-01-27 12:56:47 +090052unsigned disabled_cpus __cpuinitdata;
Ingo Molnarfdbecd92009-01-31 03:57:12 +010053
Brian Gerstec70de82009-01-27 12:56:47 +090054/* Processor that is doing the boot up */
55unsigned int boot_cpu_physical_apicid = -1U;
Glauber Costa5af55732008-03-25 13:28:56 -030056
Cyrill Gorcunov80e56092008-08-24 02:01:42 -070057/*
Ingo Molnarfdbecd92009-01-31 03:57:12 +010058 * The highest APIC ID seen during enumeration.
59 *
60 * This determines the messaging protocol we can use: if all APIC IDs
61 * are in the 0 ... 7 range, then we can use logical addressing which
62 * has some performance advantages (better broadcasting).
63 *
64 * If there's an APIC ID above 8, we use physical addressing.
Cyrill Gorcunov80e56092008-08-24 02:01:42 -070065 */
Brian Gerstec70de82009-01-27 12:56:47 +090066unsigned int max_physical_apicid;
67
Ingo Molnarfdbecd92009-01-31 03:57:12 +010068/*
69 * Bitmask of physically existing CPUs:
70 */
Brian Gerstec70de82009-01-27 12:56:47 +090071physid_mask_t phys_cpu_present_map;
72
73/*
74 * Map cpu index to physical APIC ID
75 */
76DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
77DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
78EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
79EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
Cyrill Gorcunov80e56092008-08-24 02:01:42 -070080
Yinghai Lub3c51172008-08-24 02:01:46 -070081#ifdef CONFIG_X86_32
82/*
83 * Knob to control our willingness to enable the local APIC.
84 *
85 * +1=force-enable
86 */
87static int force_enable_local_apic;
88/*
89 * APIC command line parameters
90 */
91static int __init parse_lapic(char *arg)
92{
93 force_enable_local_apic = 1;
94 return 0;
95}
96early_param("lapic", parse_lapic);
Yinghai Luf28c0ae2008-08-24 02:01:49 -070097/* Local APIC was disabled by the BIOS and enabled by the kernel */
98static int enabled_via_apicbase;
99
Yinghai Lub3c51172008-08-24 02:01:46 -0700100#endif
101
102#ifdef CONFIG_X86_64
Chris Wrightbc1d99c2007-10-12 23:04:23 +0200103static int apic_calibrate_pmtmr __initdata;
Yinghai Lub3c51172008-08-24 02:01:46 -0700104static __init int setup_apicpmtimer(char *s)
105{
106 apic_calibrate_pmtmr = 1;
107 notsc_setup(NULL);
108 return 0;
109}
110__setup("apicpmtimer", setup_apicpmtimer);
111#endif
112
Yinghai Lu06cd9a72009-02-16 17:29:58 -0800113#ifdef CONFIG_X86_X2APIC
Suresh Siddha89027d32008-07-10 11:16:56 -0700114int x2apic;
Suresh Siddha6e1cb382008-07-10 11:16:58 -0700115/* x2apic enabled before OS handover */
Jaswinder Singhb6b301a2008-12-23 21:52:33 +0530116static int x2apic_preenabled;
117static int disable_x2apic;
Yinghai Lu49899ea2008-08-24 02:01:47 -0700118static __init int setup_nox2apic(char *str)
119{
120 disable_x2apic = 1;
121 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
122 return 0;
123}
124early_param("nox2apic", setup_nox2apic);
125#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126
Yinghai Lub3c51172008-08-24 02:01:46 -0700127unsigned long mp_lapic_addr;
128int disable_apic;
129/* Disable local APIC timer from the kernel commandline or via dmi quirk */
130static int disable_apic_timer __cpuinitdata;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100131/* Local APIC timer works in C2 */
Linus Torvalds2e7c2832007-03-23 11:32:31 -0700132int local_apic_timer_c2_ok;
133EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
134
Yinghai Luefa25592008-08-19 20:50:36 -0700135int first_system_vector = 0xfe;
136
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100137/*
138 * Debug level, exported for io_apic.c
139 */
Maciej W. Rozyckibaa13182008-07-14 18:44:51 +0100140unsigned int apic_verbosity;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100141
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -0700142int pic_mode;
143
Alexey Starikovskiybab4b272008-05-19 19:47:03 +0400144/* Have we found an MP table */
145int smp_found_config;
146
Aaron Durbin39928722006-12-07 02:14:01 +0100147static struct resource lapic_resource = {
148 .name = "Local APIC",
149 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
150};
151
Thomas Gleixnerd03030e2007-10-12 23:04:06 +0200152static unsigned int calibration_result;
153
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200154static int lapic_next_event(unsigned long delta,
155 struct clock_event_device *evt);
156static void lapic_timer_setup(enum clock_event_mode mode,
157 struct clock_event_device *evt);
Mike Travis96289372008-12-31 18:08:46 -0800158static void lapic_timer_broadcast(const struct cpumask *mask);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100159static void apic_pm_activate(void);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200160
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400161/*
162 * The local apic timer can be used for any function which is CPU local.
163 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200164static struct clock_event_device lapic_clockevent = {
165 .name = "lapic",
166 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
167 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
168 .shift = 32,
169 .set_mode = lapic_timer_setup,
170 .set_next_event = lapic_next_event,
171 .broadcast = lapic_timer_broadcast,
172 .rating = 100,
173 .irq = -1,
174};
175static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
176
Andi Kleend3432892008-01-30 13:33:17 +0100177static unsigned long apic_phys;
178
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100179/*
180 * Get the LAPIC version
181 */
182static inline int lapic_get_version(void)
183{
184 return GET_APIC_VERSION(apic_read(APIC_LVR));
185}
186
187/*
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400188 * Check, if the APIC is integrated or a separate chip
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100189 */
190static inline int lapic_is_integrated(void)
191{
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400192#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100193 return 1;
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400194#else
195 return APIC_INTEGRATED(lapic_get_version());
196#endif
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100197}
198
199/*
200 * Check, whether this is a modern or a first generation APIC
201 */
202static int modern_apic(void)
203{
204 /* AMD systems use old APIC versions, so check the CPU */
205 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
206 boot_cpu_data.x86 >= 0xf)
207 return 1;
208 return lapic_get_version() >= 0x14;
209}
210
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800211void native_apic_wait_icr_idle(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100212{
213 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
214 cpu_relax();
215}
216
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800217u32 native_safe_apic_wait_icr_idle(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100218{
219 u32 send_status;
220 int timeout;
221
222 timeout = 0;
223 do {
224 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
225 if (!send_status)
226 break;
227 udelay(100);
228 } while (timeout++ < 1000);
229
230 return send_status;
231}
232
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800233void native_apic_icr_write(u32 low, u32 id)
Suresh Siddha1b374e42008-07-10 11:16:49 -0700234{
Cyrill Gorcunoved4e5ec2008-08-15 13:51:20 +0200235 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
Suresh Siddha1b374e42008-07-10 11:16:49 -0700236 apic_write(APIC_ICR, low);
237}
238
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800239u64 native_apic_icr_read(void)
Suresh Siddha1b374e42008-07-10 11:16:49 -0700240{
241 u32 icr1, icr2;
242
243 icr2 = apic_read(APIC_ICR2);
244 icr1 = apic_read(APIC_ICR);
245
Cyrill Gorcunovcf9768d72008-08-16 23:21:55 +0400246 return icr1 | ((u64)icr2 << 32);
Suresh Siddha1b374e42008-07-10 11:16:49 -0700247}
248
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100249/**
250 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
251 */
Jan Beuliche9427102008-01-30 13:31:24 +0100252void __cpuinit enable_NMI_through_LVT0(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100253{
254 unsigned int v;
255
256 /* unmask and set to NMI */
257 v = APIC_DM_NMI;
Cyrill Gorcunovd4c63ec2008-07-24 13:52:29 +0200258
259 /* Level triggered for 82489DX (32bit mode) */
260 if (!lapic_is_integrated())
261 v |= APIC_LVT_LEVEL_TRIGGER;
262
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100263 apic_write(APIC_LVT0, v);
264}
265
Cyrill Gorcunov7c37e482008-08-24 02:01:40 -0700266#ifdef CONFIG_X86_32
267/**
268 * get_physical_broadcast - Get number of physical broadcast IDs
269 */
270int get_physical_broadcast(void)
271{
272 return modern_apic() ? 0xff : 0xf;
273}
274#endif
275
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100276/**
277 * lapic_get_maxlvt - get the maximum number of local vector table entries
278 */
279int lapic_get_maxlvt(void)
280{
Cyrill Gorcunov36a028d2008-07-24 13:52:28 +0200281 unsigned int v;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100282
283 v = apic_read(APIC_LVR);
Cyrill Gorcunov36a028d2008-07-24 13:52:28 +0200284 /*
285 * - we always have APIC integrated on 64bit mode
286 * - 82489DXs do not report # of LVT entries
287 */
288 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100289}
290
291/*
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400292 * Local APIC timer
293 */
294
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400295/* Clock divisor */
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400296#define APIC_DIVISOR 16
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200297
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100298/*
299 * This function sets up the local APIC timer, with a timeout of
300 * 'clocks' APIC bus clock. During calibration we actually call
301 * this function twice on the boot CPU, once with a bogus timeout
302 * value, second time for real. The other (noncalibrating) CPUs
303 * call this function only once, with the real, calibrated value.
304 *
305 * We do reads before writes even if unnecessary, to get around the
306 * P5 APIC double write bug.
307 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100308static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
309{
310 unsigned int lvtt_value, tmp_value;
311
312 lvtt_value = LOCAL_TIMER_VECTOR;
313 if (!oneshot)
314 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200315 if (!lapic_is_integrated())
316 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
317
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100318 if (!irqen)
319 lvtt_value |= APIC_LVT_MASKED;
320
321 apic_write(APIC_LVTT, lvtt_value);
322
323 /*
324 * Divide PICLK by 16
325 */
326 tmp_value = apic_read(APIC_TDCR);
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400327 apic_write(APIC_TDCR,
328 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
329 APIC_TDR_DIV_16);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100330
331 if (!oneshot)
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200332 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100333}
334
335/*
Robert Richter7b83dae2008-01-30 13:30:40 +0100336 * Setup extended LVT, AMD specific (K8, family 10h)
337 *
338 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
339 * MCE interrupts are supported. Thus MCE offset must be set to 0.
Robert Richter286f5712008-07-22 21:08:46 +0200340 *
341 * If mask=1, the LVT entry does not generate interrupts while mask=0
342 * enables the vector. See also the BKDGs.
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100343 */
Robert Richter7b83dae2008-01-30 13:30:40 +0100344
345#define APIC_EILVT_LVTOFF_MCE 0
346#define APIC_EILVT_LVTOFF_IBS 1
347
348static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100349{
Robert Richter7b83dae2008-01-30 13:30:40 +0100350 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100351 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
352
353 apic_write(reg, v);
354}
355
Robert Richter7b83dae2008-01-30 13:30:40 +0100356u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
357{
358 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
359 return APIC_EILVT_LVTOFF_MCE;
360}
361
362u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
363{
364 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
365 return APIC_EILVT_LVTOFF_IBS;
366}
Robert Richter6aa360e2008-07-23 15:28:14 +0200367EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
Robert Richter7b83dae2008-01-30 13:30:40 +0100368
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100369/*
370 * Program the next event, relative to now
371 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200372static int lapic_next_event(unsigned long delta,
373 struct clock_event_device *evt)
374{
375 apic_write(APIC_TMICT, delta);
376 return 0;
377}
378
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100379/*
380 * Setup the lapic timer in periodic or oneshot mode
381 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200382static void lapic_timer_setup(enum clock_event_mode mode,
383 struct clock_event_device *evt)
384{
385 unsigned long flags;
386 unsigned int v;
387
388 /* Lapic used as dummy for broadcast ? */
389 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
390 return;
391
392 local_irq_save(flags);
393
394 switch (mode) {
395 case CLOCK_EVT_MODE_PERIODIC:
396 case CLOCK_EVT_MODE_ONESHOT:
397 __setup_APIC_LVTT(calibration_result,
398 mode != CLOCK_EVT_MODE_PERIODIC, 1);
399 break;
400 case CLOCK_EVT_MODE_UNUSED:
401 case CLOCK_EVT_MODE_SHUTDOWN:
402 v = apic_read(APIC_LVTT);
403 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
404 apic_write(APIC_LVTT, v);
Thomas Gleixnera98f8fd2008-11-06 01:13:39 +0100405 apic_write(APIC_TMICT, 0xffffffff);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200406 break;
407 case CLOCK_EVT_MODE_RESUME:
408 /* Nothing to do here */
409 break;
410 }
411
412 local_irq_restore(flags);
413}
414
415/*
416 * Local APIC timer broadcast function
417 */
Mike Travis96289372008-12-31 18:08:46 -0800418static void lapic_timer_broadcast(const struct cpumask *mask)
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200419{
420#ifdef CONFIG_SMP
Ingo Molnardac5f412009-01-28 15:42:24 +0100421 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200422#endif
423}
424
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100425/*
426 * Setup the local APIC timer for this CPU. Copy the initilized values
427 * of the boot CPU and register the clock event in the framework.
428 */
Cyrill Gorcunovdb4b5522008-08-24 02:01:39 -0700429static void __cpuinit setup_APIC_timer(void)
Fernando Luis VazquezCao8339e9f2007-05-02 19:27:17 +0200430{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100431 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
432
433 memcpy(levt, &lapic_clockevent, sizeof(*levt));
Rusty Russell320ab2b2008-12-13 21:20:26 +1030434 levt->cpumask = cpumask_of(smp_processor_id());
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100435
436 clockevents_register_device(levt);
Fernando Luis VazquezCao8339e9f2007-05-02 19:27:17 +0200437}
438
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700439/*
440 * In this functions we calibrate APIC bus clocks to the external timer.
441 *
442 * We want to do the calibration only once since we want to have local timer
443 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
444 * frequency.
445 *
446 * This was previously done by reading the PIT/HPET and waiting for a wrap
447 * around to find out, that a tick has elapsed. I have a box, where the PIT
448 * readout is broken, so it never gets out of the wait loop again. This was
449 * also reported by others.
450 *
451 * Monitoring the jiffies value is inaccurate and the clockevents
452 * infrastructure allows us to do a simple substitution of the interrupt
453 * handler.
454 *
455 * The calibration routine also uses the pm_timer when possible, as the PIT
456 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
457 * back to normal later in the boot process).
458 */
459
460#define LAPIC_CAL_LOOPS (HZ/10)
461
462static __initdata int lapic_cal_loops = -1;
463static __initdata long lapic_cal_t1, lapic_cal_t2;
464static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
465static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
466static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
467
468/*
469 * Temporary interrupt handler.
470 */
471static void __init lapic_cal_handler(struct clock_event_device *dev)
472{
473 unsigned long long tsc = 0;
474 long tapic = apic_read(APIC_TMCCT);
475 unsigned long pm = acpi_pm_read_early();
476
477 if (cpu_has_tsc)
478 rdtscll(tsc);
479
480 switch (lapic_cal_loops++) {
481 case 0:
482 lapic_cal_t1 = tapic;
483 lapic_cal_tsc1 = tsc;
484 lapic_cal_pm1 = pm;
485 lapic_cal_j1 = jiffies;
486 break;
487
488 case LAPIC_CAL_LOOPS:
489 lapic_cal_t2 = tapic;
490 lapic_cal_tsc2 = tsc;
491 if (pm < lapic_cal_pm1)
492 pm += ACPI_PM_OVRRUN;
493 lapic_cal_pm2 = pm;
494 lapic_cal_j2 = jiffies;
495 break;
496 }
497}
498
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900499static int __init
500calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400501{
502 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
503 const long pm_thresh = pm_100ms / 100;
504 unsigned long mult;
505 u64 res;
506
507#ifndef CONFIG_X86_PM_TIMER
508 return -1;
509#endif
510
Yasuaki Ishimatsu39ba5d42009-01-28 12:52:24 +0900511 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400512
513 /* Check, if the PM timer is available */
514 if (!deltapm)
515 return -1;
516
517 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
518
519 if (deltapm > (pm_100ms - pm_thresh) &&
520 deltapm < (pm_100ms + pm_thresh)) {
Yasuaki Ishimatsu39ba5d42009-01-28 12:52:24 +0900521 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900522 return 0;
523 }
524
525 res = (((u64)deltapm) * mult) >> 22;
526 do_div(res, 1000000);
527 pr_warning("APIC calibration not consistent "
Yasuaki Ishimatsu39ba5d42009-01-28 12:52:24 +0900528 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900529
530 /* Correct the lapic counter value */
531 res = (((u64)(*delta)) * pm_100ms);
532 do_div(res, deltapm);
533 pr_info("APIC delta adjusted to PM-Timer: "
534 "%lu (%ld)\n", (unsigned long)res, *delta);
535 *delta = (long)res;
536
537 /* Correct the tsc counter value */
538 if (cpu_has_tsc) {
539 res = (((u64)(*deltatsc)) * pm_100ms);
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400540 do_div(res, deltapm);
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900541 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
542 "PM-Timer: %lu (%ld) \n",
543 (unsigned long)res, *deltatsc);
544 *deltatsc = (long)res;
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400545 }
546
547 return 0;
548}
549
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700550static int __init calibrate_APIC_clock(void)
551{
552 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700553 void (*real_handler)(struct clock_event_device *dev);
554 unsigned long deltaj;
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900555 long delta, deltatsc;
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700556 int pm_referenced = 0;
557
558 local_irq_disable();
559
560 /* Replace the global interrupt handler */
561 real_handler = global_clock_event->event_handler;
562 global_clock_event->event_handler = lapic_cal_handler;
563
564 /*
Cyrill Gorcunov81608f32008-10-10 19:00:17 +0400565 * Setup the APIC counter to maximum. There is no way the lapic
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700566 * can underflow in the 100ms detection time frame
567 */
Cyrill Gorcunov81608f32008-10-10 19:00:17 +0400568 __setup_APIC_LVTT(0xffffffff, 0, 0);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700569
570 /* Let the interrupts run */
571 local_irq_enable();
572
573 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
574 cpu_relax();
575
576 local_irq_disable();
577
578 /* Restore the real event handler */
579 global_clock_event->event_handler = real_handler;
580
581 /* Build delta t1-t2 as apic timer counts down */
582 delta = lapic_cal_t1 - lapic_cal_t2;
583 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
584
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900585 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
586
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400587 /* we trust the PM based calibration if possible */
588 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900589 &delta, &deltatsc);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700590
591 /* Calculate the scaled math multiplication factor */
592 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
593 lapic_clockevent.shift);
594 lapic_clockevent.max_delta_ns =
595 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
596 lapic_clockevent.min_delta_ns =
597 clockevent_delta2ns(0xF, &lapic_clockevent);
598
599 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
600
601 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
602 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
603 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
604 calibration_result);
605
606 if (cpu_has_tsc) {
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700607 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
608 "%ld.%04ld MHz.\n",
Yasuaki Ishimatsu754ef0c2009-01-28 12:51:09 +0900609 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
610 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700611 }
612
613 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
614 "%u.%04u MHz.\n",
615 calibration_result / (1000000 / HZ),
616 calibration_result % (1000000 / HZ));
617
618 /*
619 * Do a sanity check on the APIC calibration result
620 */
621 if (calibration_result < (1000000 / HZ)) {
622 local_irq_enable();
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100623 pr_warning("APIC frequency too slow, disabling apic timer\n");
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700624 return -1;
625 }
626
627 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
628
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400629 /*
630 * PM timer calibration failed or not turned on
631 * so lets try APIC timer based calibration
632 */
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700633 if (!pm_referenced) {
634 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
635
636 /*
637 * Setup the apic timer manually
638 */
639 levt->event_handler = lapic_cal_handler;
640 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
641 lapic_cal_loops = -1;
642
643 /* Let the interrupts run */
644 local_irq_enable();
645
646 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
647 cpu_relax();
648
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700649 /* Stop the lapic timer */
650 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
651
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700652 /* Jiffies delta */
653 deltaj = lapic_cal_j2 - lapic_cal_j1;
654 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
655
656 /* Check, if the jiffies result is consistent */
657 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
658 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
659 else
660 levt->features |= CLOCK_EVT_FEAT_DUMMY;
661 } else
662 local_irq_enable();
663
664 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +0530665 pr_warning("APIC timer disabled due to verification failure\n");
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700666 return -1;
667 }
668
669 return 0;
670}
671
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100672/*
673 * Setup the boot APIC
674 *
675 * Calibrate and verify the result.
676 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100677void __init setup_boot_APIC_clock(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100679 /*
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400680 * The local apic timer can be disabled via the kernel
681 * commandline or from the CPU detection code. Register the lapic
682 * timer as a dummy clock event source on SMP systems, so the
683 * broadcast mechanism is used. On UP systems simply ignore it.
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100684 */
685 if (disable_apic_timer) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100686 pr_info("Disabling APIC timer\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100687 /* No broadcast on UP ! */
Thomas Gleixner9d099512008-01-30 13:33:04 +0100688 if (num_possible_cpus() > 1) {
689 lapic_clockevent.mult = 1;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100690 setup_APIC_timer();
Thomas Gleixner9d099512008-01-30 13:33:04 +0100691 }
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100692 return;
693 }
Thomas Gleixner6935d1f2007-07-21 17:10:17 +0200694
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400695 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
696 "calibrating APIC timer ...\n");
697
Cyrill Gorcunov89b3b1f2008-07-15 21:02:54 +0400698 if (calibrate_APIC_clock()) {
Thomas Gleixnerc2b84b32008-01-30 13:33:04 +0100699 /* No broadcast on UP ! */
700 if (num_possible_cpus() > 1)
701 setup_APIC_timer();
702 return;
703 }
704
705 /*
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100706 * If nmi_watchdog is set to IO_APIC, we need the
707 * PIT/HPET going. Otherwise register lapic as a dummy
708 * device.
709 */
710 if (nmi_watchdog != NMI_IO_APIC)
711 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
712 else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100713 pr_warning("APIC timer registered as dummy,"
Cyrill Gorcunov116f5702008-06-24 22:52:04 +0200714 " due to nmi_watchdog=%d!\n", nmi_watchdog);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100715
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400716 /* Setup the lapic or request the broadcast */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100717 setup_APIC_timer();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718}
719
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100720void __cpuinit setup_secondary_APIC_clock(void)
721{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100722 setup_APIC_timer();
723}
724
725/*
726 * The guts of the apic timer interrupt
727 */
728static void local_apic_timer_interrupt(void)
729{
730 int cpu = smp_processor_id();
731 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
732
733 /*
734 * Normally we should not be here till LAPIC has been initialized but
735 * in some cases like kdump, its possible that there is a pending LAPIC
736 * timer interrupt from previous kernel's context and is delivered in
737 * new kernel the moment interrupts are enabled.
738 *
739 * Interrupts are enabled early and LAPIC is setup much later, hence
740 * its possible that when we get here evt->event_handler is NULL.
741 * Check for event_handler being NULL and discard the interrupt as
742 * spurious.
743 */
744 if (!evt->event_handler) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100745 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100746 /* Switch it off */
747 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
748 return;
749 }
750
751 /*
752 * the NMI deadlock-detector uses this.
753 */
Hiroshi Shimamoto915b0d02008-12-08 19:19:26 -0800754 inc_irq_stat(apic_timer_irqs);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100755
756 evt->event_handler(evt);
757}
758
759/*
760 * Local APIC timer interrupt. This is the most natural way for doing
761 * local interrupts, but local timer interrupts can be emulated by
762 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
763 *
764 * [ if a single-CPU system runs an SMP kernel then we call the local
765 * interrupt as well. Thus we cannot inline the local irq ... ]
766 */
Frederic Weisbeckerbcbc4f22008-12-09 23:54:20 +0100767void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100768{
769 struct pt_regs *old_regs = set_irq_regs(regs);
770
771 /*
772 * NOTE! We'd better ACK the irq immediately,
773 * because timer handling can be slow.
774 */
775 ack_APIC_irq();
776 /*
777 * update_process_times() expects us to have done irq_enter().
778 * Besides, if we don't timer interrupts ignore the global
779 * interrupt lock, which is the WrongThing (tm) to do.
780 */
781 exit_idle();
782 irq_enter();
783 local_apic_timer_interrupt();
784 irq_exit();
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400785
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100786 set_irq_regs(old_regs);
787}
788
789int setup_profiling_timer(unsigned int multiplier)
790{
791 return -EINVAL;
792}
793
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100794/*
795 * Local APIC start and shutdown
796 */
797
798/**
799 * clear_local_APIC - shutdown the local APIC
800 *
801 * This is called, when a CPU is disabled and before rebooting, so the state of
802 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
803 * leftovers during boot.
804 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805void clear_local_APIC(void)
806{
Chuck Ebbert2584a822008-05-20 18:18:12 -0400807 int maxlvt;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100808 u32 v;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809
Andi Kleend3432892008-01-30 13:33:17 +0100810 /* APIC hasn't been mapped yet */
811 if (!apic_phys)
812 return;
813
814 maxlvt = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815 /*
Siddha, Suresh B704fc592006-06-26 13:59:53 +0200816 * Masking an LVT entry can trigger a local APIC error
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817 * if the vector is zero. Mask LVTERR first to prevent this.
818 */
819 if (maxlvt >= 3) {
820 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
Andi Kleen11a8e772006-01-11 22:46:51 +0100821 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822 }
823 /*
824 * Careful: we have to set masks only first to deassert
825 * any level-triggered sources.
826 */
827 v = apic_read(APIC_LVTT);
Andi Kleen11a8e772006-01-11 22:46:51 +0100828 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 v = apic_read(APIC_LVT0);
Andi Kleen11a8e772006-01-11 22:46:51 +0100830 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831 v = apic_read(APIC_LVT1);
Andi Kleen11a8e772006-01-11 22:46:51 +0100832 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 if (maxlvt >= 4) {
834 v = apic_read(APIC_LVTPC);
Andi Kleen11a8e772006-01-11 22:46:51 +0100835 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836 }
837
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400838 /* lets not touch this if we didn't frob it */
Andi Kleen07db1c12009-02-12 13:39:35 +0100839#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400840 if (maxlvt >= 5) {
841 v = apic_read(APIC_LVTTHMR);
842 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
843 }
844#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 /*
846 * Clean APIC state for other OSs:
847 */
Andi Kleen11a8e772006-01-11 22:46:51 +0100848 apic_write(APIC_LVTT, APIC_LVT_MASKED);
849 apic_write(APIC_LVT0, APIC_LVT_MASKED);
850 apic_write(APIC_LVT1, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851 if (maxlvt >= 3)
Andi Kleen11a8e772006-01-11 22:46:51 +0100852 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 if (maxlvt >= 4)
Andi Kleen11a8e772006-01-11 22:46:51 +0100854 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400855
856 /* Integrated APIC (!82489DX) ? */
857 if (lapic_is_integrated()) {
858 if (maxlvt > 3)
859 /* Clear ESR due to Pentium errata 3AP and 11AP */
860 apic_write(APIC_ESR, 0);
861 apic_read(APIC_ESR);
862 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863}
864
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100865/**
866 * disable_local_APIC - clear and disable the local APIC
867 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700868void disable_local_APIC(void)
869{
870 unsigned int value;
871
Jan Beulich4a13ad02009-01-14 12:28:51 +0000872 /* APIC hasn't been mapped yet */
873 if (!apic_phys)
874 return;
875
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 clear_local_APIC();
877
878 /*
879 * Disable APIC (implies clearing of registers
880 * for 82489DX!).
881 */
882 value = apic_read(APIC_SPIV);
883 value &= ~APIC_SPIV_APIC_ENABLED;
Andi Kleen11a8e772006-01-11 22:46:51 +0100884 apic_write(APIC_SPIV, value);
Cyrill Gorcunov990b1832008-08-18 20:45:51 +0400885
886#ifdef CONFIG_X86_32
887 /*
888 * When LAPIC was disabled by the BIOS and enabled by the kernel,
889 * restore the disabled state.
890 */
891 if (enabled_via_apicbase) {
892 unsigned int l, h;
893
894 rdmsr(MSR_IA32_APICBASE, l, h);
895 l &= ~MSR_IA32_APICBASE_ENABLE;
896 wrmsr(MSR_IA32_APICBASE, l, h);
897 }
898#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899}
900
Cyrill Gorcunovfe4024d2008-08-18 20:45:52 +0400901/*
902 * If Linux enabled the LAPIC against the BIOS default disable it down before
903 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
904 * not power-off. Additionally clear all LVT entries before disable_local_APIC
905 * for the case where Linux didn't enable the LAPIC.
906 */
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -0700907void lapic_shutdown(void)
908{
909 unsigned long flags;
910
911 if (!cpu_has_apic)
912 return;
913
914 local_irq_save(flags);
915
Cyrill Gorcunovfe4024d2008-08-18 20:45:52 +0400916#ifdef CONFIG_X86_32
917 if (!enabled_via_apicbase)
918 clear_local_APIC();
919 else
920#endif
921 disable_local_APIC();
922
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -0700923
924 local_irq_restore(flags);
925}
926
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927/*
928 * This is to verify that we're looking at a real local APIC.
929 * Check these against your board if the CPUs aren't getting
930 * started for no apparent reason.
931 */
932int __init verify_local_APIC(void)
933{
934 unsigned int reg0, reg1;
935
936 /*
937 * The version register is read-only in a real APIC.
938 */
939 reg0 = apic_read(APIC_LVR);
940 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
941 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
942 reg1 = apic_read(APIC_LVR);
943 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
944
945 /*
946 * The two version reads above should print the same
947 * numbers. If the second one is different, then we
948 * poke at a non-APIC.
949 */
950 if (reg1 != reg0)
951 return 0;
952
953 /*
954 * Check if the version looks reasonably.
955 */
956 reg1 = GET_APIC_VERSION(reg0);
957 if (reg1 == 0x00 || reg1 == 0xff)
958 return 0;
Thomas Gleixner37e650c2008-01-30 13:30:14 +0100959 reg1 = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960 if (reg1 < 0x02 || reg1 == 0xff)
961 return 0;
962
963 /*
964 * The ID register is read/write in a real APIC.
965 */
Suresh Siddha2d7a66d2008-07-11 14:24:19 -0700966 reg0 = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
Ingo Molnar5b812722009-01-28 14:59:17 +0100968 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
Suresh Siddha2d7a66d2008-07-11 14:24:19 -0700969 reg1 = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700970 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
971 apic_write(APIC_ID, reg0);
Ingo Molnar5b812722009-01-28 14:59:17 +0100972 if (reg1 != (reg0 ^ apic->apic_id_mask))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973 return 0;
974
975 /*
976 * The next two are just to see if we have sane values.
977 * They're only really relevant if we're in Virtual Wire
978 * compatibility mode, but most boxes are anymore.
979 */
980 reg0 = apic_read(APIC_LVT0);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100981 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 reg1 = apic_read(APIC_LVT1);
983 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
984
985 return 1;
986}
987
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100988/**
989 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
990 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991void __init sync_Arb_IDs(void)
992{
Cyrill Gorcunov296cb952008-08-15 13:51:23 +0200993 /*
994 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
995 * needed on AMD.
996 */
997 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998 return;
999
1000 /*
1001 * Wait for idle.
1002 */
1003 apic_wait_icr_idle();
1004
1005 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
Cyrill Gorcunov6f6da972008-08-15 23:05:19 +04001006 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1007 APIC_INT_LEVELTRIG | APIC_DM_INIT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008}
1009
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010/*
1011 * An initial setup of the virtual wire mode.
1012 */
1013void __init init_bsp_APIC(void)
1014{
Andi Kleen11a8e772006-01-11 22:46:51 +01001015 unsigned int value;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016
1017 /*
1018 * Don't do the setup now if we have a SMP BIOS as the
1019 * through-I/O-APIC virtual wire mode might be active.
1020 */
1021 if (smp_found_config || !cpu_has_apic)
1022 return;
1023
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 /*
1025 * Do not trust the local APIC being empty at bootup.
1026 */
1027 clear_local_APIC();
1028
1029 /*
1030 * Enable APIC.
1031 */
1032 value = apic_read(APIC_SPIV);
1033 value &= ~APIC_VECTOR_MASK;
1034 value |= APIC_SPIV_APIC_ENABLED;
Cyrill Gorcunov638c0412008-08-15 23:05:18 +04001035
1036#ifdef CONFIG_X86_32
1037 /* This bit is reserved on P4/Xeon and should be cleared */
1038 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1039 (boot_cpu_data.x86 == 15))
1040 value &= ~APIC_SPIV_FOCUS_DISABLED;
1041 else
1042#endif
1043 value |= APIC_SPIV_FOCUS_DISABLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +01001045 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046
1047 /*
1048 * Set up the virtual wire mode.
1049 */
Andi Kleen11a8e772006-01-11 22:46:51 +01001050 apic_write(APIC_LVT0, APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051 value = APIC_DM_NMI;
Cyrill Gorcunov638c0412008-08-15 23:05:18 +04001052 if (!lapic_is_integrated()) /* 82489DX */
1053 value |= APIC_LVT_LEVEL_TRIGGER;
Andi Kleen11a8e772006-01-11 22:46:51 +01001054 apic_write(APIC_LVT1, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055}
1056
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001057static void __cpuinit lapic_setup_esr(void)
1058{
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001059 unsigned int oldvalue, value, maxlvt;
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001060
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001061 if (!lapic_is_integrated()) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001062 pr_info("No ESR for 82489DX.\n");
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001063 return;
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001064 }
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001065
Ingo Molnar08125d32009-01-28 05:08:44 +01001066 if (apic->disable_esr) {
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001067 /*
1068 * Something untraceable is creating bad interrupts on
1069 * secondary quads ... for the moment, just leave the
1070 * ESR disabled - we can't do anything useful with the
1071 * errors anyway - mbligh
1072 */
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001073 pr_info("Leaving ESR disabled.\n");
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001074 return;
1075 }
1076
1077 maxlvt = lapic_get_maxlvt();
1078 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1079 apic_write(APIC_ESR, 0);
1080 oldvalue = apic_read(APIC_ESR);
1081
1082 /* enables sending errors */
1083 value = ERROR_APIC_VECTOR;
1084 apic_write(APIC_LVTERR, value);
1085
1086 /*
1087 * spec says clear errors after enabling vector.
1088 */
1089 if (maxlvt > 3)
1090 apic_write(APIC_ESR, 0);
1091 value = apic_read(APIC_ESR);
1092 if (value != oldvalue)
1093 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1094 "vector: 0x%08x after: 0x%08x\n",
1095 oldvalue, value);
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001096}
1097
1098
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001099/**
1100 * setup_local_APIC - setup the local APIC
1101 */
1102void __cpuinit setup_local_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103{
Andi Kleen739f33b2008-01-30 13:30:40 +01001104 unsigned int value;
Vivek Goyalda7ed9f2006-03-25 16:31:16 +01001105 int i, j;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106
Jan Beulichf1182632009-01-14 12:27:35 +00001107 if (disable_apic) {
Ingo Molnar65a4e572009-01-31 03:36:17 +01001108 arch_disable_smp_support();
Jan Beulichf1182632009-01-14 12:27:35 +00001109 return;
1110 }
1111
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001112#ifdef CONFIG_X86_32
1113 /* Pound the ESR really hard over the head with a big hammer - mbligh */
Ingo Molnar08125d32009-01-28 05:08:44 +01001114 if (lapic_is_integrated() && apic->disable_esr) {
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001115 apic_write(APIC_ESR, 0);
1116 apic_write(APIC_ESR, 0);
1117 apic_write(APIC_ESR, 0);
1118 apic_write(APIC_ESR, 0);
1119 }
1120#endif
1121
Jack Steinerac23d4e2008-03-28 14:12:16 -05001122 preempt_disable();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124 /*
1125 * Double-check whether this APIC is really registered.
1126 * This is meaningless in clustered apic mode, so we skip it.
1127 */
Ingo Molnar7ed248d2009-01-28 03:43:47 +01001128 if (!apic->apic_id_registered())
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129 BUG();
1130
1131 /*
1132 * Intel recommends to set DFR, LDR and TPR before enabling
1133 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1134 * document number 292116). So here it goes...
1135 */
Ingo Molnara5c43292009-01-28 06:50:47 +01001136 apic->init_apic_ldr();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137
1138 /*
1139 * Set Task Priority to 'accept all'. We never change this
1140 * later on.
1141 */
1142 value = apic_read(APIC_TASKPRI);
1143 value &= ~APIC_TPRI_MASK;
Andi Kleen11a8e772006-01-11 22:46:51 +01001144 apic_write(APIC_TASKPRI, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145
1146 /*
Vivek Goyalda7ed9f2006-03-25 16:31:16 +01001147 * After a crash, we no longer service the interrupts and a pending
1148 * interrupt from previous kernel might still have ISR bit set.
1149 *
1150 * Most probably by now CPU has serviced that pending interrupt and
1151 * it might not have done the ack_APIC_irq() because it thought,
1152 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1153 * does not clear the ISR bit and cpu thinks it has already serivced
1154 * the interrupt. Hence a vector might get locked. It was noticed
1155 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1156 */
1157 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1158 value = apic_read(APIC_ISR + i*0x10);
1159 for (j = 31; j >= 0; j--) {
1160 if (value & (1<<j))
1161 ack_APIC_irq();
1162 }
1163 }
1164
1165 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166 * Now that we are all set up, enable the APIC
1167 */
1168 value = apic_read(APIC_SPIV);
1169 value &= ~APIC_VECTOR_MASK;
1170 /*
1171 * Enable APIC
1172 */
1173 value |= APIC_SPIV_APIC_ENABLED;
1174
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001175#ifdef CONFIG_X86_32
1176 /*
1177 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1178 * certain networking cards. If high frequency interrupts are
1179 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1180 * entry is masked/unmasked at a high rate as well then sooner or
1181 * later IOAPIC line gets 'stuck', no more interrupts are received
1182 * from the device. If focus CPU is disabled then the hang goes
1183 * away, oh well :-(
1184 *
1185 * [ This bug can be reproduced easily with a level-triggered
1186 * PCI Ne2000 networking cards and PII/PIII processors, dual
1187 * BX chipset. ]
1188 */
1189 /*
1190 * Actually disabling the focus CPU check just makes the hang less
1191 * frequent as it makes the interrupt distributon model be more
1192 * like LRU than MRU (the short-term load is more even across CPUs).
1193 * See also the comment in end_level_ioapic_irq(). --macro
1194 */
1195
1196 /*
1197 * - enable focus processor (bit==0)
1198 * - 64bit mode always use processor focus
1199 * so no need to set it
1200 */
1201 value &= ~APIC_SPIV_FOCUS_DISABLED;
1202#endif
Andi Kleen3f14c742006-09-26 10:52:29 +02001203
Linus Torvalds1da177e2005-04-16 15:20:36 -07001204 /*
1205 * Set spurious IRQ vector
1206 */
1207 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +01001208 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209
1210 /*
1211 * Set up LVT0, LVT1:
1212 *
1213 * set up through-local-APIC on the BP's LINT0. This is not
1214 * strictly necessary in pure symmetric-IO mode, but sometimes
1215 * we delegate interrupts to the 8259A.
1216 */
1217 /*
1218 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1219 */
1220 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001221 if (!smp_processor_id() && (pic_mode || !value)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222 value = APIC_DM_EXTINT;
Chris Wrightbc1d99c2007-10-12 23:04:23 +02001223 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001224 smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 } else {
1226 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
Chris Wrightbc1d99c2007-10-12 23:04:23 +02001227 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001228 smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229 }
Andi Kleen11a8e772006-01-11 22:46:51 +01001230 apic_write(APIC_LVT0, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231
1232 /*
1233 * only the BP should see the LINT1 NMI signal, obviously.
1234 */
1235 if (!smp_processor_id())
1236 value = APIC_DM_NMI;
1237 else
1238 value = APIC_DM_NMI | APIC_LVT_MASKED;
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001239 if (!lapic_is_integrated()) /* 82489DX */
1240 value |= APIC_LVT_LEVEL_TRIGGER;
Andi Kleen11a8e772006-01-11 22:46:51 +01001241 apic_write(APIC_LVT1, value);
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001242
Jack Steinerac23d4e2008-03-28 14:12:16 -05001243 preempt_enable();
Andi Kleen739f33b2008-01-30 13:30:40 +01001244}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245
Andi Kleen739f33b2008-01-30 13:30:40 +01001246void __cpuinit end_local_APIC_setup(void)
1247{
1248 lapic_setup_esr();
Cyrill Gorcunovfa6b95f2008-08-18 20:45:58 +04001249
1250#ifdef CONFIG_X86_32
Cyrill Gorcunov1b4ee4e2008-08-18 23:12:33 +04001251 {
1252 unsigned int value;
1253 /* Disable the local apic timer */
1254 value = apic_read(APIC_LVTT);
1255 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1256 apic_write(APIC_LVTT, value);
1257 }
Cyrill Gorcunovfa6b95f2008-08-18 20:45:58 +04001258#endif
1259
Don Zickusf2802e72006-09-26 10:52:26 +02001260 setup_apic_nmi_watchdog(NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261 apic_pm_activate();
1262}
1263
Yinghai Lu06cd9a72009-02-16 17:29:58 -08001264#ifdef CONFIG_X86_X2APIC
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001265void check_x2apic(void)
1266{
Suresh Siddhaef1f87a2009-02-21 14:23:21 -08001267 if (x2apic_enabled()) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001268 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001269 x2apic_preenabled = x2apic = 1;
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001270 }
1271}
1272
1273void enable_x2apic(void)
1274{
1275 int msr, msr2;
1276
Yinghai Lu06cd9a72009-02-16 17:29:58 -08001277 if (!x2apic)
1278 return;
1279
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001280 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1281 if (!(msr & X2APIC_ENABLE)) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001282 pr_info("Enabling x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001283 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1284 }
1285}
1286
Al Viro2236d252008-11-22 17:37:34 +00001287void __init enable_IR_x2apic(void)
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001288{
1289#ifdef CONFIG_INTR_REMAP
1290 int ret;
1291 unsigned long flags;
1292
1293 if (!cpu_has_x2apic)
1294 return;
1295
1296 if (!x2apic_preenabled && disable_x2apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001297 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1298 "because of nox2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001299 return;
1300 }
1301
1302 if (x2apic_preenabled && disable_x2apic)
1303 panic("Bios already enabled x2apic, can't enforce nox2apic");
1304
1305 if (!x2apic_preenabled && skip_ioapic_setup) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001306 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1307 "because of skipping io-apic setup\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001308 return;
1309 }
1310
1311 ret = dmar_table_init();
1312 if (ret) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001313 pr_info("dmar_table_init() failed with %d:\n", ret);
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001314
1315 if (x2apic_preenabled)
1316 panic("x2apic enabled by bios. But IR enabling failed");
1317 else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001318 pr_info("Not enabling x2apic,Intr-remapping\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001319 return;
1320 }
1321
1322 local_irq_save(flags);
1323 mask_8259A();
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001324
1325 ret = save_mask_IO_APIC_setup();
1326 if (ret) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001327 pr_info("Saving IO-APIC state failed: %d\n", ret);
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001328 goto end;
1329 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001330
1331 ret = enable_intr_remapping(1);
1332
1333 if (ret && x2apic_preenabled) {
1334 local_irq_restore(flags);
1335 panic("x2apic enabled by bios. But IR enabling failed");
1336 }
1337
1338 if (ret)
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001339 goto end_restore;
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001340
1341 if (!x2apic) {
1342 x2apic = 1;
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001343 enable_x2apic();
1344 }
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001345
1346end_restore:
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001347 if (ret)
1348 /*
1349 * IR enabling failed
1350 */
1351 restore_IO_APIC_setup();
1352 else
1353 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1354
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001355end:
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001356 unmask_8259A();
1357 local_irq_restore(flags);
1358
1359 if (!ret) {
1360 if (!x2apic_preenabled)
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001361 pr_info("Enabled x2apic and interrupt-remapping\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001362 else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001363 pr_info("Enabled Interrupt-remapping\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001364 } else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001365 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001366#else
1367 if (!cpu_has_x2apic)
1368 return;
1369
1370 if (x2apic_preenabled)
1371 panic("x2apic enabled prior OS handover,"
1372 " enable CONFIG_INTR_REMAP");
1373
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001374 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1375 " and x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001376#endif
1377
1378 return;
1379}
Yinghai Lu06cd9a72009-02-16 17:29:58 -08001380#endif /* CONFIG_X86_X2APIC */
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001381
Yinghai Lube7a6562008-08-24 02:01:51 -07001382#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001383/*
1384 * Detect and enable local APICs on non-SMP boards.
1385 * Original code written by Keir Fraser.
1386 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1387 * not correctly set up (usually the APIC timer won't work etc.)
1388 */
1389static int __init detect_init_APIC(void)
1390{
1391 if (!cpu_has_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001392 pr_info("No local APIC present\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001393 return -1;
1394 }
1395
1396 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
Glauber de Oliveira Costac70dcb72008-03-19 14:25:58 -03001397 boot_cpu_physical_apicid = 0;
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001398 return 0;
1399}
Yinghai Lube7a6562008-08-24 02:01:51 -07001400#else
1401/*
1402 * Detect and initialize APIC
1403 */
1404static int __init detect_init_APIC(void)
1405{
1406 u32 h, l, features;
1407
1408 /* Disabled by kernel option? */
1409 if (disable_apic)
1410 return -1;
1411
1412 switch (boot_cpu_data.x86_vendor) {
1413 case X86_VENDOR_AMD:
1414 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
Borislav Petkov85877062009-02-03 16:24:22 +01001415 (boot_cpu_data.x86 >= 15))
Yinghai Lube7a6562008-08-24 02:01:51 -07001416 break;
1417 goto no_apic;
1418 case X86_VENDOR_INTEL:
1419 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1420 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1421 break;
1422 goto no_apic;
1423 default:
1424 goto no_apic;
1425 }
1426
1427 if (!cpu_has_apic) {
1428 /*
1429 * Over-ride BIOS and try to enable the local APIC only if
1430 * "lapic" specified.
1431 */
1432 if (!force_enable_local_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001433 pr_info("Local APIC disabled by BIOS -- "
1434 "you can enable it with \"lapic\"\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001435 return -1;
1436 }
1437 /*
1438 * Some BIOSes disable the local APIC in the APIC_BASE
1439 * MSR. This can only be done in software for Intel P6 or later
1440 * and AMD K7 (Model > 1) or later.
1441 */
1442 rdmsr(MSR_IA32_APICBASE, l, h);
1443 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001444 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001445 l &= ~MSR_IA32_APICBASE_BASE;
1446 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1447 wrmsr(MSR_IA32_APICBASE, l, h);
1448 enabled_via_apicbase = 1;
1449 }
1450 }
1451 /*
1452 * The APIC feature bit should now be enabled
1453 * in `cpuid'
1454 */
1455 features = cpuid_edx(1);
1456 if (!(features & (1 << X86_FEATURE_APIC))) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001457 pr_warning("Could not enable APIC!\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001458 return -1;
1459 }
1460 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1461 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1462
1463 /* The BIOS may have set up the APIC at some other address */
1464 rdmsr(MSR_IA32_APICBASE, l, h);
1465 if (l & MSR_IA32_APICBASE_ENABLE)
1466 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1467
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001468 pr_info("Found and enabled local APIC!\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001469
1470 apic_pm_activate();
1471
1472 return 0;
1473
1474no_apic:
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001475 pr_info("No local APIC present or hardware disabled\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001476 return -1;
1477}
1478#endif
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001479
Yinghai Luf28c0ae2008-08-24 02:01:49 -07001480#ifdef CONFIG_X86_64
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001481void __init early_init_lapic_mapping(void)
1482{
Thomas Gleixner431ee792008-05-12 15:43:35 +02001483 unsigned long phys_addr;
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001484
1485 /*
1486 * If no local APIC can be found then go out
1487 * : it means there is no mpatable and MADT
1488 */
1489 if (!smp_found_config)
1490 return;
1491
Thomas Gleixner431ee792008-05-12 15:43:35 +02001492 phys_addr = mp_lapic_addr;
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001493
Thomas Gleixner431ee792008-05-12 15:43:35 +02001494 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001495 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
Thomas Gleixner431ee792008-05-12 15:43:35 +02001496 APIC_BASE, phys_addr);
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001497
1498 /*
1499 * Fetch the APIC ID of the BSP in case we have a
1500 * default configuration (or the MP table is broken).
1501 */
Yinghai Lu4c9961d2008-07-11 18:44:16 -07001502 boot_cpu_physical_apicid = read_apic_id();
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001503}
Yinghai Luf28c0ae2008-08-24 02:01:49 -07001504#endif
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001505
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001506/**
1507 * init_apic_mappings - initialize APIC mappings
1508 */
1509void __init init_apic_mappings(void)
1510{
Yinghai Lu06cd9a72009-02-16 17:29:58 -08001511#ifdef CONFIG_X86_X2APIC
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001512 if (x2apic) {
Yinghai Lu4c9961d2008-07-11 18:44:16 -07001513 boot_cpu_physical_apicid = read_apic_id();
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001514 return;
1515 }
Yinghai Lu49899ea2008-08-24 02:01:47 -07001516#endif
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001517
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001518 /*
1519 * If no local APIC can be found then set up a fake all
1520 * zeroes page to simulate the local APIC and another
1521 * one for the IO-APIC.
1522 */
1523 if (!smp_found_config && detect_init_APIC()) {
1524 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1525 apic_phys = __pa(apic_phys);
1526 } else
1527 apic_phys = mp_lapic_addr;
1528
1529 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
Yinghai Lu79c09692008-09-07 17:58:57 -07001530 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001531 APIC_BASE, apic_phys);
1532
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001533 /*
1534 * Fetch the APIC ID of the BSP in case we have a
1535 * default configuration (or the MP table is broken).
1536 */
Yinghai Luf28c0ae2008-08-24 02:01:49 -07001537 if (boot_cpu_physical_apicid == -1U)
1538 boot_cpu_physical_apicid = read_apic_id();
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001539}
1540
1541/*
1542 * This initializes the IO-APIC and APIC hardware if this is
1543 * a UP kernel.
1544 */
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001545int apic_version[MAX_APICS];
1546
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001547int __init APIC_init_uniprocessor(void)
1548{
1549 if (disable_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001550 pr_info("Apic disabled\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001551 return -1;
1552 }
Jan Beulichf1182632009-01-14 12:27:35 +00001553#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001554 if (!cpu_has_apic) {
1555 disable_apic = 1;
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001556 pr_info("Apic disabled by BIOS\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001557 return -1;
1558 }
Yinghai Lufa2bd352008-08-24 02:01:50 -07001559#else
1560 if (!smp_found_config && !cpu_has_apic)
1561 return -1;
1562
1563 /*
1564 * Complain if the BIOS pretends there is one.
1565 */
1566 if (!cpu_has_apic &&
1567 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001568 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1569 boot_cpu_physical_apicid);
Yinghai Lufa2bd352008-08-24 02:01:50 -07001570 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1571 return -1;
1572 }
1573#endif
1574
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001575 enable_IR_x2apic();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001576#ifdef CONFIG_X86_64
Ingo Molnar72ce0162009-01-28 06:50:47 +01001577 default_setup_apic_routing();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001578#endif
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001579
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001580 verify_local_APIC();
Glauber Costab5841762008-05-28 13:38:28 -03001581 connect_bsp_APIC();
1582
Yinghai Lufa2bd352008-08-24 02:01:50 -07001583#ifdef CONFIG_X86_64
Glauber de Oliveira Costac70dcb72008-03-19 14:25:58 -03001584 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
Yinghai Lufa2bd352008-08-24 02:01:50 -07001585#else
1586 /*
1587 * Hack: In case of kdump, after a crash, kernel might be booting
1588 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1589 * might be zero if read from MP tables. Get it from LAPIC.
1590 */
1591# ifdef CONFIG_CRASH_DUMP
1592 boot_cpu_physical_apicid = read_apic_id();
1593# endif
1594#endif
1595 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001596 setup_local_APIC();
1597
Yinghai Lu88d0f552009-02-14 23:57:28 -08001598#ifdef CONFIG_X86_IO_APIC
Andi Kleen739f33b2008-01-30 13:30:40 +01001599 /*
1600 * Now enable IO-APICs, actually call clear_IO_APIC
Yinghai Lu98c061b2009-02-16 00:00:50 -08001601 * We need clear_IO_APIC before enabling error vector
Andi Kleen739f33b2008-01-30 13:30:40 +01001602 */
1603 if (!skip_ioapic_setup && nr_ioapics)
1604 enable_IO_APIC();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001605#endif
Andi Kleen739f33b2008-01-30 13:30:40 +01001606
1607 end_local_APIC_setup();
1608
Yinghai Lufa2bd352008-08-24 02:01:50 -07001609#ifdef CONFIG_X86_IO_APIC
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001610 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1611 setup_IO_APIC();
Yinghai Lu98c061b2009-02-16 00:00:50 -08001612 else {
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001613 nr_ioapics = 0;
Yinghai Lu98c061b2009-02-16 00:00:50 -08001614 localise_nmi_watchdog();
1615 }
1616#else
1617 localise_nmi_watchdog();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001618#endif
1619
Yinghai Lufa2bd352008-08-24 02:01:50 -07001620 setup_boot_clock();
Yinghai Lu98c061b2009-02-16 00:00:50 -08001621#ifdef CONFIG_X86_64
1622 check_nmi_watchdog();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001623#endif
1624
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001625 return 0;
1626}
1627
1628/*
1629 * Local APIC interrupts
1630 */
1631
1632/*
1633 * This interrupt should _never_ happen with our APIC/SMP architecture
1634 */
Yinghai Ludc1528d2008-08-24 02:01:53 -07001635void smp_spurious_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001636{
Yinghai Ludc1528d2008-08-24 02:01:53 -07001637 u32 v;
1638
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001639 exit_idle();
1640 irq_enter();
1641 /*
1642 * Check if this really is a spurious interrupt and ACK it
1643 * if it is a vectored one. Just in case...
1644 * Spurious interrupts should not be ACKed.
1645 */
1646 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1647 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1648 ack_APIC_irq();
1649
Hiroshi Shimamoto915b0d02008-12-08 19:19:26 -08001650 inc_irq_stat(irq_spurious_count);
1651
Yinghai Ludc1528d2008-08-24 02:01:53 -07001652 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001653 pr_info("spurious APIC interrupt on CPU#%d, "
1654 "should never happen.\n", smp_processor_id());
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001655 irq_exit();
1656}
1657
1658/*
1659 * This interrupt should never happen with our APIC/SMP architecture
1660 */
Yinghai Ludc1528d2008-08-24 02:01:53 -07001661void smp_error_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001662{
Yinghai Ludc1528d2008-08-24 02:01:53 -07001663 u32 v, v1;
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001664
1665 exit_idle();
1666 irq_enter();
1667 /* First tickle the hardware, only then report what went on. -- REW */
1668 v = apic_read(APIC_ESR);
1669 apic_write(APIC_ESR, 0);
1670 v1 = apic_read(APIC_ESR);
1671 ack_APIC_irq();
1672 atomic_inc(&irq_err_count);
1673
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001674 /*
1675 * Here is what the APIC error bits mean:
1676 * 0: Send CS error
1677 * 1: Receive CS error
1678 * 2: Send accept error
1679 * 3: Receive accept error
1680 * 4: Reserved
1681 * 5: Send illegal vector
1682 * 6: Received illegal vector
1683 * 7: Illegal register address
1684 */
1685 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001686 smp_processor_id(), v , v1);
1687 irq_exit();
1688}
1689
Glauber Costab5841762008-05-28 13:38:28 -03001690/**
Cyrill Gorcunov36c9d672008-08-18 20:45:53 +04001691 * connect_bsp_APIC - attach the APIC to the interrupt system
1692 */
Glauber Costab5841762008-05-28 13:38:28 -03001693void __init connect_bsp_APIC(void)
1694{
Cyrill Gorcunov36c9d672008-08-18 20:45:53 +04001695#ifdef CONFIG_X86_32
1696 if (pic_mode) {
1697 /*
1698 * Do not trust the local APIC being empty at bootup.
1699 */
1700 clear_local_APIC();
1701 /*
1702 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1703 * local APIC to INT and NMI lines.
1704 */
1705 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1706 "enabling APIC mode.\n");
1707 outb(0x70, 0x22);
1708 outb(0x01, 0x23);
1709 }
1710#endif
Ingo Molnar49040332009-01-28 12:43:18 +01001711 if (apic->enable_apic_mode)
1712 apic->enable_apic_mode();
Glauber Costab5841762008-05-28 13:38:28 -03001713}
1714
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04001715/**
1716 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1717 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1718 *
1719 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1720 * APIC is disabled.
1721 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001722void disconnect_bsp_APIC(int virt_wire_setup)
1723{
Cyrill Gorcunov1b4ee4e2008-08-18 23:12:33 +04001724 unsigned int value;
1725
Cyrill Gorcunovc177b0b2008-08-18 20:45:56 +04001726#ifdef CONFIG_X86_32
1727 if (pic_mode) {
1728 /*
1729 * Put the board back into PIC mode (has an effect only on
1730 * certain older boards). Note that APIC interrupts, including
1731 * IPIs, won't work beyond this point! The only exception are
1732 * INIT IPIs.
1733 */
1734 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1735 "entering PIC mode.\n");
1736 outb(0x70, 0x22);
1737 outb(0x00, 0x23);
1738 return;
1739 }
1740#endif
1741
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001742 /* Go back to Virtual Wire compatibility mode */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001743
1744 /* For the spurious interrupt use vector F, and enable it */
1745 value = apic_read(APIC_SPIV);
1746 value &= ~APIC_VECTOR_MASK;
1747 value |= APIC_SPIV_APIC_ENABLED;
1748 value |= 0xf;
1749 apic_write(APIC_SPIV, value);
1750
1751 if (!virt_wire_setup) {
1752 /*
1753 * For LVT0 make it edge triggered, active high,
1754 * external and enabled
1755 */
1756 value = apic_read(APIC_LVT0);
1757 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1758 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1759 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1760 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1761 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1762 apic_write(APIC_LVT0, value);
1763 } else {
1764 /* Disable LVT0 */
1765 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1766 }
1767
Cyrill Gorcunovc177b0b2008-08-18 20:45:56 +04001768 /*
1769 * For LVT1 make it edge triggered, active high,
1770 * nmi and enabled
1771 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001772 value = apic_read(APIC_LVT1);
1773 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1774 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1775 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1776 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1777 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1778 apic_write(APIC_LVT1, value);
1779}
1780
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001781void __cpuinit generic_processor_info(int apicid, int version)
1782{
1783 int cpu;
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001784
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001785 /*
1786 * Validate version
1787 */
1788 if (version == 0x0) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001789 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
Mike Travis3b11ce72008-12-17 15:21:39 -08001790 "fixing up to 0x10. (tell your hw vendor)\n",
1791 version);
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001792 version = 0x10;
1793 }
1794 apic_version[apicid] = version;
1795
Mike Travis3b11ce72008-12-17 15:21:39 -08001796 if (num_processors >= nr_cpu_ids) {
1797 int max = nr_cpu_ids;
1798 int thiscpu = max + disabled_cpus;
1799
1800 pr_warning(
1801 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1802 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1803
1804 disabled_cpus++;
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001805 return;
1806 }
1807
1808 num_processors++;
Mike Travis3b11ce72008-12-17 15:21:39 -08001809 cpu = cpumask_next_zero(-1, cpu_present_mask);
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001810
Mike Travisb2b815d2009-01-16 15:22:16 -08001811 if (version != apic_version[boot_cpu_physical_apicid])
1812 WARN_ONCE(1,
1813 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1814 apic_version[boot_cpu_physical_apicid], cpu, version);
1815
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001816 physid_set(apicid, phys_cpu_present_map);
1817 if (apicid == boot_cpu_physical_apicid) {
1818 /*
1819 * x86_bios_cpu_apicid is required to have processors listed
1820 * in same order as logical cpu numbers. Hence the first
1821 * entry is BSP, and so on.
1822 */
1823 cpu = 0;
1824 }
Yinghai Lue0da3362008-06-08 18:29:22 -07001825 if (apicid > max_physical_apicid)
1826 max_physical_apicid = apicid;
1827
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001828#ifdef CONFIG_X86_32
1829 /*
1830 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1831 * but we need to work other dependencies like SMP_SUSPEND etc
1832 * before this can be done without some confusion.
1833 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1834 * - Ashok Raj <ashok.raj@intel.com>
1835 */
1836 if (max_physical_apicid >= 8) {
1837 switch (boot_cpu_data.x86_vendor) {
1838 case X86_VENDOR_INTEL:
1839 if (!APIC_XAPIC(version)) {
1840 def_to_bigsmp = 0;
1841 break;
1842 }
1843 /* If P4 and above fall through */
1844 case X86_VENDOR_AMD:
1845 def_to_bigsmp = 1;
1846 }
1847 }
1848#endif
1849
Ingo Molnar3e5095d2009-01-27 17:07:08 +01001850#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
Tejun Heof10fcd42009-01-13 20:41:34 +09001851 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1852 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001853#endif
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001854
Mike Travis1de88cd2008-12-16 17:34:02 -08001855 set_cpu_possible(cpu, true);
1856 set_cpu_present(cpu, true);
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001857}
1858
Suresh Siddha0c81c742008-07-10 11:16:48 -07001859int hard_smp_processor_id(void)
1860{
1861 return read_apic_id();
1862}
Ingo Molnar1dcdd3d2009-01-28 17:55:37 +01001863
1864void default_init_apic_ldr(void)
1865{
1866 unsigned long val;
1867
1868 apic_write(APIC_DFR, APIC_DFR_VALUE);
1869 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1870 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1871 apic_write(APIC_LDR, val);
1872}
1873
1874#ifdef CONFIG_X86_32
1875int default_apicid_to_node(int logical_apicid)
1876{
1877#ifdef CONFIG_SMP
1878 return apicid_2_node[hard_smp_processor_id()];
1879#else
1880 return 0;
1881#endif
1882}
Yinghai Lu34919982008-08-24 02:01:48 -07001883#endif
Suresh Siddha0c81c742008-07-10 11:16:48 -07001884
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001885/*
1886 * Power management
1887 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001888#ifdef CONFIG_PM
1889
1890static struct {
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04001891 /*
1892 * 'active' is true if the local APIC was enabled by us and
1893 * not the BIOS; this signifies that we are also responsible
1894 * for disabling it before entering apm/acpi suspend
1895 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896 int active;
1897 /* r/w apic fields */
1898 unsigned int apic_id;
1899 unsigned int apic_taskpri;
1900 unsigned int apic_ldr;
1901 unsigned int apic_dfr;
1902 unsigned int apic_spiv;
1903 unsigned int apic_lvtt;
1904 unsigned int apic_lvtpc;
1905 unsigned int apic_lvt0;
1906 unsigned int apic_lvt1;
1907 unsigned int apic_lvterr;
1908 unsigned int apic_tmict;
1909 unsigned int apic_tdcr;
1910 unsigned int apic_thmr;
1911} apic_pm_state;
1912
Pavel Machek0b9c33a2005-04-16 15:25:31 -07001913static int lapic_suspend(struct sys_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001914{
1915 unsigned long flags;
Karsten Wiesef990fff2006-12-07 02:14:11 +01001916 int maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917
1918 if (!apic_pm_state.active)
1919 return 0;
1920
Thomas Gleixner37e650c2008-01-30 13:30:14 +01001921 maxlvt = lapic_get_maxlvt();
Karsten Wiesef990fff2006-12-07 02:14:11 +01001922
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07001923 apic_pm_state.apic_id = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001924 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1925 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1926 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1927 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1928 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
Karsten Wiesef990fff2006-12-07 02:14:11 +01001929 if (maxlvt >= 4)
1930 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001931 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1932 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1933 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1934 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1935 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
Cyrill Gorcunov24968cf2008-08-16 23:21:52 +04001936#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
Karsten Wiesef990fff2006-12-07 02:14:11 +01001937 if (maxlvt >= 5)
1938 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1939#endif
Cyrill Gorcunov24968cf2008-08-16 23:21:52 +04001940
Fernando Luis Vázquez Cao2b94ab22006-09-26 10:52:33 +02001941 local_irq_save(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001942 disable_local_APIC();
1943 local_irq_restore(flags);
1944 return 0;
1945}
1946
1947static int lapic_resume(struct sys_device *dev)
1948{
1949 unsigned int l, h;
1950 unsigned long flags;
Karsten Wiesef990fff2006-12-07 02:14:11 +01001951 int maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001952
1953 if (!apic_pm_state.active)
1954 return 0;
1955
Thomas Gleixner37e650c2008-01-30 13:30:14 +01001956 maxlvt = lapic_get_maxlvt();
Karsten Wiesef990fff2006-12-07 02:14:11 +01001957
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958 local_irq_save(flags);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04001959
Yinghai Lu06cd9a72009-02-16 17:29:58 -08001960#ifdef CONFIG_X86_X2APIC
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04001961 if (x2apic)
1962 enable_x2apic();
1963 else
1964#endif
Yinghai Lud5e629a2008-08-17 21:12:27 -07001965 {
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04001966 /*
1967 * Make sure the APICBASE points to the right address
1968 *
1969 * FIXME! This will be wrong if we ever support suspend on
1970 * SMP! We'll need to do this as part of the CPU restore!
1971 */
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001972 rdmsr(MSR_IA32_APICBASE, l, h);
1973 l &= ~MSR_IA32_APICBASE_BASE;
1974 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1975 wrmsr(MSR_IA32_APICBASE, l, h);
Yinghai Lud5e629a2008-08-17 21:12:27 -07001976 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001977
Linus Torvalds1da177e2005-04-16 15:20:36 -07001978 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1979 apic_write(APIC_ID, apic_pm_state.apic_id);
1980 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1981 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1982 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1983 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1984 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1985 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04001986#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
Karsten Wiesef990fff2006-12-07 02:14:11 +01001987 if (maxlvt >= 5)
1988 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1989#endif
1990 if (maxlvt >= 4)
1991 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001992 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1993 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1994 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1995 apic_write(APIC_ESR, 0);
1996 apic_read(APIC_ESR);
1997 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1998 apic_write(APIC_ESR, 0);
1999 apic_read(APIC_ESR);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002001 local_irq_restore(flags);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002002
Linus Torvalds1da177e2005-04-16 15:20:36 -07002003 return 0;
2004}
2005
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04002006/*
2007 * This device has no shutdown method - fully functioning local APICs
2008 * are needed on every CPU up until machine_halt/restart/poweroff.
2009 */
2010
Linus Torvalds1da177e2005-04-16 15:20:36 -07002011static struct sysdev_class lapic_sysclass = {
Kay Sieversaf5ca3f2007-12-20 02:09:39 +01002012 .name = "lapic",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002013 .resume = lapic_resume,
2014 .suspend = lapic_suspend,
2015};
2016
2017static struct sys_device device_lapic = {
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002018 .id = 0,
2019 .cls = &lapic_sysclass,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002020};
2021
Ashok Raje6982c62005-06-25 14:54:58 -07002022static void __cpuinit apic_pm_activate(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002023{
2024 apic_pm_state.active = 1;
2025}
2026
2027static int __init init_lapic_sysfs(void)
2028{
2029 int error;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002030
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031 if (!cpu_has_apic)
2032 return 0;
2033 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002034
Linus Torvalds1da177e2005-04-16 15:20:36 -07002035 error = sysdev_class_register(&lapic_sysclass);
2036 if (!error)
2037 error = sysdev_register(&device_lapic);
2038 return error;
2039}
2040device_initcall(init_lapic_sysfs);
2041
2042#else /* CONFIG_PM */
2043
2044static void apic_pm_activate(void) { }
2045
2046#endif /* CONFIG_PM */
2047
Yinghai Luf28c0ae2008-08-24 02:01:49 -07002048#ifdef CONFIG_X86_64
Linus Torvalds1da177e2005-04-16 15:20:36 -07002049/*
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02002050 * apic_is_clustered_box() -- Check if we can expect good TSC
Linus Torvalds1da177e2005-04-16 15:20:36 -07002051 *
2052 * Thus far, the major user of this is IBM's Summit2 series:
2053 *
Linus Torvalds637029c2006-02-27 20:41:56 -08002054 * Clustered boxes may have unsynced TSC problems if they are
Linus Torvalds1da177e2005-04-16 15:20:36 -07002055 * multi-chassis. Use available data to take a good guess.
2056 * If in doubt, go HPET.
2057 */
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02002058__cpuinit int apic_is_clustered_box(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002059{
2060 int i, clusters, zeros;
2061 unsigned id;
Yinghai Lu322850a2008-02-23 21:48:42 -08002062 u16 *bios_cpu_apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002063 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2064
Yinghai Lu322850a2008-02-23 21:48:42 -08002065 /*
2066 * there is not this kind of box with AMD CPU yet.
2067 * Some AMD box with quadcore cpu and 8 sockets apicid
2068 * will be [4, 0x23] or [8, 0x27] could be thought to
Yinghai Luf8fffa42008-02-24 21:36:28 -08002069 * vsmp box still need checking...
Yinghai Lu322850a2008-02-23 21:48:42 -08002070 */
Ravikiran G Thirumalai1cb68482008-03-20 00:45:08 -07002071 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
Yinghai Lu322850a2008-02-23 21:48:42 -08002072 return 0;
2073
Mike Travis23ca4bb2008-05-12 21:21:12 +02002074 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
Suresh Siddha376ec332005-05-16 21:53:32 -07002075 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002076
Mike Travis168ef542008-12-16 17:34:01 -08002077 for (i = 0; i < nr_cpu_ids; i++) {
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002078 /* are we being called early in kernel startup? */
Mike Travis693e3c52008-01-30 13:33:14 +01002079 if (bios_cpu_apicid) {
2080 id = bios_cpu_apicid[i];
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +05302081 } else if (i < nr_cpu_ids) {
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002082 if (cpu_present(i))
2083 id = per_cpu(x86_bios_cpu_apicid, i);
2084 else
2085 continue;
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +05302086 } else
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002087 break;
2088
Linus Torvalds1da177e2005-04-16 15:20:36 -07002089 if (id != BAD_APICID)
2090 __set_bit(APIC_CLUSTERID(id), clustermap);
2091 }
2092
2093 /* Problem: Partially populated chassis may not have CPUs in some of
2094 * the APIC clusters they have been allocated. Only present CPUs have
travis@sgi.com602a54a2008-01-30 13:33:21 +01002095 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2096 * Since clusters are allocated sequentially, count zeros only if
2097 * they are bounded by ones.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002098 */
2099 clusters = 0;
2100 zeros = 0;
2101 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2102 if (test_bit(i, clustermap)) {
2103 clusters += 1 + zeros;
2104 zeros = 0;
2105 } else
2106 ++zeros;
2107 }
2108
Ravikiran G Thirumalai1cb68482008-03-20 00:45:08 -07002109 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2110 * not guaranteed to be synced between boards
2111 */
2112 if (is_vsmp_box() && clusters > 1)
2113 return 1;
2114
Linus Torvalds1da177e2005-04-16 15:20:36 -07002115 /*
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02002116 * If clusters > 2, then should be multi-chassis.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002117 * May have to revisit this when multi-core + hyperthreaded CPUs come
2118 * out, but AFAIK this will work even for them.
2119 */
2120 return (clusters > 2);
2121}
Yinghai Luf28c0ae2008-08-24 02:01:49 -07002122#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002123
2124/*
Thomas Gleixner0e078e22008-01-30 13:30:20 +01002125 * APIC command line parameters
Linus Torvalds1da177e2005-04-16 15:20:36 -07002126 */
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002127static int __init setup_disableapic(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002128{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002129 disable_apic = 1;
Yinghai Lu9175fc02008-07-21 01:38:14 -07002130 setup_clear_cpu_cap(X86_FEATURE_APIC);
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002131 return 0;
2132}
2133early_param("disableapic", setup_disableapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002134
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002135/* same as disableapic, for compatibility */
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002136static int __init setup_nolapic(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002137{
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002138 return setup_disableapic(arg);
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002139}
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002140early_param("nolapic", setup_nolapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002141
Linus Torvalds2e7c2832007-03-23 11:32:31 -07002142static int __init parse_lapic_timer_c2_ok(char *arg)
2143{
2144 local_apic_timer_c2_ok = 1;
2145 return 0;
2146}
2147early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2148
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002149static int __init parse_disable_apic_timer(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002150{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002151 disable_apic_timer = 1;
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002152 return 0;
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002153}
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002154early_param("noapictimer", parse_disable_apic_timer);
2155
2156static int __init parse_nolapic_timer(char *arg)
2157{
2158 disable_apic_timer = 1;
2159 return 0;
2160}
2161early_param("nolapic_timer", parse_nolapic_timer);
Andi Kleen73dea472006-02-03 21:50:50 +01002162
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002163static int __init apic_set_verbosity(char *arg)
2164{
2165 if (!arg) {
2166#ifdef CONFIG_X86_64
2167 skip_ioapic_setup = 0;
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002168 return 0;
2169#endif
2170 return -EINVAL;
2171 }
2172
2173 if (strcmp("debug", arg) == 0)
2174 apic_verbosity = APIC_DEBUG;
2175 else if (strcmp("verbose", arg) == 0)
2176 apic_verbosity = APIC_VERBOSE;
2177 else {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01002178 pr_warning("APIC Verbosity level %s not recognised"
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002179 " use apic=verbose or apic=debug\n", arg);
2180 return -EINVAL;
2181 }
2182
2183 return 0;
2184}
2185early_param("apic", apic_set_verbosity);
2186
Yinghai Lu1e934dd2008-02-22 13:37:26 -08002187static int __init lapic_insert_resource(void)
2188{
2189 if (!apic_phys)
2190 return -1;
2191
2192 /* Put local APIC into the resource map. */
2193 lapic_resource.start = apic_phys;
2194 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2195 insert_resource(&iomem_resource, &lapic_resource);
2196
2197 return 0;
2198}
2199
2200/*
2201 * need call insert after e820_reserve_resources()
2202 * that is using request_resource
2203 */
2204late_initcall(lapic_insert_resource);