blob: f147204e1e47e51b02a7cfcebb6e4051ce57453f [file] [log] [blame]
Michael Chanb6016b72005-05-26 13:03:09 -07001/* bnx2.c: Broadcom NX2 network driver.
2 *
Michael Chanfeebb332008-01-21 17:07:29 -08003 * Copyright (c) 2004-2008 Broadcom Corporation
Michael Chanb6016b72005-05-26 13:03:09 -07004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
Michael Chanf2a4f052006-03-23 01:13:12 -080012
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
Jiri Slaby1977f032007-10-18 23:40:25 -070029#include <linux/bitops.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080030#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
Michael Chanc86a31f2006-06-13 15:03:47 -070034#include <asm/page.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080035#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080038#include <linux/if_vlan.h>
David S. Miller08013fa2008-08-15 19:46:01 -070039#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
Michael Chanf2a4f052006-03-23 01:13:12 -080040#define BCM_VLAN 1
41#endif
Michael Chanf2a4f052006-03-23 01:13:12 -080042#include <net/ip.h>
Linus Torvaldsde081fa2007-07-12 16:40:08 -070043#include <net/tcp.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080044#include <net/checksum.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080045#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
Michael Chan29b12172006-03-23 01:13:43 -080048#include <linux/cache.h>
Michael Chanfba9fe92006-06-12 22:21:25 -070049#include <linux/zlib.h>
Benjamin Li706bf242008-07-18 17:55:11 -070050#include <linux/log2.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080051
Michael Chanb6016b72005-05-26 13:03:09 -070052#include "bnx2.h"
53#include "bnx2_fw.h"
Michael Chand43584c2006-11-19 14:14:35 -080054#include "bnx2_fw2.h"
Michael Chanb6016b72005-05-26 13:03:09 -070055
Michael Chan110d0ef2007-12-12 11:18:34 -080056#define FW_BUF_SIZE 0x10000
Denys Vlasenkob3448b02007-09-30 17:55:51 -070057
Michael Chanb6016b72005-05-26 13:03:09 -070058#define DRV_MODULE_NAME "bnx2"
59#define PFX DRV_MODULE_NAME ": "
Michael Chan0eb8b1f2008-08-14 15:30:31 -070060#define DRV_MODULE_VERSION "1.8.0"
61#define DRV_MODULE_RELDATE "Aug 14, 2008"
Michael Chanb6016b72005-05-26 13:03:09 -070062
63#define RUN_AT(x) (jiffies + (x))
64
65/* Time in jiffies before concluding the transmitter is hung. */
66#define TX_TIMEOUT (5*HZ)
67
Andrew Mortonfefa8642008-02-09 23:17:15 -080068static char version[] __devinitdata =
Michael Chanb6016b72005-05-26 13:03:09 -070069 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70
71MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
Benjamin Li453a9c62008-09-18 16:39:16 -070072MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
Michael Chanb6016b72005-05-26 13:03:09 -070073MODULE_LICENSE("GPL");
74MODULE_VERSION(DRV_MODULE_VERSION);
75
76static int disable_msi = 0;
77
78module_param(disable_msi, int, 0);
79MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
80
81typedef enum {
82 BCM5706 = 0,
83 NC370T,
84 NC370I,
85 BCM5706S,
86 NC370F,
Michael Chan5b0c76a2005-11-04 08:45:49 -080087 BCM5708,
88 BCM5708S,
Michael Chanbac0dff2006-11-19 14:15:05 -080089 BCM5709,
Michael Chan27a005b2007-05-03 13:23:41 -070090 BCM5709S,
Michael Chan7bb0a042008-07-14 22:37:47 -070091 BCM5716,
Michael Chanb6016b72005-05-26 13:03:09 -070092} board_t;
93
94/* indexed by board_t, above */
Andrew Mortonfefa8642008-02-09 23:17:15 -080095static struct {
Michael Chanb6016b72005-05-26 13:03:09 -070096 char *name;
97} board_info[] __devinitdata = {
98 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
99 { "HP NC370T Multifunction Gigabit Server Adapter" },
100 { "HP NC370i Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
102 { "HP NC370F Multifunction Gigabit Server Adapter" },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800103 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
Michael Chanbac0dff2006-11-19 14:15:05 -0800105 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
Michael Chan27a005b2007-05-03 13:23:41 -0700106 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
Michael Chan7bb0a042008-07-14 22:37:47 -0700107 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
Michael Chanb6016b72005-05-26 13:03:09 -0700108 };
109
Michael Chan7bb0a042008-07-14 22:37:47 -0700110static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
Michael Chanb6016b72005-05-26 13:03:09 -0700111 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
112 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
113 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
114 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
115 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
Michael Chanb6016b72005-05-26 13:03:09 -0700119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
120 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
Michael Chanbac0dff2006-11-19 14:15:05 -0800125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
Michael Chan27a005b2007-05-03 13:23:41 -0700127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
Michael Chan7bb0a042008-07-14 22:37:47 -0700129 { PCI_VENDOR_ID_BROADCOM, 0x163b,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
Michael Chanb6016b72005-05-26 13:03:09 -0700131 { 0, }
132};
133
134static struct flash_spec flash_table[] =
135{
Michael Chane30372c2007-07-16 18:26:23 -0700136#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
137#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
Michael Chanb6016b72005-05-26 13:03:09 -0700138 /* Slow EEPROM */
Michael Chan37137702005-11-04 08:49:17 -0800139 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700140 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700141 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
142 "EEPROM - slow"},
Michael Chan37137702005-11-04 08:49:17 -0800143 /* Expansion entry 0001 */
144 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700145 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800146 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
147 "Entry 0001"},
Michael Chanb6016b72005-05-26 13:03:09 -0700148 /* Saifun SA25F010 (non-buffered flash) */
149 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800150 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700151 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700152 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
153 "Non-buffered flash (128kB)"},
154 /* Saifun SA25F020 (non-buffered flash) */
155 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800156 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700158 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
159 "Non-buffered flash (256kB)"},
Michael Chan37137702005-11-04 08:49:17 -0800160 /* Expansion entry 0100 */
161 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700162 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800163 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
164 "Entry 0100"},
165 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400166 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
169 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
170 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
171 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700172 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800173 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
174 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
175 /* Saifun SA25F005 (non-buffered flash) */
176 /* strap, cfg1, & write1 need updates */
177 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800179 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
180 "Non-buffered flash (64kB)"},
181 /* Fast EEPROM */
182 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700183 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800184 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
185 "EEPROM - fast"},
186 /* Expansion entry 1001 */
187 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1001"},
191 /* Expansion entry 1010 */
192 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
195 "Entry 1010"},
196 /* ATMEL AT45DB011B (buffered flash) */
197 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700198 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800199 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
200 "Buffered flash (128kB)"},
201 /* Expansion entry 1100 */
202 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1100"},
206 /* Expansion entry 1101 */
207 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1101"},
211 /* Ateml Expansion entry 1110 */
212 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800214 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
215 "Entry 1110 (Atmel)"},
216 /* ATMEL AT45DB021B (buffered flash) */
217 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700218 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800219 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
220 "Buffered flash (256kB)"},
Michael Chanb6016b72005-05-26 13:03:09 -0700221};
222
Michael Chane30372c2007-07-16 18:26:23 -0700223static struct flash_spec flash_5709 = {
224 .flags = BNX2_NV_BUFFERED,
225 .page_bits = BCM5709_FLASH_PAGE_BITS,
226 .page_size = BCM5709_FLASH_PAGE_SIZE,
227 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
228 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
229 .name = "5709 Buffered flash (256kB)",
230};
231
Michael Chanb6016b72005-05-26 13:03:09 -0700232MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
233
Michael Chan35e90102008-06-19 16:37:42 -0700234static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
Michael Chane89bbf12005-08-25 15:36:58 -0700235{
Michael Chan2f8af122006-08-15 01:39:10 -0700236 u32 diff;
Michael Chane89bbf12005-08-25 15:36:58 -0700237
Michael Chan2f8af122006-08-15 01:39:10 -0700238 smp_mb();
Michael Chanfaac9c42006-12-14 15:56:32 -0800239
240 /* The ring uses 256 indices for 255 entries, one of them
241 * needs to be skipped.
242 */
Michael Chan35e90102008-06-19 16:37:42 -0700243 diff = txr->tx_prod - txr->tx_cons;
Michael Chanfaac9c42006-12-14 15:56:32 -0800244 if (unlikely(diff >= TX_DESC_CNT)) {
245 diff &= 0xffff;
246 if (diff == TX_DESC_CNT)
247 diff = MAX_TX_DESC_CNT;
248 }
Michael Chane89bbf12005-08-25 15:36:58 -0700249 return (bp->tx_ring_size - diff);
250}
251
Michael Chanb6016b72005-05-26 13:03:09 -0700252static u32
253bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
254{
Michael Chan1b8227c2007-05-03 13:24:05 -0700255 u32 val;
256
257 spin_lock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700258 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
Michael Chan1b8227c2007-05-03 13:24:05 -0700259 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
260 spin_unlock_bh(&bp->indirect_lock);
261 return val;
Michael Chanb6016b72005-05-26 13:03:09 -0700262}
263
264static void
265bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
266{
Michael Chan1b8227c2007-05-03 13:24:05 -0700267 spin_lock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700268 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
269 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
Michael Chan1b8227c2007-05-03 13:24:05 -0700270 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700271}
272
273static void
Michael Chan2726d6e2008-01-29 21:35:05 -0800274bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
275{
276 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
277}
278
279static u32
280bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
281{
282 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
283}
284
285static void
Michael Chanb6016b72005-05-26 13:03:09 -0700286bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
287{
288 offset += cid_addr;
Michael Chan1b8227c2007-05-03 13:24:05 -0700289 spin_lock_bh(&bp->indirect_lock);
Michael Chan59b47d82006-11-19 14:10:45 -0800290 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
291 int i;
292
293 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
294 REG_WR(bp, BNX2_CTX_CTX_CTRL,
295 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
296 for (i = 0; i < 5; i++) {
Michael Chan59b47d82006-11-19 14:10:45 -0800297 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
298 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
299 break;
300 udelay(5);
301 }
302 } else {
303 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
304 REG_WR(bp, BNX2_CTX_DATA, val);
305 }
Michael Chan1b8227c2007-05-03 13:24:05 -0700306 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700307}
308
309static int
310bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
311{
312 u32 val1;
313 int i, ret;
314
Michael Chan583c28e2008-01-21 19:51:35 -0800315 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700316 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
318
319 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
320 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
321
322 udelay(40);
323 }
324
325 val1 = (bp->phy_addr << 21) | (reg << 16) |
326 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
327 BNX2_EMAC_MDIO_COMM_START_BUSY;
328 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
329
330 for (i = 0; i < 50; i++) {
331 udelay(10);
332
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
335 udelay(5);
336
337 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
338 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
339
340 break;
341 }
342 }
343
344 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
345 *val = 0x0;
346 ret = -EBUSY;
347 }
348 else {
349 *val = val1;
350 ret = 0;
351 }
352
Michael Chan583c28e2008-01-21 19:51:35 -0800353 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700354 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
356
357 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
358 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
359
360 udelay(40);
361 }
362
363 return ret;
364}
365
366static int
367bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
368{
369 u32 val1;
370 int i, ret;
371
Michael Chan583c28e2008-01-21 19:51:35 -0800372 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700373 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
375
376 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
377 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
378
379 udelay(40);
380 }
381
382 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
383 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
384 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
385 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400386
Michael Chanb6016b72005-05-26 13:03:09 -0700387 for (i = 0; i < 50; i++) {
388 udelay(10);
389
390 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
391 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
392 udelay(5);
393 break;
394 }
395 }
396
397 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
398 ret = -EBUSY;
399 else
400 ret = 0;
401
Michael Chan583c28e2008-01-21 19:51:35 -0800402 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700403 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
405
406 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
407 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
408
409 udelay(40);
410 }
411
412 return ret;
413}
414
415static void
416bnx2_disable_int(struct bnx2 *bp)
417{
Michael Chanb4b36042007-12-20 19:59:30 -0800418 int i;
419 struct bnx2_napi *bnapi;
420
421 for (i = 0; i < bp->irq_nvecs; i++) {
422 bnapi = &bp->bnx2_napi[i];
423 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
424 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
425 }
Michael Chanb6016b72005-05-26 13:03:09 -0700426 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
427}
428
429static void
430bnx2_enable_int(struct bnx2 *bp)
431{
Michael Chanb4b36042007-12-20 19:59:30 -0800432 int i;
433 struct bnx2_napi *bnapi;
Michael Chan1269a8a2006-01-23 16:11:03 -0800434
Michael Chanb4b36042007-12-20 19:59:30 -0800435 for (i = 0; i < bp->irq_nvecs; i++) {
436 bnapi = &bp->bnx2_napi[i];
Michael Chan35efa7c2007-12-20 19:56:37 -0800437
Michael Chanb4b36042007-12-20 19:59:30 -0800438 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
439 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
440 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
441 bnapi->last_status_idx);
Michael Chanb6016b72005-05-26 13:03:09 -0700442
Michael Chanb4b36042007-12-20 19:59:30 -0800443 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
444 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
445 bnapi->last_status_idx);
446 }
Michael Chanbf5295b2006-03-23 01:11:56 -0800447 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -0700448}
449
450static void
451bnx2_disable_int_sync(struct bnx2 *bp)
452{
Michael Chanb4b36042007-12-20 19:59:30 -0800453 int i;
454
Michael Chanb6016b72005-05-26 13:03:09 -0700455 atomic_inc(&bp->intr_sem);
456 bnx2_disable_int(bp);
Michael Chanb4b36042007-12-20 19:59:30 -0800457 for (i = 0; i < bp->irq_nvecs; i++)
458 synchronize_irq(bp->irq_tbl[i].vector);
Michael Chanb6016b72005-05-26 13:03:09 -0700459}
460
461static void
Michael Chan35efa7c2007-12-20 19:56:37 -0800462bnx2_napi_disable(struct bnx2 *bp)
463{
Michael Chanb4b36042007-12-20 19:59:30 -0800464 int i;
465
466 for (i = 0; i < bp->irq_nvecs; i++)
467 napi_disable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800468}
469
470static void
471bnx2_napi_enable(struct bnx2 *bp)
472{
Michael Chanb4b36042007-12-20 19:59:30 -0800473 int i;
474
475 for (i = 0; i < bp->irq_nvecs; i++)
476 napi_enable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800477}
478
479static void
Michael Chanb6016b72005-05-26 13:03:09 -0700480bnx2_netif_stop(struct bnx2 *bp)
481{
482 bnx2_disable_int_sync(bp);
483 if (netif_running(bp->dev)) {
Michael Chan35efa7c2007-12-20 19:56:37 -0800484 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700485 netif_tx_disable(bp->dev);
486 bp->dev->trans_start = jiffies; /* prevent tx timeout */
487 }
488}
489
490static void
491bnx2_netif_start(struct bnx2 *bp)
492{
493 if (atomic_dec_and_test(&bp->intr_sem)) {
494 if (netif_running(bp->dev)) {
Benjamin Li706bf242008-07-18 17:55:11 -0700495 netif_tx_wake_all_queues(bp->dev);
Michael Chan35efa7c2007-12-20 19:56:37 -0800496 bnx2_napi_enable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700497 bnx2_enable_int(bp);
498 }
499 }
500}
501
502static void
Michael Chan35e90102008-06-19 16:37:42 -0700503bnx2_free_tx_mem(struct bnx2 *bp)
504{
505 int i;
506
507 for (i = 0; i < bp->num_tx_rings; i++) {
508 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
509 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
510
511 if (txr->tx_desc_ring) {
512 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
513 txr->tx_desc_ring,
514 txr->tx_desc_mapping);
515 txr->tx_desc_ring = NULL;
516 }
517 kfree(txr->tx_buf_ring);
518 txr->tx_buf_ring = NULL;
519 }
520}
521
Michael Chanbb4f98a2008-06-19 16:38:19 -0700522static void
523bnx2_free_rx_mem(struct bnx2 *bp)
524{
525 int i;
526
527 for (i = 0; i < bp->num_rx_rings; i++) {
528 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
529 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
530 int j;
531
532 for (j = 0; j < bp->rx_max_ring; j++) {
533 if (rxr->rx_desc_ring[j])
534 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
535 rxr->rx_desc_ring[j],
536 rxr->rx_desc_mapping[j]);
537 rxr->rx_desc_ring[j] = NULL;
538 }
539 if (rxr->rx_buf_ring)
540 vfree(rxr->rx_buf_ring);
541 rxr->rx_buf_ring = NULL;
542
543 for (j = 0; j < bp->rx_max_pg_ring; j++) {
544 if (rxr->rx_pg_desc_ring[j])
545 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
546 rxr->rx_pg_desc_ring[i],
547 rxr->rx_pg_desc_mapping[i]);
548 rxr->rx_pg_desc_ring[i] = NULL;
549 }
550 if (rxr->rx_pg_ring)
551 vfree(rxr->rx_pg_ring);
552 rxr->rx_pg_ring = NULL;
553 }
554}
555
Michael Chan35e90102008-06-19 16:37:42 -0700556static int
557bnx2_alloc_tx_mem(struct bnx2 *bp)
558{
559 int i;
560
561 for (i = 0; i < bp->num_tx_rings; i++) {
562 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
563 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
564
565 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
566 if (txr->tx_buf_ring == NULL)
567 return -ENOMEM;
568
569 txr->tx_desc_ring =
570 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
571 &txr->tx_desc_mapping);
572 if (txr->tx_desc_ring == NULL)
573 return -ENOMEM;
574 }
575 return 0;
576}
577
Michael Chanbb4f98a2008-06-19 16:38:19 -0700578static int
579bnx2_alloc_rx_mem(struct bnx2 *bp)
580{
581 int i;
582
583 for (i = 0; i < bp->num_rx_rings; i++) {
584 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
585 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
586 int j;
587
588 rxr->rx_buf_ring =
589 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
590 if (rxr->rx_buf_ring == NULL)
591 return -ENOMEM;
592
593 memset(rxr->rx_buf_ring, 0,
594 SW_RXBD_RING_SIZE * bp->rx_max_ring);
595
596 for (j = 0; j < bp->rx_max_ring; j++) {
597 rxr->rx_desc_ring[j] =
598 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
599 &rxr->rx_desc_mapping[j]);
600 if (rxr->rx_desc_ring[j] == NULL)
601 return -ENOMEM;
602
603 }
604
605 if (bp->rx_pg_ring_size) {
606 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
607 bp->rx_max_pg_ring);
608 if (rxr->rx_pg_ring == NULL)
609 return -ENOMEM;
610
611 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
612 bp->rx_max_pg_ring);
613 }
614
615 for (j = 0; j < bp->rx_max_pg_ring; j++) {
616 rxr->rx_pg_desc_ring[j] =
617 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
618 &rxr->rx_pg_desc_mapping[j]);
619 if (rxr->rx_pg_desc_ring[j] == NULL)
620 return -ENOMEM;
621
622 }
623 }
624 return 0;
625}
626
Michael Chan35e90102008-06-19 16:37:42 -0700627static void
Michael Chanb6016b72005-05-26 13:03:09 -0700628bnx2_free_mem(struct bnx2 *bp)
629{
Michael Chan13daffa2006-03-20 17:49:20 -0800630 int i;
Michael Chan43e80b82008-06-19 16:41:08 -0700631 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
Michael Chan13daffa2006-03-20 17:49:20 -0800632
Michael Chan35e90102008-06-19 16:37:42 -0700633 bnx2_free_tx_mem(bp);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700634 bnx2_free_rx_mem(bp);
Michael Chan35e90102008-06-19 16:37:42 -0700635
Michael Chan59b47d82006-11-19 14:10:45 -0800636 for (i = 0; i < bp->ctx_pages; i++) {
637 if (bp->ctx_blk[i]) {
638 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
639 bp->ctx_blk[i],
640 bp->ctx_blk_mapping[i]);
641 bp->ctx_blk[i] = NULL;
642 }
643 }
Michael Chan43e80b82008-06-19 16:41:08 -0700644 if (bnapi->status_blk.msi) {
Michael Chan0f31f992006-03-23 01:12:38 -0800645 pci_free_consistent(bp->pdev, bp->status_stats_size,
Michael Chan43e80b82008-06-19 16:41:08 -0700646 bnapi->status_blk.msi,
647 bp->status_blk_mapping);
648 bnapi->status_blk.msi = NULL;
Michael Chan0f31f992006-03-23 01:12:38 -0800649 bp->stats_blk = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -0700650 }
Michael Chanb6016b72005-05-26 13:03:09 -0700651}
652
653static int
654bnx2_alloc_mem(struct bnx2 *bp)
655{
Michael Chan35e90102008-06-19 16:37:42 -0700656 int i, status_blk_size, err;
Michael Chan43e80b82008-06-19 16:41:08 -0700657 struct bnx2_napi *bnapi;
658 void *status_blk;
Michael Chanb6016b72005-05-26 13:03:09 -0700659
Michael Chan0f31f992006-03-23 01:12:38 -0800660 /* Combine status and statistics blocks into one allocation. */
661 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
David S. Millerf86e82f2008-01-21 17:15:40 -0800662 if (bp->flags & BNX2_FLAG_MSIX_CAP)
Michael Chanb4b36042007-12-20 19:59:30 -0800663 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
664 BNX2_SBLK_MSIX_ALIGN_SIZE);
Michael Chan0f31f992006-03-23 01:12:38 -0800665 bp->status_stats_size = status_blk_size +
666 sizeof(struct statistics_block);
667
Michael Chan43e80b82008-06-19 16:41:08 -0700668 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
669 &bp->status_blk_mapping);
670 if (status_blk == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -0700671 goto alloc_mem_err;
672
Michael Chan43e80b82008-06-19 16:41:08 -0700673 memset(status_blk, 0, bp->status_stats_size);
Michael Chanb6016b72005-05-26 13:03:09 -0700674
Michael Chan43e80b82008-06-19 16:41:08 -0700675 bnapi = &bp->bnx2_napi[0];
676 bnapi->status_blk.msi = status_blk;
677 bnapi->hw_tx_cons_ptr =
678 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
679 bnapi->hw_rx_cons_ptr =
680 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
David S. Millerf86e82f2008-01-21 17:15:40 -0800681 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
Michael Chanb4b36042007-12-20 19:59:30 -0800682 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
Michael Chan43e80b82008-06-19 16:41:08 -0700683 struct status_block_msix *sblk;
Michael Chanb4b36042007-12-20 19:59:30 -0800684
Michael Chan43e80b82008-06-19 16:41:08 -0700685 bnapi = &bp->bnx2_napi[i];
686
687 sblk = (void *) (status_blk +
688 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
689 bnapi->status_blk.msix = sblk;
690 bnapi->hw_tx_cons_ptr =
691 &sblk->status_tx_quick_consumer_index;
692 bnapi->hw_rx_cons_ptr =
693 &sblk->status_rx_quick_consumer_index;
Michael Chanb4b36042007-12-20 19:59:30 -0800694 bnapi->int_num = i << 24;
695 }
696 }
Michael Chan35efa7c2007-12-20 19:56:37 -0800697
Michael Chan43e80b82008-06-19 16:41:08 -0700698 bp->stats_blk = status_blk + status_blk_size;
Michael Chanb6016b72005-05-26 13:03:09 -0700699
Michael Chan0f31f992006-03-23 01:12:38 -0800700 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
Michael Chanb6016b72005-05-26 13:03:09 -0700701
Michael Chan59b47d82006-11-19 14:10:45 -0800702 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
703 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
704 if (bp->ctx_pages == 0)
705 bp->ctx_pages = 1;
706 for (i = 0; i < bp->ctx_pages; i++) {
707 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
708 BCM_PAGE_SIZE,
709 &bp->ctx_blk_mapping[i]);
710 if (bp->ctx_blk[i] == NULL)
711 goto alloc_mem_err;
712 }
713 }
Michael Chan35e90102008-06-19 16:37:42 -0700714
Michael Chanbb4f98a2008-06-19 16:38:19 -0700715 err = bnx2_alloc_rx_mem(bp);
716 if (err)
717 goto alloc_mem_err;
718
Michael Chan35e90102008-06-19 16:37:42 -0700719 err = bnx2_alloc_tx_mem(bp);
720 if (err)
721 goto alloc_mem_err;
722
Michael Chanb6016b72005-05-26 13:03:09 -0700723 return 0;
724
725alloc_mem_err:
726 bnx2_free_mem(bp);
727 return -ENOMEM;
728}
729
730static void
Michael Chane3648b32005-11-04 08:51:21 -0800731bnx2_report_fw_link(struct bnx2 *bp)
732{
733 u32 fw_link_status = 0;
734
Michael Chan583c28e2008-01-21 19:51:35 -0800735 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -0700736 return;
737
Michael Chane3648b32005-11-04 08:51:21 -0800738 if (bp->link_up) {
739 u32 bmsr;
740
741 switch (bp->line_speed) {
742 case SPEED_10:
743 if (bp->duplex == DUPLEX_HALF)
744 fw_link_status = BNX2_LINK_STATUS_10HALF;
745 else
746 fw_link_status = BNX2_LINK_STATUS_10FULL;
747 break;
748 case SPEED_100:
749 if (bp->duplex == DUPLEX_HALF)
750 fw_link_status = BNX2_LINK_STATUS_100HALF;
751 else
752 fw_link_status = BNX2_LINK_STATUS_100FULL;
753 break;
754 case SPEED_1000:
755 if (bp->duplex == DUPLEX_HALF)
756 fw_link_status = BNX2_LINK_STATUS_1000HALF;
757 else
758 fw_link_status = BNX2_LINK_STATUS_1000FULL;
759 break;
760 case SPEED_2500:
761 if (bp->duplex == DUPLEX_HALF)
762 fw_link_status = BNX2_LINK_STATUS_2500HALF;
763 else
764 fw_link_status = BNX2_LINK_STATUS_2500FULL;
765 break;
766 }
767
768 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
769
770 if (bp->autoneg) {
771 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
772
Michael Chanca58c3a2007-05-03 13:22:52 -0700773 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
774 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chane3648b32005-11-04 08:51:21 -0800775
776 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
Michael Chan583c28e2008-01-21 19:51:35 -0800777 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
Michael Chane3648b32005-11-04 08:51:21 -0800778 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
779 else
780 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
781 }
782 }
783 else
784 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
785
Michael Chan2726d6e2008-01-29 21:35:05 -0800786 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
Michael Chane3648b32005-11-04 08:51:21 -0800787}
788
Michael Chan9b1084b2007-07-07 22:50:37 -0700789static char *
790bnx2_xceiver_str(struct bnx2 *bp)
791{
792 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
Michael Chan583c28e2008-01-21 19:51:35 -0800793 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
Michael Chan9b1084b2007-07-07 22:50:37 -0700794 "Copper"));
795}
796
Michael Chane3648b32005-11-04 08:51:21 -0800797static void
Michael Chanb6016b72005-05-26 13:03:09 -0700798bnx2_report_link(struct bnx2 *bp)
799{
800 if (bp->link_up) {
801 netif_carrier_on(bp->dev);
Michael Chan9b1084b2007-07-07 22:50:37 -0700802 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
803 bnx2_xceiver_str(bp));
Michael Chanb6016b72005-05-26 13:03:09 -0700804
805 printk("%d Mbps ", bp->line_speed);
806
807 if (bp->duplex == DUPLEX_FULL)
808 printk("full duplex");
809 else
810 printk("half duplex");
811
812 if (bp->flow_ctrl) {
813 if (bp->flow_ctrl & FLOW_CTRL_RX) {
814 printk(", receive ");
815 if (bp->flow_ctrl & FLOW_CTRL_TX)
816 printk("& transmit ");
817 }
818 else {
819 printk(", transmit ");
820 }
821 printk("flow control ON");
822 }
823 printk("\n");
824 }
825 else {
826 netif_carrier_off(bp->dev);
Michael Chan9b1084b2007-07-07 22:50:37 -0700827 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
828 bnx2_xceiver_str(bp));
Michael Chanb6016b72005-05-26 13:03:09 -0700829 }
Michael Chane3648b32005-11-04 08:51:21 -0800830
831 bnx2_report_fw_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700832}
833
834static void
835bnx2_resolve_flow_ctrl(struct bnx2 *bp)
836{
837 u32 local_adv, remote_adv;
838
839 bp->flow_ctrl = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400840 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
Michael Chanb6016b72005-05-26 13:03:09 -0700841 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
842
843 if (bp->duplex == DUPLEX_FULL) {
844 bp->flow_ctrl = bp->req_flow_ctrl;
845 }
846 return;
847 }
848
849 if (bp->duplex != DUPLEX_FULL) {
850 return;
851 }
852
Michael Chan583c28e2008-01-21 19:51:35 -0800853 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan5b0c76a2005-11-04 08:45:49 -0800854 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
855 u32 val;
856
857 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
858 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
859 bp->flow_ctrl |= FLOW_CTRL_TX;
860 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
861 bp->flow_ctrl |= FLOW_CTRL_RX;
862 return;
863 }
864
Michael Chanca58c3a2007-05-03 13:22:52 -0700865 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
866 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -0700867
Michael Chan583c28e2008-01-21 19:51:35 -0800868 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -0700869 u32 new_local_adv = 0;
870 u32 new_remote_adv = 0;
871
872 if (local_adv & ADVERTISE_1000XPAUSE)
873 new_local_adv |= ADVERTISE_PAUSE_CAP;
874 if (local_adv & ADVERTISE_1000XPSE_ASYM)
875 new_local_adv |= ADVERTISE_PAUSE_ASYM;
876 if (remote_adv & ADVERTISE_1000XPAUSE)
877 new_remote_adv |= ADVERTISE_PAUSE_CAP;
878 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
879 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
880
881 local_adv = new_local_adv;
882 remote_adv = new_remote_adv;
883 }
884
885 /* See Table 28B-3 of 802.3ab-1999 spec. */
886 if (local_adv & ADVERTISE_PAUSE_CAP) {
887 if(local_adv & ADVERTISE_PAUSE_ASYM) {
888 if (remote_adv & ADVERTISE_PAUSE_CAP) {
889 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
890 }
891 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
892 bp->flow_ctrl = FLOW_CTRL_RX;
893 }
894 }
895 else {
896 if (remote_adv & ADVERTISE_PAUSE_CAP) {
897 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
898 }
899 }
900 }
901 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
902 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
903 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
904
905 bp->flow_ctrl = FLOW_CTRL_TX;
906 }
907 }
908}
909
910static int
Michael Chan27a005b2007-05-03 13:23:41 -0700911bnx2_5709s_linkup(struct bnx2 *bp)
912{
913 u32 val, speed;
914
915 bp->link_up = 1;
916
917 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
918 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
919 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
920
921 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
922 bp->line_speed = bp->req_line_speed;
923 bp->duplex = bp->req_duplex;
924 return 0;
925 }
926 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
927 switch (speed) {
928 case MII_BNX2_GP_TOP_AN_SPEED_10:
929 bp->line_speed = SPEED_10;
930 break;
931 case MII_BNX2_GP_TOP_AN_SPEED_100:
932 bp->line_speed = SPEED_100;
933 break;
934 case MII_BNX2_GP_TOP_AN_SPEED_1G:
935 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
936 bp->line_speed = SPEED_1000;
937 break;
938 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
939 bp->line_speed = SPEED_2500;
940 break;
941 }
942 if (val & MII_BNX2_GP_TOP_AN_FD)
943 bp->duplex = DUPLEX_FULL;
944 else
945 bp->duplex = DUPLEX_HALF;
946 return 0;
947}
948
949static int
Michael Chan5b0c76a2005-11-04 08:45:49 -0800950bnx2_5708s_linkup(struct bnx2 *bp)
951{
952 u32 val;
953
954 bp->link_up = 1;
955 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
956 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
957 case BCM5708S_1000X_STAT1_SPEED_10:
958 bp->line_speed = SPEED_10;
959 break;
960 case BCM5708S_1000X_STAT1_SPEED_100:
961 bp->line_speed = SPEED_100;
962 break;
963 case BCM5708S_1000X_STAT1_SPEED_1G:
964 bp->line_speed = SPEED_1000;
965 break;
966 case BCM5708S_1000X_STAT1_SPEED_2G5:
967 bp->line_speed = SPEED_2500;
968 break;
969 }
970 if (val & BCM5708S_1000X_STAT1_FD)
971 bp->duplex = DUPLEX_FULL;
972 else
973 bp->duplex = DUPLEX_HALF;
974
975 return 0;
976}
977
978static int
979bnx2_5706s_linkup(struct bnx2 *bp)
Michael Chanb6016b72005-05-26 13:03:09 -0700980{
981 u32 bmcr, local_adv, remote_adv, common;
982
983 bp->link_up = 1;
984 bp->line_speed = SPEED_1000;
985
Michael Chanca58c3a2007-05-03 13:22:52 -0700986 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -0700987 if (bmcr & BMCR_FULLDPLX) {
988 bp->duplex = DUPLEX_FULL;
989 }
990 else {
991 bp->duplex = DUPLEX_HALF;
992 }
993
994 if (!(bmcr & BMCR_ANENABLE)) {
995 return 0;
996 }
997
Michael Chanca58c3a2007-05-03 13:22:52 -0700998 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
999 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001000
1001 common = local_adv & remote_adv;
1002 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1003
1004 if (common & ADVERTISE_1000XFULL) {
1005 bp->duplex = DUPLEX_FULL;
1006 }
1007 else {
1008 bp->duplex = DUPLEX_HALF;
1009 }
1010 }
1011
1012 return 0;
1013}
1014
1015static int
1016bnx2_copper_linkup(struct bnx2 *bp)
1017{
1018 u32 bmcr;
1019
Michael Chanca58c3a2007-05-03 13:22:52 -07001020 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001021 if (bmcr & BMCR_ANENABLE) {
1022 u32 local_adv, remote_adv, common;
1023
1024 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1025 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1026
1027 common = local_adv & (remote_adv >> 2);
1028 if (common & ADVERTISE_1000FULL) {
1029 bp->line_speed = SPEED_1000;
1030 bp->duplex = DUPLEX_FULL;
1031 }
1032 else if (common & ADVERTISE_1000HALF) {
1033 bp->line_speed = SPEED_1000;
1034 bp->duplex = DUPLEX_HALF;
1035 }
1036 else {
Michael Chanca58c3a2007-05-03 13:22:52 -07001037 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1038 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001039
1040 common = local_adv & remote_adv;
1041 if (common & ADVERTISE_100FULL) {
1042 bp->line_speed = SPEED_100;
1043 bp->duplex = DUPLEX_FULL;
1044 }
1045 else if (common & ADVERTISE_100HALF) {
1046 bp->line_speed = SPEED_100;
1047 bp->duplex = DUPLEX_HALF;
1048 }
1049 else if (common & ADVERTISE_10FULL) {
1050 bp->line_speed = SPEED_10;
1051 bp->duplex = DUPLEX_FULL;
1052 }
1053 else if (common & ADVERTISE_10HALF) {
1054 bp->line_speed = SPEED_10;
1055 bp->duplex = DUPLEX_HALF;
1056 }
1057 else {
1058 bp->line_speed = 0;
1059 bp->link_up = 0;
1060 }
1061 }
1062 }
1063 else {
1064 if (bmcr & BMCR_SPEED100) {
1065 bp->line_speed = SPEED_100;
1066 }
1067 else {
1068 bp->line_speed = SPEED_10;
1069 }
1070 if (bmcr & BMCR_FULLDPLX) {
1071 bp->duplex = DUPLEX_FULL;
1072 }
1073 else {
1074 bp->duplex = DUPLEX_HALF;
1075 }
1076 }
1077
1078 return 0;
1079}
1080
Michael Chan83e3fc82008-01-29 21:37:17 -08001081static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07001082bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
Michael Chan83e3fc82008-01-29 21:37:17 -08001083{
Michael Chanbb4f98a2008-06-19 16:38:19 -07001084 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
Michael Chan83e3fc82008-01-29 21:37:17 -08001085
1086 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1087 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1088 val |= 0x02 << 8;
1089
1090 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1091 u32 lo_water, hi_water;
1092
1093 if (bp->flow_ctrl & FLOW_CTRL_TX)
1094 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1095 else
1096 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1097 if (lo_water >= bp->rx_ring_size)
1098 lo_water = 0;
1099
1100 hi_water = bp->rx_ring_size / 4;
1101
1102 if (hi_water <= lo_water)
1103 lo_water = 0;
1104
1105 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1106 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1107
1108 if (hi_water > 0xf)
1109 hi_water = 0xf;
1110 else if (hi_water == 0)
1111 lo_water = 0;
1112 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1113 }
1114 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1115}
1116
Michael Chanbb4f98a2008-06-19 16:38:19 -07001117static void
1118bnx2_init_all_rx_contexts(struct bnx2 *bp)
1119{
1120 int i;
1121 u32 cid;
1122
1123 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1124 if (i == 1)
1125 cid = RX_RSS_CID;
1126 bnx2_init_rx_context(bp, cid);
1127 }
1128}
1129
Benjamin Li344478d2008-09-18 16:38:24 -07001130static void
Michael Chanb6016b72005-05-26 13:03:09 -07001131bnx2_set_mac_link(struct bnx2 *bp)
1132{
1133 u32 val;
1134
1135 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1136 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1137 (bp->duplex == DUPLEX_HALF)) {
1138 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1139 }
1140
1141 /* Configure the EMAC mode register. */
1142 val = REG_RD(bp, BNX2_EMAC_MODE);
1143
1144 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
Michael Chan5b0c76a2005-11-04 08:45:49 -08001145 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08001146 BNX2_EMAC_MODE_25G_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -07001147
1148 if (bp->link_up) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001149 switch (bp->line_speed) {
1150 case SPEED_10:
Michael Chan59b47d82006-11-19 14:10:45 -08001151 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1152 val |= BNX2_EMAC_MODE_PORT_MII_10M;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001153 break;
1154 }
1155 /* fall through */
1156 case SPEED_100:
1157 val |= BNX2_EMAC_MODE_PORT_MII;
1158 break;
1159 case SPEED_2500:
Michael Chan59b47d82006-11-19 14:10:45 -08001160 val |= BNX2_EMAC_MODE_25G_MODE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001161 /* fall through */
1162 case SPEED_1000:
1163 val |= BNX2_EMAC_MODE_PORT_GMII;
1164 break;
1165 }
Michael Chanb6016b72005-05-26 13:03:09 -07001166 }
1167 else {
1168 val |= BNX2_EMAC_MODE_PORT_GMII;
1169 }
1170
1171 /* Set the MAC to operate in the appropriate duplex mode. */
1172 if (bp->duplex == DUPLEX_HALF)
1173 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1174 REG_WR(bp, BNX2_EMAC_MODE, val);
1175
1176 /* Enable/disable rx PAUSE. */
1177 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1178
1179 if (bp->flow_ctrl & FLOW_CTRL_RX)
1180 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1181 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1182
1183 /* Enable/disable tx PAUSE. */
1184 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1185 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1186
1187 if (bp->flow_ctrl & FLOW_CTRL_TX)
1188 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1189 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1190
1191 /* Acknowledge the interrupt. */
1192 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1193
Michael Chan83e3fc82008-01-29 21:37:17 -08001194 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chanbb4f98a2008-06-19 16:38:19 -07001195 bnx2_init_all_rx_contexts(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001196}
1197
Michael Chan27a005b2007-05-03 13:23:41 -07001198static void
1199bnx2_enable_bmsr1(struct bnx2 *bp)
1200{
Michael Chan583c28e2008-01-21 19:51:35 -08001201 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan27a005b2007-05-03 13:23:41 -07001202 (CHIP_NUM(bp) == CHIP_NUM_5709))
1203 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1204 MII_BNX2_BLK_ADDR_GP_STATUS);
1205}
1206
1207static void
1208bnx2_disable_bmsr1(struct bnx2 *bp)
1209{
Michael Chan583c28e2008-01-21 19:51:35 -08001210 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan27a005b2007-05-03 13:23:41 -07001211 (CHIP_NUM(bp) == CHIP_NUM_5709))
1212 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1214}
1215
Michael Chanb6016b72005-05-26 13:03:09 -07001216static int
Michael Chan605a9e22007-05-03 13:23:13 -07001217bnx2_test_and_enable_2g5(struct bnx2 *bp)
1218{
1219 u32 up1;
1220 int ret = 1;
1221
Michael Chan583c28e2008-01-21 19:51:35 -08001222 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001223 return 0;
1224
1225 if (bp->autoneg & AUTONEG_SPEED)
1226 bp->advertising |= ADVERTISED_2500baseX_Full;
1227
Michael Chan27a005b2007-05-03 13:23:41 -07001228 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1229 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1230
Michael Chan605a9e22007-05-03 13:23:13 -07001231 bnx2_read_phy(bp, bp->mii_up1, &up1);
1232 if (!(up1 & BCM5708S_UP1_2G5)) {
1233 up1 |= BCM5708S_UP1_2G5;
1234 bnx2_write_phy(bp, bp->mii_up1, up1);
1235 ret = 0;
1236 }
1237
Michael Chan27a005b2007-05-03 13:23:41 -07001238 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1239 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1240 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1241
Michael Chan605a9e22007-05-03 13:23:13 -07001242 return ret;
1243}
1244
1245static int
1246bnx2_test_and_disable_2g5(struct bnx2 *bp)
1247{
1248 u32 up1;
1249 int ret = 0;
1250
Michael Chan583c28e2008-01-21 19:51:35 -08001251 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001252 return 0;
1253
Michael Chan27a005b2007-05-03 13:23:41 -07001254 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1255 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1256
Michael Chan605a9e22007-05-03 13:23:13 -07001257 bnx2_read_phy(bp, bp->mii_up1, &up1);
1258 if (up1 & BCM5708S_UP1_2G5) {
1259 up1 &= ~BCM5708S_UP1_2G5;
1260 bnx2_write_phy(bp, bp->mii_up1, up1);
1261 ret = 1;
1262 }
1263
Michael Chan27a005b2007-05-03 13:23:41 -07001264 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1265 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1266 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1267
Michael Chan605a9e22007-05-03 13:23:13 -07001268 return ret;
1269}
1270
1271static void
1272bnx2_enable_forced_2g5(struct bnx2 *bp)
1273{
1274 u32 bmcr;
1275
Michael Chan583c28e2008-01-21 19:51:35 -08001276 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001277 return;
1278
Michael Chan27a005b2007-05-03 13:23:41 -07001279 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1280 u32 val;
1281
1282 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1283 MII_BNX2_BLK_ADDR_SERDES_DIG);
1284 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1285 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1286 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1287 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1288
1289 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1290 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1291 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1292
1293 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001294 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1295 bmcr |= BCM5708S_BMCR_FORCE_2500;
1296 }
1297
1298 if (bp->autoneg & AUTONEG_SPEED) {
1299 bmcr &= ~BMCR_ANENABLE;
1300 if (bp->req_duplex == DUPLEX_FULL)
1301 bmcr |= BMCR_FULLDPLX;
1302 }
1303 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1304}
1305
1306static void
1307bnx2_disable_forced_2g5(struct bnx2 *bp)
1308{
1309 u32 bmcr;
1310
Michael Chan583c28e2008-01-21 19:51:35 -08001311 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001312 return;
1313
Michael Chan27a005b2007-05-03 13:23:41 -07001314 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1315 u32 val;
1316
1317 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1318 MII_BNX2_BLK_ADDR_SERDES_DIG);
1319 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1320 val &= ~MII_BNX2_SD_MISC1_FORCE;
1321 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1322
1323 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1324 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1325 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1326
1327 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001328 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1329 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1330 }
1331
1332 if (bp->autoneg & AUTONEG_SPEED)
1333 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1334 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1335}
1336
Michael Chanb2fadea2008-01-21 17:07:06 -08001337static void
1338bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1339{
1340 u32 val;
1341
1342 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1343 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1344 if (start)
1345 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1346 else
1347 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1348}
1349
Michael Chan605a9e22007-05-03 13:23:13 -07001350static int
Michael Chanb6016b72005-05-26 13:03:09 -07001351bnx2_set_link(struct bnx2 *bp)
1352{
1353 u32 bmsr;
1354 u8 link_up;
1355
Michael Chan80be4432006-11-19 14:07:28 -08001356 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
Michael Chanb6016b72005-05-26 13:03:09 -07001357 bp->link_up = 1;
1358 return 0;
1359 }
1360
Michael Chan583c28e2008-01-21 19:51:35 -08001361 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001362 return 0;
1363
Michael Chanb6016b72005-05-26 13:03:09 -07001364 link_up = bp->link_up;
1365
Michael Chan27a005b2007-05-03 13:23:41 -07001366 bnx2_enable_bmsr1(bp);
1367 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1368 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1369 bnx2_disable_bmsr1(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001370
Michael Chan583c28e2008-01-21 19:51:35 -08001371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chanb6016b72005-05-26 13:03:09 -07001372 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
Michael Chana2724e22008-02-23 19:47:44 -08001373 u32 val, an_dbg;
Michael Chanb6016b72005-05-26 13:03:09 -07001374
Michael Chan583c28e2008-01-21 19:51:35 -08001375 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001376 bnx2_5706s_force_link_dn(bp, 0);
Michael Chan583c28e2008-01-21 19:51:35 -08001377 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
Michael Chanb2fadea2008-01-21 17:07:06 -08001378 }
Michael Chanb6016b72005-05-26 13:03:09 -07001379 val = REG_RD(bp, BNX2_EMAC_STATUS);
Michael Chana2724e22008-02-23 19:47:44 -08001380
1381 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1382 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1383 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1384
1385 if ((val & BNX2_EMAC_STATUS_LINK) &&
1386 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
Michael Chanb6016b72005-05-26 13:03:09 -07001387 bmsr |= BMSR_LSTATUS;
1388 else
1389 bmsr &= ~BMSR_LSTATUS;
1390 }
1391
1392 if (bmsr & BMSR_LSTATUS) {
1393 bp->link_up = 1;
1394
Michael Chan583c28e2008-01-21 19:51:35 -08001395 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001396 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1397 bnx2_5706s_linkup(bp);
1398 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1399 bnx2_5708s_linkup(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07001400 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1401 bnx2_5709s_linkup(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001402 }
1403 else {
1404 bnx2_copper_linkup(bp);
1405 }
1406 bnx2_resolve_flow_ctrl(bp);
1407 }
1408 else {
Michael Chan583c28e2008-01-21 19:51:35 -08001409 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan605a9e22007-05-03 13:23:13 -07001410 (bp->autoneg & AUTONEG_SPEED))
1411 bnx2_disable_forced_2g5(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001412
Michael Chan583c28e2008-01-21 19:51:35 -08001413 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001414 u32 bmcr;
1415
1416 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1417 bmcr |= BMCR_ANENABLE;
1418 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1419
Michael Chan583c28e2008-01-21 19:51:35 -08001420 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb2fadea2008-01-21 17:07:06 -08001421 }
Michael Chanb6016b72005-05-26 13:03:09 -07001422 bp->link_up = 0;
1423 }
1424
1425 if (bp->link_up != link_up) {
1426 bnx2_report_link(bp);
1427 }
1428
1429 bnx2_set_mac_link(bp);
1430
1431 return 0;
1432}
1433
1434static int
1435bnx2_reset_phy(struct bnx2 *bp)
1436{
1437 int i;
1438 u32 reg;
1439
Michael Chanca58c3a2007-05-03 13:22:52 -07001440 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
Michael Chanb6016b72005-05-26 13:03:09 -07001441
1442#define PHY_RESET_MAX_WAIT 100
1443 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1444 udelay(10);
1445
Michael Chanca58c3a2007-05-03 13:22:52 -07001446 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001447 if (!(reg & BMCR_RESET)) {
1448 udelay(20);
1449 break;
1450 }
1451 }
1452 if (i == PHY_RESET_MAX_WAIT) {
1453 return -EBUSY;
1454 }
1455 return 0;
1456}
1457
1458static u32
1459bnx2_phy_get_pause_adv(struct bnx2 *bp)
1460{
1461 u32 adv = 0;
1462
1463 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1464 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1465
Michael Chan583c28e2008-01-21 19:51:35 -08001466 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001467 adv = ADVERTISE_1000XPAUSE;
1468 }
1469 else {
1470 adv = ADVERTISE_PAUSE_CAP;
1471 }
1472 }
1473 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001474 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001475 adv = ADVERTISE_1000XPSE_ASYM;
1476 }
1477 else {
1478 adv = ADVERTISE_PAUSE_ASYM;
1479 }
1480 }
1481 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001482 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001483 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1484 }
1485 else {
1486 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1487 }
1488 }
1489 return adv;
1490}
1491
Michael Chana2f13892008-07-14 22:38:23 -07001492static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
Michael Chan0d8a6572007-07-07 22:49:43 -07001493
Michael Chanb6016b72005-05-26 13:03:09 -07001494static int
Michael Chan0d8a6572007-07-07 22:49:43 -07001495bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1496{
1497 u32 speed_arg = 0, pause_adv;
1498
1499 pause_adv = bnx2_phy_get_pause_adv(bp);
1500
1501 if (bp->autoneg & AUTONEG_SPEED) {
1502 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1503 if (bp->advertising & ADVERTISED_10baseT_Half)
1504 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1505 if (bp->advertising & ADVERTISED_10baseT_Full)
1506 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1507 if (bp->advertising & ADVERTISED_100baseT_Half)
1508 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1509 if (bp->advertising & ADVERTISED_100baseT_Full)
1510 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1511 if (bp->advertising & ADVERTISED_1000baseT_Full)
1512 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1513 if (bp->advertising & ADVERTISED_2500baseX_Full)
1514 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1515 } else {
1516 if (bp->req_line_speed == SPEED_2500)
1517 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1518 else if (bp->req_line_speed == SPEED_1000)
1519 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1520 else if (bp->req_line_speed == SPEED_100) {
1521 if (bp->req_duplex == DUPLEX_FULL)
1522 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1523 else
1524 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1525 } else if (bp->req_line_speed == SPEED_10) {
1526 if (bp->req_duplex == DUPLEX_FULL)
1527 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1528 else
1529 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1530 }
1531 }
1532
1533 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1534 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
Michael Chanc26736e2008-01-31 17:07:21 -08001535 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
Michael Chan0d8a6572007-07-07 22:49:43 -07001536 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1537
1538 if (port == PORT_TP)
1539 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1540 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1541
Michael Chan2726d6e2008-01-29 21:35:05 -08001542 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
Michael Chan0d8a6572007-07-07 22:49:43 -07001543
1544 spin_unlock_bh(&bp->phy_lock);
Michael Chana2f13892008-07-14 22:38:23 -07001545 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
Michael Chan0d8a6572007-07-07 22:49:43 -07001546 spin_lock_bh(&bp->phy_lock);
1547
1548 return 0;
1549}
1550
1551static int
1552bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
Michael Chanb6016b72005-05-26 13:03:09 -07001553{
Michael Chan605a9e22007-05-03 13:23:13 -07001554 u32 adv, bmcr;
Michael Chanb6016b72005-05-26 13:03:09 -07001555 u32 new_adv = 0;
1556
Michael Chan583c28e2008-01-21 19:51:35 -08001557 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001558 return (bnx2_setup_remote_phy(bp, port));
1559
Michael Chanb6016b72005-05-26 13:03:09 -07001560 if (!(bp->autoneg & AUTONEG_SPEED)) {
1561 u32 new_bmcr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001562 int force_link_down = 0;
1563
Michael Chan605a9e22007-05-03 13:23:13 -07001564 if (bp->req_line_speed == SPEED_2500) {
1565 if (!bnx2_test_and_enable_2g5(bp))
1566 force_link_down = 1;
1567 } else if (bp->req_line_speed == SPEED_1000) {
1568 if (bnx2_test_and_disable_2g5(bp))
1569 force_link_down = 1;
1570 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001571 bnx2_read_phy(bp, bp->mii_adv, &adv);
Michael Chan80be4432006-11-19 14:07:28 -08001572 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1573
Michael Chanca58c3a2007-05-03 13:22:52 -07001574 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001575 new_bmcr = bmcr & ~BMCR_ANENABLE;
Michael Chan80be4432006-11-19 14:07:28 -08001576 new_bmcr |= BMCR_SPEED1000;
Michael Chan605a9e22007-05-03 13:23:13 -07001577
Michael Chan27a005b2007-05-03 13:23:41 -07001578 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1579 if (bp->req_line_speed == SPEED_2500)
1580 bnx2_enable_forced_2g5(bp);
1581 else if (bp->req_line_speed == SPEED_1000) {
1582 bnx2_disable_forced_2g5(bp);
1583 new_bmcr &= ~0x2000;
1584 }
1585
1586 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001587 if (bp->req_line_speed == SPEED_2500)
1588 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1589 else
1590 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001591 }
1592
Michael Chanb6016b72005-05-26 13:03:09 -07001593 if (bp->req_duplex == DUPLEX_FULL) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001594 adv |= ADVERTISE_1000XFULL;
Michael Chanb6016b72005-05-26 13:03:09 -07001595 new_bmcr |= BMCR_FULLDPLX;
1596 }
1597 else {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001598 adv |= ADVERTISE_1000XHALF;
Michael Chanb6016b72005-05-26 13:03:09 -07001599 new_bmcr &= ~BMCR_FULLDPLX;
1600 }
Michael Chan5b0c76a2005-11-04 08:45:49 -08001601 if ((new_bmcr != bmcr) || (force_link_down)) {
Michael Chanb6016b72005-05-26 13:03:09 -07001602 /* Force a link down visible on the other side */
1603 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001604 bnx2_write_phy(bp, bp->mii_adv, adv &
Michael Chan5b0c76a2005-11-04 08:45:49 -08001605 ~(ADVERTISE_1000XFULL |
1606 ADVERTISE_1000XHALF));
Michael Chanca58c3a2007-05-03 13:22:52 -07001607 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
Michael Chanb6016b72005-05-26 13:03:09 -07001608 BMCR_ANRESTART | BMCR_ANENABLE);
1609
1610 bp->link_up = 0;
1611 netif_carrier_off(bp->dev);
Michael Chanca58c3a2007-05-03 13:22:52 -07001612 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan80be4432006-11-19 14:07:28 -08001613 bnx2_report_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001614 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001615 bnx2_write_phy(bp, bp->mii_adv, adv);
1616 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001617 } else {
1618 bnx2_resolve_flow_ctrl(bp);
1619 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001620 }
1621 return 0;
1622 }
1623
Michael Chan605a9e22007-05-03 13:23:13 -07001624 bnx2_test_and_enable_2g5(bp);
Michael Chan5b0c76a2005-11-04 08:45:49 -08001625
Michael Chanb6016b72005-05-26 13:03:09 -07001626 if (bp->advertising & ADVERTISED_1000baseT_Full)
1627 new_adv |= ADVERTISE_1000XFULL;
1628
1629 new_adv |= bnx2_phy_get_pause_adv(bp);
1630
Michael Chanca58c3a2007-05-03 13:22:52 -07001631 bnx2_read_phy(bp, bp->mii_adv, &adv);
1632 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001633
1634 bp->serdes_an_pending = 0;
1635 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1636 /* Force a link down visible on the other side */
1637 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001638 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chan80be4432006-11-19 14:07:28 -08001639 spin_unlock_bh(&bp->phy_lock);
1640 msleep(20);
1641 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07001642 }
1643
Michael Chanca58c3a2007-05-03 13:22:52 -07001644 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1645 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07001646 BMCR_ANENABLE);
Michael Chanf8dd0642006-11-19 14:08:29 -08001647 /* Speed up link-up time when the link partner
1648 * does not autonegotiate which is very common
1649 * in blade servers. Some blade servers use
1650 * IPMI for kerboard input and it's important
1651 * to minimize link disruptions. Autoneg. involves
1652 * exchanging base pages plus 3 next pages and
1653 * normally completes in about 120 msec.
1654 */
1655 bp->current_interval = SERDES_AN_TIMEOUT;
1656 bp->serdes_an_pending = 1;
1657 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chan605a9e22007-05-03 13:23:13 -07001658 } else {
1659 bnx2_resolve_flow_ctrl(bp);
1660 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001661 }
1662
1663 return 0;
1664}
1665
1666#define ETHTOOL_ALL_FIBRE_SPEED \
Michael Chan583c28e2008-01-21 19:51:35 -08001667 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
Michael Chandeaf3912007-07-07 22:48:00 -07001668 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1669 (ADVERTISED_1000baseT_Full)
Michael Chanb6016b72005-05-26 13:03:09 -07001670
1671#define ETHTOOL_ALL_COPPER_SPEED \
1672 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1673 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1674 ADVERTISED_1000baseT_Full)
1675
1676#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1677 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001678
Michael Chanb6016b72005-05-26 13:03:09 -07001679#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1680
Michael Chandeaf3912007-07-07 22:48:00 -07001681static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001682bnx2_set_default_remote_link(struct bnx2 *bp)
1683{
1684 u32 link;
1685
1686 if (bp->phy_port == PORT_TP)
Michael Chan2726d6e2008-01-29 21:35:05 -08001687 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001688 else
Michael Chan2726d6e2008-01-29 21:35:05 -08001689 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001690
1691 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1692 bp->req_line_speed = 0;
1693 bp->autoneg |= AUTONEG_SPEED;
1694 bp->advertising = ADVERTISED_Autoneg;
1695 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1696 bp->advertising |= ADVERTISED_10baseT_Half;
1697 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1698 bp->advertising |= ADVERTISED_10baseT_Full;
1699 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1700 bp->advertising |= ADVERTISED_100baseT_Half;
1701 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1702 bp->advertising |= ADVERTISED_100baseT_Full;
1703 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1704 bp->advertising |= ADVERTISED_1000baseT_Full;
1705 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1706 bp->advertising |= ADVERTISED_2500baseX_Full;
1707 } else {
1708 bp->autoneg = 0;
1709 bp->advertising = 0;
1710 bp->req_duplex = DUPLEX_FULL;
1711 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1712 bp->req_line_speed = SPEED_10;
1713 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1714 bp->req_duplex = DUPLEX_HALF;
1715 }
1716 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1717 bp->req_line_speed = SPEED_100;
1718 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1719 bp->req_duplex = DUPLEX_HALF;
1720 }
1721 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1722 bp->req_line_speed = SPEED_1000;
1723 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1724 bp->req_line_speed = SPEED_2500;
1725 }
1726}
1727
1728static void
Michael Chandeaf3912007-07-07 22:48:00 -07001729bnx2_set_default_link(struct bnx2 *bp)
1730{
Harvey Harrisonab598592008-05-01 02:47:38 -07001731 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1732 bnx2_set_default_remote_link(bp);
1733 return;
1734 }
Michael Chan0d8a6572007-07-07 22:49:43 -07001735
Michael Chandeaf3912007-07-07 22:48:00 -07001736 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1737 bp->req_line_speed = 0;
Michael Chan583c28e2008-01-21 19:51:35 -08001738 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chandeaf3912007-07-07 22:48:00 -07001739 u32 reg;
1740
1741 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1742
Michael Chan2726d6e2008-01-29 21:35:05 -08001743 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
Michael Chandeaf3912007-07-07 22:48:00 -07001744 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1745 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1746 bp->autoneg = 0;
1747 bp->req_line_speed = bp->line_speed = SPEED_1000;
1748 bp->req_duplex = DUPLEX_FULL;
1749 }
1750 } else
1751 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1752}
1753
Michael Chan0d8a6572007-07-07 22:49:43 -07001754static void
Michael Chandf149d72007-07-07 22:51:36 -07001755bnx2_send_heart_beat(struct bnx2 *bp)
1756{
1757 u32 msg;
1758 u32 addr;
1759
1760 spin_lock(&bp->indirect_lock);
1761 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1762 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1763 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1764 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1765 spin_unlock(&bp->indirect_lock);
1766}
1767
1768static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001769bnx2_remote_phy_event(struct bnx2 *bp)
1770{
1771 u32 msg;
1772 u8 link_up = bp->link_up;
1773 u8 old_port;
1774
Michael Chan2726d6e2008-01-29 21:35:05 -08001775 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
Michael Chan0d8a6572007-07-07 22:49:43 -07001776
Michael Chandf149d72007-07-07 22:51:36 -07001777 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1778 bnx2_send_heart_beat(bp);
1779
1780 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1781
Michael Chan0d8a6572007-07-07 22:49:43 -07001782 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1783 bp->link_up = 0;
1784 else {
1785 u32 speed;
1786
1787 bp->link_up = 1;
1788 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1789 bp->duplex = DUPLEX_FULL;
1790 switch (speed) {
1791 case BNX2_LINK_STATUS_10HALF:
1792 bp->duplex = DUPLEX_HALF;
1793 case BNX2_LINK_STATUS_10FULL:
1794 bp->line_speed = SPEED_10;
1795 break;
1796 case BNX2_LINK_STATUS_100HALF:
1797 bp->duplex = DUPLEX_HALF;
1798 case BNX2_LINK_STATUS_100BASE_T4:
1799 case BNX2_LINK_STATUS_100FULL:
1800 bp->line_speed = SPEED_100;
1801 break;
1802 case BNX2_LINK_STATUS_1000HALF:
1803 bp->duplex = DUPLEX_HALF;
1804 case BNX2_LINK_STATUS_1000FULL:
1805 bp->line_speed = SPEED_1000;
1806 break;
1807 case BNX2_LINK_STATUS_2500HALF:
1808 bp->duplex = DUPLEX_HALF;
1809 case BNX2_LINK_STATUS_2500FULL:
1810 bp->line_speed = SPEED_2500;
1811 break;
1812 default:
1813 bp->line_speed = 0;
1814 break;
1815 }
1816
Michael Chan0d8a6572007-07-07 22:49:43 -07001817 bp->flow_ctrl = 0;
1818 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1819 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1820 if (bp->duplex == DUPLEX_FULL)
1821 bp->flow_ctrl = bp->req_flow_ctrl;
1822 } else {
1823 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1824 bp->flow_ctrl |= FLOW_CTRL_TX;
1825 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1826 bp->flow_ctrl |= FLOW_CTRL_RX;
1827 }
1828
1829 old_port = bp->phy_port;
1830 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1831 bp->phy_port = PORT_FIBRE;
1832 else
1833 bp->phy_port = PORT_TP;
1834
1835 if (old_port != bp->phy_port)
1836 bnx2_set_default_link(bp);
1837
Michael Chan0d8a6572007-07-07 22:49:43 -07001838 }
1839 if (bp->link_up != link_up)
1840 bnx2_report_link(bp);
1841
1842 bnx2_set_mac_link(bp);
1843}
1844
1845static int
1846bnx2_set_remote_link(struct bnx2 *bp)
1847{
1848 u32 evt_code;
1849
Michael Chan2726d6e2008-01-29 21:35:05 -08001850 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07001851 switch (evt_code) {
1852 case BNX2_FW_EVT_CODE_LINK_EVENT:
1853 bnx2_remote_phy_event(bp);
1854 break;
1855 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1856 default:
Michael Chandf149d72007-07-07 22:51:36 -07001857 bnx2_send_heart_beat(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07001858 break;
1859 }
1860 return 0;
1861}
1862
Michael Chanb6016b72005-05-26 13:03:09 -07001863static int
1864bnx2_setup_copper_phy(struct bnx2 *bp)
1865{
1866 u32 bmcr;
1867 u32 new_bmcr;
1868
Michael Chanca58c3a2007-05-03 13:22:52 -07001869 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001870
1871 if (bp->autoneg & AUTONEG_SPEED) {
1872 u32 adv_reg, adv1000_reg;
1873 u32 new_adv_reg = 0;
1874 u32 new_adv1000_reg = 0;
1875
Michael Chanca58c3a2007-05-03 13:22:52 -07001876 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001877 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1878 ADVERTISE_PAUSE_ASYM);
1879
1880 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1881 adv1000_reg &= PHY_ALL_1000_SPEED;
1882
1883 if (bp->advertising & ADVERTISED_10baseT_Half)
1884 new_adv_reg |= ADVERTISE_10HALF;
1885 if (bp->advertising & ADVERTISED_10baseT_Full)
1886 new_adv_reg |= ADVERTISE_10FULL;
1887 if (bp->advertising & ADVERTISED_100baseT_Half)
1888 new_adv_reg |= ADVERTISE_100HALF;
1889 if (bp->advertising & ADVERTISED_100baseT_Full)
1890 new_adv_reg |= ADVERTISE_100FULL;
1891 if (bp->advertising & ADVERTISED_1000baseT_Full)
1892 new_adv1000_reg |= ADVERTISE_1000FULL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001893
Michael Chanb6016b72005-05-26 13:03:09 -07001894 new_adv_reg |= ADVERTISE_CSMA;
1895
1896 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1897
1898 if ((adv1000_reg != new_adv1000_reg) ||
1899 (adv_reg != new_adv_reg) ||
1900 ((bmcr & BMCR_ANENABLE) == 0)) {
1901
Michael Chanca58c3a2007-05-03 13:22:52 -07001902 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001903 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
Michael Chanca58c3a2007-05-03 13:22:52 -07001904 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07001905 BMCR_ANENABLE);
1906 }
1907 else if (bp->link_up) {
1908 /* Flow ctrl may have changed from auto to forced */
1909 /* or vice-versa. */
1910
1911 bnx2_resolve_flow_ctrl(bp);
1912 bnx2_set_mac_link(bp);
1913 }
1914 return 0;
1915 }
1916
1917 new_bmcr = 0;
1918 if (bp->req_line_speed == SPEED_100) {
1919 new_bmcr |= BMCR_SPEED100;
1920 }
1921 if (bp->req_duplex == DUPLEX_FULL) {
1922 new_bmcr |= BMCR_FULLDPLX;
1923 }
1924 if (new_bmcr != bmcr) {
1925 u32 bmsr;
Michael Chanb6016b72005-05-26 13:03:09 -07001926
Michael Chanca58c3a2007-05-03 13:22:52 -07001927 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1928 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001929
Michael Chanb6016b72005-05-26 13:03:09 -07001930 if (bmsr & BMSR_LSTATUS) {
1931 /* Force link down */
Michael Chanca58c3a2007-05-03 13:22:52 -07001932 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chana16dda02006-11-19 14:08:56 -08001933 spin_unlock_bh(&bp->phy_lock);
1934 msleep(50);
1935 spin_lock_bh(&bp->phy_lock);
1936
Michael Chanca58c3a2007-05-03 13:22:52 -07001937 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1938 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chanb6016b72005-05-26 13:03:09 -07001939 }
1940
Michael Chanca58c3a2007-05-03 13:22:52 -07001941 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001942
1943 /* Normally, the new speed is setup after the link has
1944 * gone down and up again. In some cases, link will not go
1945 * down so we need to set up the new speed here.
1946 */
1947 if (bmsr & BMSR_LSTATUS) {
1948 bp->line_speed = bp->req_line_speed;
1949 bp->duplex = bp->req_duplex;
1950 bnx2_resolve_flow_ctrl(bp);
1951 bnx2_set_mac_link(bp);
1952 }
Michael Chan27a005b2007-05-03 13:23:41 -07001953 } else {
1954 bnx2_resolve_flow_ctrl(bp);
1955 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001956 }
1957 return 0;
1958}
1959
1960static int
Michael Chan0d8a6572007-07-07 22:49:43 -07001961bnx2_setup_phy(struct bnx2 *bp, u8 port)
Michael Chanb6016b72005-05-26 13:03:09 -07001962{
1963 if (bp->loopback == MAC_LOOPBACK)
1964 return 0;
1965
Michael Chan583c28e2008-01-21 19:51:35 -08001966 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan0d8a6572007-07-07 22:49:43 -07001967 return (bnx2_setup_serdes_phy(bp, port));
Michael Chanb6016b72005-05-26 13:03:09 -07001968 }
1969 else {
1970 return (bnx2_setup_copper_phy(bp));
1971 }
1972}
1973
1974static int
Michael Chan9a120bc2008-05-16 22:17:45 -07001975bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
Michael Chan27a005b2007-05-03 13:23:41 -07001976{
1977 u32 val;
1978
1979 bp->mii_bmcr = MII_BMCR + 0x10;
1980 bp->mii_bmsr = MII_BMSR + 0x10;
1981 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1982 bp->mii_adv = MII_ADVERTISE + 0x10;
1983 bp->mii_lpa = MII_LPA + 0x10;
1984 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1985
1986 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1987 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1988
1989 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
Michael Chan9a120bc2008-05-16 22:17:45 -07001990 if (reset_phy)
1991 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07001992
1993 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1994
1995 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1996 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1997 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1998 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1999
2000 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2001 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
Michael Chan583c28e2008-01-21 19:51:35 -08002002 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan27a005b2007-05-03 13:23:41 -07002003 val |= BCM5708S_UP1_2G5;
2004 else
2005 val &= ~BCM5708S_UP1_2G5;
2006 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2007
2008 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2009 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2010 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2011 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2012
2013 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2014
2015 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2016 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2017 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2018
2019 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2020
2021 return 0;
2022}
2023
2024static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002025bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
Michael Chan5b0c76a2005-11-04 08:45:49 -08002026{
2027 u32 val;
2028
Michael Chan9a120bc2008-05-16 22:17:45 -07002029 if (reset_phy)
2030 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002031
2032 bp->mii_up1 = BCM5708S_UP1;
2033
Michael Chan5b0c76a2005-11-04 08:45:49 -08002034 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2035 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2036 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2037
2038 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2039 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2040 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2041
2042 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2043 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2044 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2045
Michael Chan583c28e2008-01-21 19:51:35 -08002046 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002047 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2048 val |= BCM5708S_UP1_2G5;
2049 bnx2_write_phy(bp, BCM5708S_UP1, val);
2050 }
2051
2052 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
Michael Chandda1e392006-01-23 16:08:14 -08002053 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2054 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002055 /* increase tx signal amplitude */
2056 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2057 BCM5708S_BLK_ADDR_TX_MISC);
2058 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2059 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2060 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2061 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2062 }
2063
Michael Chan2726d6e2008-01-29 21:35:05 -08002064 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
Michael Chan5b0c76a2005-11-04 08:45:49 -08002065 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2066
2067 if (val) {
2068 u32 is_backplane;
2069
Michael Chan2726d6e2008-01-29 21:35:05 -08002070 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan5b0c76a2005-11-04 08:45:49 -08002071 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2072 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2073 BCM5708S_BLK_ADDR_TX_MISC);
2074 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2075 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2076 BCM5708S_BLK_ADDR_DIG);
2077 }
2078 }
2079 return 0;
2080}
2081
2082static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002083bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07002084{
Michael Chan9a120bc2008-05-16 22:17:45 -07002085 if (reset_phy)
2086 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002087
Michael Chan583c28e2008-01-21 19:51:35 -08002088 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb6016b72005-05-26 13:03:09 -07002089
Michael Chan59b47d82006-11-19 14:10:45 -08002090 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2091 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
Michael Chanb6016b72005-05-26 13:03:09 -07002092
2093 if (bp->dev->mtu > 1500) {
2094 u32 val;
2095
2096 /* Set extended packet length bit */
2097 bnx2_write_phy(bp, 0x18, 0x7);
2098 bnx2_read_phy(bp, 0x18, &val);
2099 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2100
2101 bnx2_write_phy(bp, 0x1c, 0x6c00);
2102 bnx2_read_phy(bp, 0x1c, &val);
2103 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2104 }
2105 else {
2106 u32 val;
2107
2108 bnx2_write_phy(bp, 0x18, 0x7);
2109 bnx2_read_phy(bp, 0x18, &val);
2110 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2111
2112 bnx2_write_phy(bp, 0x1c, 0x6c00);
2113 bnx2_read_phy(bp, 0x1c, &val);
2114 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2115 }
2116
2117 return 0;
2118}
2119
2120static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002121bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07002122{
Michael Chan5b0c76a2005-11-04 08:45:49 -08002123 u32 val;
2124
Michael Chan9a120bc2008-05-16 22:17:45 -07002125 if (reset_phy)
2126 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002127
Michael Chan583c28e2008-01-21 19:51:35 -08002128 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07002129 bnx2_write_phy(bp, 0x18, 0x0c00);
2130 bnx2_write_phy(bp, 0x17, 0x000a);
2131 bnx2_write_phy(bp, 0x15, 0x310b);
2132 bnx2_write_phy(bp, 0x17, 0x201f);
2133 bnx2_write_phy(bp, 0x15, 0x9506);
2134 bnx2_write_phy(bp, 0x17, 0x401f);
2135 bnx2_write_phy(bp, 0x15, 0x14e2);
2136 bnx2_write_phy(bp, 0x18, 0x0400);
2137 }
2138
Michael Chan583c28e2008-01-21 19:51:35 -08002139 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
Michael Chanb659f442007-02-02 00:46:35 -08002140 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2141 MII_BNX2_DSP_EXPAND_REG | 0x8);
2142 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2143 val &= ~(1 << 8);
2144 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2145 }
2146
Michael Chanb6016b72005-05-26 13:03:09 -07002147 if (bp->dev->mtu > 1500) {
Michael Chanb6016b72005-05-26 13:03:09 -07002148 /* Set extended packet length bit */
2149 bnx2_write_phy(bp, 0x18, 0x7);
2150 bnx2_read_phy(bp, 0x18, &val);
2151 bnx2_write_phy(bp, 0x18, val | 0x4000);
2152
2153 bnx2_read_phy(bp, 0x10, &val);
2154 bnx2_write_phy(bp, 0x10, val | 0x1);
2155 }
2156 else {
Michael Chanb6016b72005-05-26 13:03:09 -07002157 bnx2_write_phy(bp, 0x18, 0x7);
2158 bnx2_read_phy(bp, 0x18, &val);
2159 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2160
2161 bnx2_read_phy(bp, 0x10, &val);
2162 bnx2_write_phy(bp, 0x10, val & ~0x1);
2163 }
2164
Michael Chan5b0c76a2005-11-04 08:45:49 -08002165 /* ethernet@wirespeed */
2166 bnx2_write_phy(bp, 0x18, 0x7007);
2167 bnx2_read_phy(bp, 0x18, &val);
2168 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
Michael Chanb6016b72005-05-26 13:03:09 -07002169 return 0;
2170}
2171
2172
2173static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002174bnx2_init_phy(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07002175{
2176 u32 val;
2177 int rc = 0;
2178
Michael Chan583c28e2008-01-21 19:51:35 -08002179 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2180 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
Michael Chanb6016b72005-05-26 13:03:09 -07002181
Michael Chanca58c3a2007-05-03 13:22:52 -07002182 bp->mii_bmcr = MII_BMCR;
2183 bp->mii_bmsr = MII_BMSR;
Michael Chan27a005b2007-05-03 13:23:41 -07002184 bp->mii_bmsr1 = MII_BMSR;
Michael Chanca58c3a2007-05-03 13:22:52 -07002185 bp->mii_adv = MII_ADVERTISE;
2186 bp->mii_lpa = MII_LPA;
2187
Michael Chanb6016b72005-05-26 13:03:09 -07002188 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2189
Michael Chan583c28e2008-01-21 19:51:35 -08002190 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07002191 goto setup_phy;
2192
Michael Chanb6016b72005-05-26 13:03:09 -07002193 bnx2_read_phy(bp, MII_PHYSID1, &val);
2194 bp->phy_id = val << 16;
2195 bnx2_read_phy(bp, MII_PHYSID2, &val);
2196 bp->phy_id |= val & 0xffff;
2197
Michael Chan583c28e2008-01-21 19:51:35 -08002198 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002199 if (CHIP_NUM(bp) == CHIP_NUM_5706)
Michael Chan9a120bc2008-05-16 22:17:45 -07002200 rc = bnx2_init_5706s_phy(bp, reset_phy);
Michael Chan5b0c76a2005-11-04 08:45:49 -08002201 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
Michael Chan9a120bc2008-05-16 22:17:45 -07002202 rc = bnx2_init_5708s_phy(bp, reset_phy);
Michael Chan27a005b2007-05-03 13:23:41 -07002203 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chan9a120bc2008-05-16 22:17:45 -07002204 rc = bnx2_init_5709s_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07002205 }
2206 else {
Michael Chan9a120bc2008-05-16 22:17:45 -07002207 rc = bnx2_init_copper_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07002208 }
2209
Michael Chan0d8a6572007-07-07 22:49:43 -07002210setup_phy:
2211 if (!rc)
2212 rc = bnx2_setup_phy(bp, bp->phy_port);
Michael Chanb6016b72005-05-26 13:03:09 -07002213
2214 return rc;
2215}
2216
2217static int
2218bnx2_set_mac_loopback(struct bnx2 *bp)
2219{
2220 u32 mac_mode;
2221
2222 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2223 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2224 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2225 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2226 bp->link_up = 1;
2227 return 0;
2228}
2229
Michael Chanbc5a0692006-01-23 16:13:22 -08002230static int bnx2_test_link(struct bnx2 *);
2231
2232static int
2233bnx2_set_phy_loopback(struct bnx2 *bp)
2234{
2235 u32 mac_mode;
2236 int rc, i;
2237
2238 spin_lock_bh(&bp->phy_lock);
Michael Chanca58c3a2007-05-03 13:22:52 -07002239 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
Michael Chanbc5a0692006-01-23 16:13:22 -08002240 BMCR_SPEED1000);
2241 spin_unlock_bh(&bp->phy_lock);
2242 if (rc)
2243 return rc;
2244
2245 for (i = 0; i < 10; i++) {
2246 if (bnx2_test_link(bp) == 0)
2247 break;
Michael Chan80be4432006-11-19 14:07:28 -08002248 msleep(100);
Michael Chanbc5a0692006-01-23 16:13:22 -08002249 }
2250
2251 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2252 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2253 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08002254 BNX2_EMAC_MODE_25G_MODE);
Michael Chanbc5a0692006-01-23 16:13:22 -08002255
2256 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2257 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2258 bp->link_up = 1;
2259 return 0;
2260}
2261
Michael Chanb6016b72005-05-26 13:03:09 -07002262static int
Michael Chana2f13892008-07-14 22:38:23 -07002263bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
Michael Chanb6016b72005-05-26 13:03:09 -07002264{
2265 int i;
2266 u32 val;
2267
Michael Chanb6016b72005-05-26 13:03:09 -07002268 bp->fw_wr_seq++;
2269 msg_data |= bp->fw_wr_seq;
2270
Michael Chan2726d6e2008-01-29 21:35:05 -08002271 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002272
Michael Chana2f13892008-07-14 22:38:23 -07002273 if (!ack)
2274 return 0;
2275
Michael Chanb6016b72005-05-26 13:03:09 -07002276 /* wait for an acknowledgement. */
Michael Chanb090ae22006-01-23 16:07:10 -08002277 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2278 msleep(10);
Michael Chanb6016b72005-05-26 13:03:09 -07002279
Michael Chan2726d6e2008-01-29 21:35:05 -08002280 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
Michael Chanb6016b72005-05-26 13:03:09 -07002281
2282 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2283 break;
2284 }
Michael Chanb090ae22006-01-23 16:07:10 -08002285 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2286 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002287
2288 /* If we timed out, inform the firmware that this is the case. */
Michael Chanb090ae22006-01-23 16:07:10 -08002289 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2290 if (!silent)
2291 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2292 "%x\n", msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002293
2294 msg_data &= ~BNX2_DRV_MSG_CODE;
2295 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2296
Michael Chan2726d6e2008-01-29 21:35:05 -08002297 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002298
Michael Chanb6016b72005-05-26 13:03:09 -07002299 return -EBUSY;
2300 }
2301
Michael Chanb090ae22006-01-23 16:07:10 -08002302 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2303 return -EIO;
2304
Michael Chanb6016b72005-05-26 13:03:09 -07002305 return 0;
2306}
2307
Michael Chan59b47d82006-11-19 14:10:45 -08002308static int
2309bnx2_init_5709_context(struct bnx2 *bp)
2310{
2311 int i, ret = 0;
2312 u32 val;
2313
2314 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2315 val |= (BCM_PAGE_BITS - 8) << 16;
2316 REG_WR(bp, BNX2_CTX_COMMAND, val);
Michael Chan641bdcd2007-06-04 21:22:24 -07002317 for (i = 0; i < 10; i++) {
2318 val = REG_RD(bp, BNX2_CTX_COMMAND);
2319 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2320 break;
2321 udelay(2);
2322 }
2323 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2324 return -EBUSY;
2325
Michael Chan59b47d82006-11-19 14:10:45 -08002326 for (i = 0; i < bp->ctx_pages; i++) {
2327 int j;
2328
Michael Chan352f7682008-05-02 16:57:26 -07002329 if (bp->ctx_blk[i])
2330 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2331 else
2332 return -ENOMEM;
2333
Michael Chan59b47d82006-11-19 14:10:45 -08002334 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2335 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2336 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2337 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2338 (u64) bp->ctx_blk_mapping[i] >> 32);
2339 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2340 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2341 for (j = 0; j < 10; j++) {
2342
2343 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2344 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2345 break;
2346 udelay(5);
2347 }
2348 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2349 ret = -EBUSY;
2350 break;
2351 }
2352 }
2353 return ret;
2354}
2355
Michael Chanb6016b72005-05-26 13:03:09 -07002356static void
2357bnx2_init_context(struct bnx2 *bp)
2358{
2359 u32 vcid;
2360
2361 vcid = 96;
2362 while (vcid) {
2363 u32 vcid_addr, pcid_addr, offset;
Michael Chan7947b202007-06-04 21:17:10 -07002364 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07002365
2366 vcid--;
2367
2368 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2369 u32 new_vcid;
2370
2371 vcid_addr = GET_PCID_ADDR(vcid);
2372 if (vcid & 0x8) {
2373 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2374 }
2375 else {
2376 new_vcid = vcid;
2377 }
2378 pcid_addr = GET_PCID_ADDR(new_vcid);
2379 }
2380 else {
2381 vcid_addr = GET_CID_ADDR(vcid);
2382 pcid_addr = vcid_addr;
2383 }
2384
Michael Chan7947b202007-06-04 21:17:10 -07002385 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2386 vcid_addr += (i << PHY_CTX_SHIFT);
2387 pcid_addr += (i << PHY_CTX_SHIFT);
Michael Chanb6016b72005-05-26 13:03:09 -07002388
Michael Chan5d5d0012007-12-12 11:17:43 -08002389 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
Michael Chan7947b202007-06-04 21:17:10 -07002390 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2391
2392 /* Zero out the context. */
2393 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
Michael Chan62a83132008-01-29 21:35:40 -08002394 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07002395 }
Michael Chanb6016b72005-05-26 13:03:09 -07002396 }
2397}
2398
2399static int
2400bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2401{
2402 u16 *good_mbuf;
2403 u32 good_mbuf_cnt;
2404 u32 val;
2405
2406 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2407 if (good_mbuf == NULL) {
2408 printk(KERN_ERR PFX "Failed to allocate memory in "
2409 "bnx2_alloc_bad_rbuf\n");
2410 return -ENOMEM;
2411 }
2412
2413 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2414 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2415
2416 good_mbuf_cnt = 0;
2417
2418 /* Allocate a bunch of mbufs and save the good ones in an array. */
Michael Chan2726d6e2008-01-29 21:35:05 -08002419 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002420 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
Michael Chan2726d6e2008-01-29 21:35:05 -08002421 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2422 BNX2_RBUF_COMMAND_ALLOC_REQ);
Michael Chanb6016b72005-05-26 13:03:09 -07002423
Michael Chan2726d6e2008-01-29 21:35:05 -08002424 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
Michael Chanb6016b72005-05-26 13:03:09 -07002425
2426 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2427
2428 /* The addresses with Bit 9 set are bad memory blocks. */
2429 if (!(val & (1 << 9))) {
2430 good_mbuf[good_mbuf_cnt] = (u16) val;
2431 good_mbuf_cnt++;
2432 }
2433
Michael Chan2726d6e2008-01-29 21:35:05 -08002434 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002435 }
2436
2437 /* Free the good ones back to the mbuf pool thus discarding
2438 * all the bad ones. */
2439 while (good_mbuf_cnt) {
2440 good_mbuf_cnt--;
2441
2442 val = good_mbuf[good_mbuf_cnt];
2443 val = (val << 9) | val | 1;
2444
Michael Chan2726d6e2008-01-29 21:35:05 -08002445 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
Michael Chanb6016b72005-05-26 13:03:09 -07002446 }
2447 kfree(good_mbuf);
2448 return 0;
2449}
2450
2451static void
Benjamin Li5fcaed02008-07-14 22:39:52 -07002452bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
Michael Chanb6016b72005-05-26 13:03:09 -07002453{
2454 u32 val;
Michael Chanb6016b72005-05-26 13:03:09 -07002455
2456 val = (mac_addr[0] << 8) | mac_addr[1];
2457
Benjamin Li5fcaed02008-07-14 22:39:52 -07002458 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
Michael Chanb6016b72005-05-26 13:03:09 -07002459
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002460 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
Michael Chanb6016b72005-05-26 13:03:09 -07002461 (mac_addr[4] << 8) | mac_addr[5];
2462
Benjamin Li5fcaed02008-07-14 22:39:52 -07002463 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
Michael Chanb6016b72005-05-26 13:03:09 -07002464}
2465
2466static inline int
Michael Chanbb4f98a2008-06-19 16:38:19 -07002467bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chan47bf4242007-12-12 11:19:12 -08002468{
2469 dma_addr_t mapping;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002470 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
Michael Chan47bf4242007-12-12 11:19:12 -08002471 struct rx_bd *rxbd =
Michael Chanbb4f98a2008-06-19 16:38:19 -07002472 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
Michael Chan47bf4242007-12-12 11:19:12 -08002473 struct page *page = alloc_page(GFP_ATOMIC);
2474
2475 if (!page)
2476 return -ENOMEM;
2477 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2478 PCI_DMA_FROMDEVICE);
2479 rx_pg->page = page;
2480 pci_unmap_addr_set(rx_pg, mapping, mapping);
2481 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2482 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2483 return 0;
2484}
2485
2486static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002487bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chan47bf4242007-12-12 11:19:12 -08002488{
Michael Chanbb4f98a2008-06-19 16:38:19 -07002489 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
Michael Chan47bf4242007-12-12 11:19:12 -08002490 struct page *page = rx_pg->page;
2491
2492 if (!page)
2493 return;
2494
2495 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2496 PCI_DMA_FROMDEVICE);
2497
2498 __free_page(page);
2499 rx_pg->page = NULL;
2500}
2501
2502static inline int
Michael Chanbb4f98a2008-06-19 16:38:19 -07002503bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chanb6016b72005-05-26 13:03:09 -07002504{
2505 struct sk_buff *skb;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002506 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
Michael Chanb6016b72005-05-26 13:03:09 -07002507 dma_addr_t mapping;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002508 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
Michael Chanb6016b72005-05-26 13:03:09 -07002509 unsigned long align;
2510
Michael Chan932f3772006-08-15 01:39:36 -07002511 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
Michael Chanb6016b72005-05-26 13:03:09 -07002512 if (skb == NULL) {
2513 return -ENOMEM;
2514 }
2515
Michael Chan59b47d82006-11-19 14:10:45 -08002516 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2517 skb_reserve(skb, BNX2_RX_ALIGN - align);
Michael Chanb6016b72005-05-26 13:03:09 -07002518
Michael Chanb6016b72005-05-26 13:03:09 -07002519 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2520 PCI_DMA_FROMDEVICE);
2521
2522 rx_buf->skb = skb;
2523 pci_unmap_addr_set(rx_buf, mapping, mapping);
2524
2525 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2526 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2527
Michael Chanbb4f98a2008-06-19 16:38:19 -07002528 rxr->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chanb6016b72005-05-26 13:03:09 -07002529
2530 return 0;
2531}
2532
Michael Chanda3e4fb2007-05-03 13:24:23 -07002533static int
Michael Chan35efa7c2007-12-20 19:56:37 -08002534bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
Michael Chanda3e4fb2007-05-03 13:24:23 -07002535{
Michael Chan43e80b82008-06-19 16:41:08 -07002536 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanda3e4fb2007-05-03 13:24:23 -07002537 u32 new_link_state, old_link_state;
2538 int is_set = 1;
2539
2540 new_link_state = sblk->status_attn_bits & event;
2541 old_link_state = sblk->status_attn_bits_ack & event;
2542 if (new_link_state != old_link_state) {
2543 if (new_link_state)
2544 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2545 else
2546 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2547 } else
2548 is_set = 0;
2549
2550 return is_set;
2551}
2552
Michael Chanb6016b72005-05-26 13:03:09 -07002553static void
Michael Chan35efa7c2007-12-20 19:56:37 -08002554bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chanb6016b72005-05-26 13:03:09 -07002555{
Michael Chan74ecc622008-05-02 16:56:16 -07002556 spin_lock(&bp->phy_lock);
2557
2558 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
Michael Chanb6016b72005-05-26 13:03:09 -07002559 bnx2_set_link(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08002560 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
Michael Chan0d8a6572007-07-07 22:49:43 -07002561 bnx2_set_remote_link(bp);
2562
Michael Chan74ecc622008-05-02 16:56:16 -07002563 spin_unlock(&bp->phy_lock);
2564
Michael Chanb6016b72005-05-26 13:03:09 -07002565}
2566
Michael Chanead72702007-12-20 19:55:39 -08002567static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08002568bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
Michael Chanead72702007-12-20 19:55:39 -08002569{
2570 u16 cons;
2571
Michael Chan43e80b82008-06-19 16:41:08 -07002572 /* Tell compiler that status block fields can change. */
2573 barrier();
2574 cons = *bnapi->hw_tx_cons_ptr;
Michael Chanead72702007-12-20 19:55:39 -08002575 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2576 cons++;
2577 return cons;
2578}
2579
Michael Chan57851d82007-12-20 20:01:44 -08002580static int
2581bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07002582{
Michael Chan35e90102008-06-19 16:37:42 -07002583 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07002584 u16 hw_cons, sw_cons, sw_ring_cons;
Benjamin Li706bf242008-07-18 17:55:11 -07002585 int tx_pkt = 0, index;
2586 struct netdev_queue *txq;
2587
2588 index = (bnapi - bp->bnx2_napi);
2589 txq = netdev_get_tx_queue(bp->dev, index);
Michael Chanb6016b72005-05-26 13:03:09 -07002590
Michael Chan35efa7c2007-12-20 19:56:37 -08002591 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chan35e90102008-06-19 16:37:42 -07002592 sw_cons = txr->tx_cons;
Michael Chanb6016b72005-05-26 13:03:09 -07002593
2594 while (sw_cons != hw_cons) {
2595 struct sw_bd *tx_buf;
2596 struct sk_buff *skb;
2597 int i, last;
2598
2599 sw_ring_cons = TX_RING_IDX(sw_cons);
2600
Michael Chan35e90102008-06-19 16:37:42 -07002601 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
Michael Chanb6016b72005-05-26 13:03:09 -07002602 skb = tx_buf->skb;
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002603
Michael Chanb6016b72005-05-26 13:03:09 -07002604 /* partial BD completions possible with TSO packets */
Herbert Xu89114af2006-07-08 13:34:32 -07002605 if (skb_is_gso(skb)) {
Michael Chanb6016b72005-05-26 13:03:09 -07002606 u16 last_idx, last_ring_idx;
2607
2608 last_idx = sw_cons +
2609 skb_shinfo(skb)->nr_frags + 1;
2610 last_ring_idx = sw_ring_cons +
2611 skb_shinfo(skb)->nr_frags + 1;
2612 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2613 last_idx++;
2614 }
2615 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2616 break;
2617 }
2618 }
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002619
Michael Chanb6016b72005-05-26 13:03:09 -07002620 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2621 skb_headlen(skb), PCI_DMA_TODEVICE);
2622
2623 tx_buf->skb = NULL;
2624 last = skb_shinfo(skb)->nr_frags;
2625
2626 for (i = 0; i < last; i++) {
2627 sw_cons = NEXT_TX_BD(sw_cons);
2628
2629 pci_unmap_page(bp->pdev,
2630 pci_unmap_addr(
Michael Chan35e90102008-06-19 16:37:42 -07002631 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
Michael Chanb6016b72005-05-26 13:03:09 -07002632 mapping),
2633 skb_shinfo(skb)->frags[i].size,
2634 PCI_DMA_TODEVICE);
2635 }
2636
2637 sw_cons = NEXT_TX_BD(sw_cons);
2638
Michael Chan745720e2006-06-29 12:37:41 -07002639 dev_kfree_skb(skb);
Michael Chan57851d82007-12-20 20:01:44 -08002640 tx_pkt++;
2641 if (tx_pkt == budget)
2642 break;
Michael Chanb6016b72005-05-26 13:03:09 -07002643
Michael Chan35efa7c2007-12-20 19:56:37 -08002644 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07002645 }
2646
Michael Chan35e90102008-06-19 16:37:42 -07002647 txr->hw_tx_cons = hw_cons;
2648 txr->tx_cons = sw_cons;
Benjamin Li706bf242008-07-18 17:55:11 -07002649
Michael Chan2f8af122006-08-15 01:39:10 -07002650 /* Need to make the tx_cons update visible to bnx2_start_xmit()
Benjamin Li706bf242008-07-18 17:55:11 -07002651 * before checking for netif_tx_queue_stopped(). Without the
Michael Chan2f8af122006-08-15 01:39:10 -07002652 * memory barrier, there is a small possibility that bnx2_start_xmit()
2653 * will miss it and cause the queue to be stopped forever.
2654 */
2655 smp_mb();
Michael Chanb6016b72005-05-26 13:03:09 -07002656
Benjamin Li706bf242008-07-18 17:55:11 -07002657 if (unlikely(netif_tx_queue_stopped(txq)) &&
Michael Chan35e90102008-06-19 16:37:42 -07002658 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
Benjamin Li706bf242008-07-18 17:55:11 -07002659 __netif_tx_lock(txq, smp_processor_id());
2660 if ((netif_tx_queue_stopped(txq)) &&
Michael Chan35e90102008-06-19 16:37:42 -07002661 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
Benjamin Li706bf242008-07-18 17:55:11 -07002662 netif_tx_wake_queue(txq);
2663 __netif_tx_unlock(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07002664 }
Benjamin Li706bf242008-07-18 17:55:11 -07002665
Michael Chan57851d82007-12-20 20:01:44 -08002666 return tx_pkt;
Michael Chanb6016b72005-05-26 13:03:09 -07002667}
2668
Michael Chan1db82f22007-12-12 11:19:35 -08002669static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002670bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
Michael Chana1f60192007-12-20 19:57:19 -08002671 struct sk_buff *skb, int count)
Michael Chan1db82f22007-12-12 11:19:35 -08002672{
2673 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2674 struct rx_bd *cons_bd, *prod_bd;
2675 dma_addr_t mapping;
2676 int i;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002677 u16 hw_prod = rxr->rx_pg_prod, prod;
2678 u16 cons = rxr->rx_pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002679
2680 for (i = 0; i < count; i++) {
2681 prod = RX_PG_RING_IDX(hw_prod);
2682
Michael Chanbb4f98a2008-06-19 16:38:19 -07002683 prod_rx_pg = &rxr->rx_pg_ring[prod];
2684 cons_rx_pg = &rxr->rx_pg_ring[cons];
2685 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2686 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
Michael Chan1db82f22007-12-12 11:19:35 -08002687
2688 if (i == 0 && skb) {
2689 struct page *page;
2690 struct skb_shared_info *shinfo;
2691
2692 shinfo = skb_shinfo(skb);
2693 shinfo->nr_frags--;
2694 page = shinfo->frags[shinfo->nr_frags].page;
2695 shinfo->frags[shinfo->nr_frags].page = NULL;
2696 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2697 PCI_DMA_FROMDEVICE);
2698 cons_rx_pg->page = page;
2699 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2700 dev_kfree_skb(skb);
2701 }
2702 if (prod != cons) {
2703 prod_rx_pg->page = cons_rx_pg->page;
2704 cons_rx_pg->page = NULL;
2705 pci_unmap_addr_set(prod_rx_pg, mapping,
2706 pci_unmap_addr(cons_rx_pg, mapping));
2707
2708 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2709 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2710
2711 }
2712 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2713 hw_prod = NEXT_RX_BD(hw_prod);
2714 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07002715 rxr->rx_pg_prod = hw_prod;
2716 rxr->rx_pg_cons = cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002717}
2718
Michael Chanb6016b72005-05-26 13:03:09 -07002719static inline void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002720bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2721 struct sk_buff *skb, u16 cons, u16 prod)
Michael Chanb6016b72005-05-26 13:03:09 -07002722{
Michael Chan236b6392006-03-20 17:49:02 -08002723 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2724 struct rx_bd *cons_bd, *prod_bd;
2725
Michael Chanbb4f98a2008-06-19 16:38:19 -07002726 cons_rx_buf = &rxr->rx_buf_ring[cons];
2727 prod_rx_buf = &rxr->rx_buf_ring[prod];
Michael Chanb6016b72005-05-26 13:03:09 -07002728
2729 pci_dma_sync_single_for_device(bp->pdev,
2730 pci_unmap_addr(cons_rx_buf, mapping),
Benjamin Li601d3d12008-05-16 22:19:35 -07002731 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002732
Michael Chanbb4f98a2008-06-19 16:38:19 -07002733 rxr->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chan236b6392006-03-20 17:49:02 -08002734
2735 prod_rx_buf->skb = skb;
2736
2737 if (cons == prod)
2738 return;
2739
Michael Chanb6016b72005-05-26 13:03:09 -07002740 pci_unmap_addr_set(prod_rx_buf, mapping,
2741 pci_unmap_addr(cons_rx_buf, mapping));
2742
Michael Chanbb4f98a2008-06-19 16:38:19 -07002743 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2744 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
Michael Chan236b6392006-03-20 17:49:02 -08002745 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2746 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
Michael Chanb6016b72005-05-26 13:03:09 -07002747}
2748
Michael Chan85833c62007-12-12 11:17:01 -08002749static int
Michael Chanbb4f98a2008-06-19 16:38:19 -07002750bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
Michael Chana1f60192007-12-20 19:57:19 -08002751 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2752 u32 ring_idx)
Michael Chan85833c62007-12-12 11:17:01 -08002753{
2754 int err;
2755 u16 prod = ring_idx & 0xffff;
2756
Michael Chanbb4f98a2008-06-19 16:38:19 -07002757 err = bnx2_alloc_rx_skb(bp, rxr, prod);
Michael Chan85833c62007-12-12 11:17:01 -08002758 if (unlikely(err)) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07002759 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
Michael Chan1db82f22007-12-12 11:19:35 -08002760 if (hdr_len) {
2761 unsigned int raw_len = len + 4;
2762 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2763
Michael Chanbb4f98a2008-06-19 16:38:19 -07002764 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
Michael Chan1db82f22007-12-12 11:19:35 -08002765 }
Michael Chan85833c62007-12-12 11:17:01 -08002766 return err;
2767 }
2768
Benjamin Lid89cb6a2008-05-16 22:18:57 -07002769 skb_reserve(skb, BNX2_RX_OFFSET);
Michael Chan85833c62007-12-12 11:17:01 -08002770 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2771 PCI_DMA_FROMDEVICE);
2772
Michael Chan1db82f22007-12-12 11:19:35 -08002773 if (hdr_len == 0) {
2774 skb_put(skb, len);
2775 return 0;
2776 } else {
2777 unsigned int i, frag_len, frag_size, pages;
2778 struct sw_pg *rx_pg;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002779 u16 pg_cons = rxr->rx_pg_cons;
2780 u16 pg_prod = rxr->rx_pg_prod;
Michael Chan1db82f22007-12-12 11:19:35 -08002781
2782 frag_size = len + 4 - hdr_len;
2783 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2784 skb_put(skb, hdr_len);
2785
2786 for (i = 0; i < pages; i++) {
2787 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2788 if (unlikely(frag_len <= 4)) {
2789 unsigned int tail = 4 - frag_len;
2790
Michael Chanbb4f98a2008-06-19 16:38:19 -07002791 rxr->rx_pg_cons = pg_cons;
2792 rxr->rx_pg_prod = pg_prod;
2793 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
Michael Chana1f60192007-12-20 19:57:19 -08002794 pages - i);
Michael Chan1db82f22007-12-12 11:19:35 -08002795 skb->len -= tail;
2796 if (i == 0) {
2797 skb->tail -= tail;
2798 } else {
2799 skb_frag_t *frag =
2800 &skb_shinfo(skb)->frags[i - 1];
2801 frag->size -= tail;
2802 skb->data_len -= tail;
2803 skb->truesize -= tail;
2804 }
2805 return 0;
2806 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07002807 rx_pg = &rxr->rx_pg_ring[pg_cons];
Michael Chan1db82f22007-12-12 11:19:35 -08002808
2809 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2810 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2811
2812 if (i == pages - 1)
2813 frag_len -= 4;
2814
2815 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2816 rx_pg->page = NULL;
2817
Michael Chanbb4f98a2008-06-19 16:38:19 -07002818 err = bnx2_alloc_rx_page(bp, rxr,
2819 RX_PG_RING_IDX(pg_prod));
Michael Chan1db82f22007-12-12 11:19:35 -08002820 if (unlikely(err)) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07002821 rxr->rx_pg_cons = pg_cons;
2822 rxr->rx_pg_prod = pg_prod;
2823 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
Michael Chana1f60192007-12-20 19:57:19 -08002824 pages - i);
Michael Chan1db82f22007-12-12 11:19:35 -08002825 return err;
2826 }
2827
2828 frag_size -= frag_len;
2829 skb->data_len += frag_len;
2830 skb->truesize += frag_len;
2831 skb->len += frag_len;
2832
2833 pg_prod = NEXT_RX_BD(pg_prod);
2834 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2835 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07002836 rxr->rx_pg_prod = pg_prod;
2837 rxr->rx_pg_cons = pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002838 }
Michael Chan85833c62007-12-12 11:17:01 -08002839 return 0;
2840}
2841
Michael Chanc09c2622007-12-10 17:18:37 -08002842static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08002843bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
Michael Chanc09c2622007-12-10 17:18:37 -08002844{
Michael Chanbb4f98a2008-06-19 16:38:19 -07002845 u16 cons;
2846
Michael Chan43e80b82008-06-19 16:41:08 -07002847 /* Tell compiler that status block fields can change. */
2848 barrier();
2849 cons = *bnapi->hw_rx_cons_ptr;
Michael Chanc09c2622007-12-10 17:18:37 -08002850 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2851 cons++;
2852 return cons;
2853}
2854
Michael Chanb6016b72005-05-26 13:03:09 -07002855static int
Michael Chan35efa7c2007-12-20 19:56:37 -08002856bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07002857{
Michael Chanbb4f98a2008-06-19 16:38:19 -07002858 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07002859 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2860 struct l2_fhdr *rx_hdr;
Michael Chan1db82f22007-12-12 11:19:35 -08002861 int rx_pkt = 0, pg_ring_used = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002862
Michael Chan35efa7c2007-12-20 19:56:37 -08002863 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chanbb4f98a2008-06-19 16:38:19 -07002864 sw_cons = rxr->rx_cons;
2865 sw_prod = rxr->rx_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07002866
2867 /* Memory barrier necessary as speculative reads of the rx
2868 * buffer can be ahead of the index in the status block
2869 */
2870 rmb();
2871 while (sw_cons != hw_cons) {
Michael Chan1db82f22007-12-12 11:19:35 -08002872 unsigned int len, hdr_len;
Michael Chanade2bfe2006-01-23 16:09:51 -08002873 u32 status;
Michael Chanb6016b72005-05-26 13:03:09 -07002874 struct sw_bd *rx_buf;
2875 struct sk_buff *skb;
Michael Chan236b6392006-03-20 17:49:02 -08002876 dma_addr_t dma_addr;
Michael Chanf22828e2008-08-14 15:30:14 -07002877 u16 vtag = 0;
2878 int hw_vlan __maybe_unused = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002879
2880 sw_ring_cons = RX_RING_IDX(sw_cons);
2881 sw_ring_prod = RX_RING_IDX(sw_prod);
2882
Michael Chanbb4f98a2008-06-19 16:38:19 -07002883 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
Michael Chanb6016b72005-05-26 13:03:09 -07002884 skb = rx_buf->skb;
Michael Chan236b6392006-03-20 17:49:02 -08002885
2886 rx_buf->skb = NULL;
2887
2888 dma_addr = pci_unmap_addr(rx_buf, mapping);
2889
2890 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
Benjamin Li601d3d12008-05-16 22:19:35 -07002891 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2892 PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002893
2894 rx_hdr = (struct l2_fhdr *) skb->data;
Michael Chan1db82f22007-12-12 11:19:35 -08002895 len = rx_hdr->l2_fhdr_pkt_len;
Michael Chanb6016b72005-05-26 13:03:09 -07002896
Michael Chanade2bfe2006-01-23 16:09:51 -08002897 if ((status = rx_hdr->l2_fhdr_status) &
Michael Chanb6016b72005-05-26 13:03:09 -07002898 (L2_FHDR_ERRORS_BAD_CRC |
2899 L2_FHDR_ERRORS_PHY_DECODE |
2900 L2_FHDR_ERRORS_ALIGNMENT |
2901 L2_FHDR_ERRORS_TOO_SHORT |
2902 L2_FHDR_ERRORS_GIANT_FRAME)) {
2903
Michael Chanbb4f98a2008-06-19 16:38:19 -07002904 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
Michael Chana1f60192007-12-20 19:57:19 -08002905 sw_ring_prod);
Michael Chan85833c62007-12-12 11:17:01 -08002906 goto next_rx;
Michael Chanb6016b72005-05-26 13:03:09 -07002907 }
Michael Chan1db82f22007-12-12 11:19:35 -08002908 hdr_len = 0;
2909 if (status & L2_FHDR_STATUS_SPLIT) {
2910 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2911 pg_ring_used = 1;
2912 } else if (len > bp->rx_jumbo_thresh) {
2913 hdr_len = bp->rx_jumbo_thresh;
2914 pg_ring_used = 1;
2915 }
2916
2917 len -= 4;
Michael Chanb6016b72005-05-26 13:03:09 -07002918
Michael Chan5d5d0012007-12-12 11:17:43 -08002919 if (len <= bp->rx_copy_thresh) {
Michael Chanb6016b72005-05-26 13:03:09 -07002920 struct sk_buff *new_skb;
2921
Michael Chanf22828e2008-08-14 15:30:14 -07002922 new_skb = netdev_alloc_skb(bp->dev, len + 6);
Michael Chan85833c62007-12-12 11:17:01 -08002923 if (new_skb == NULL) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07002924 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
Michael Chan85833c62007-12-12 11:17:01 -08002925 sw_ring_prod);
2926 goto next_rx;
2927 }
Michael Chanb6016b72005-05-26 13:03:09 -07002928
2929 /* aligned copy */
Benjamin Lid89cb6a2008-05-16 22:18:57 -07002930 skb_copy_from_linear_data_offset(skb,
Michael Chanf22828e2008-08-14 15:30:14 -07002931 BNX2_RX_OFFSET - 6,
2932 new_skb->data, len + 6);
2933 skb_reserve(new_skb, 6);
Michael Chanb6016b72005-05-26 13:03:09 -07002934 skb_put(new_skb, len);
Michael Chanb6016b72005-05-26 13:03:09 -07002935
Michael Chanbb4f98a2008-06-19 16:38:19 -07002936 bnx2_reuse_rx_skb(bp, rxr, skb,
Michael Chanb6016b72005-05-26 13:03:09 -07002937 sw_ring_cons, sw_ring_prod);
2938
2939 skb = new_skb;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002940 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
Michael Chana1f60192007-12-20 19:57:19 -08002941 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
Michael Chanb6016b72005-05-26 13:03:09 -07002942 goto next_rx;
Michael Chanb6016b72005-05-26 13:03:09 -07002943
Michael Chanf22828e2008-08-14 15:30:14 -07002944 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2945 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2946 vtag = rx_hdr->l2_fhdr_vlan_tag;
2947#ifdef BCM_VLAN
2948 if (bp->vlgrp)
2949 hw_vlan = 1;
2950 else
2951#endif
2952 {
2953 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2954 __skb_push(skb, 4);
2955
2956 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2957 ve->h_vlan_proto = htons(ETH_P_8021Q);
2958 ve->h_vlan_TCI = htons(vtag);
2959 len += 4;
2960 }
2961 }
2962
Michael Chanb6016b72005-05-26 13:03:09 -07002963 skb->protocol = eth_type_trans(skb, bp->dev);
2964
2965 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
Alexey Dobriyand1e100b2006-06-11 20:57:17 -07002966 (ntohs(skb->protocol) != 0x8100)) {
Michael Chanb6016b72005-05-26 13:03:09 -07002967
Michael Chan745720e2006-06-29 12:37:41 -07002968 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07002969 goto next_rx;
2970
2971 }
2972
Michael Chanb6016b72005-05-26 13:03:09 -07002973 skb->ip_summed = CHECKSUM_NONE;
2974 if (bp->rx_csum &&
2975 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2976 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2977
Michael Chanade2bfe2006-01-23 16:09:51 -08002978 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2979 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
Michael Chanb6016b72005-05-26 13:03:09 -07002980 skb->ip_summed = CHECKSUM_UNNECESSARY;
2981 }
2982
2983#ifdef BCM_VLAN
Michael Chanf22828e2008-08-14 15:30:14 -07002984 if (hw_vlan)
2985 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
Michael Chanb6016b72005-05-26 13:03:09 -07002986 else
2987#endif
2988 netif_receive_skb(skb);
2989
2990 bp->dev->last_rx = jiffies;
2991 rx_pkt++;
2992
2993next_rx:
Michael Chanb6016b72005-05-26 13:03:09 -07002994 sw_cons = NEXT_RX_BD(sw_cons);
2995 sw_prod = NEXT_RX_BD(sw_prod);
2996
2997 if ((rx_pkt == budget))
2998 break;
Michael Chanf4e418f2005-11-04 08:53:48 -08002999
3000 /* Refresh hw_cons to see if there is new work */
3001 if (sw_cons == hw_cons) {
Michael Chan35efa7c2007-12-20 19:56:37 -08003002 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chanf4e418f2005-11-04 08:53:48 -08003003 rmb();
3004 }
Michael Chanb6016b72005-05-26 13:03:09 -07003005 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07003006 rxr->rx_cons = sw_cons;
3007 rxr->rx_prod = sw_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07003008
Michael Chan1db82f22007-12-12 11:19:35 -08003009 if (pg_ring_used)
Michael Chanbb4f98a2008-06-19 16:38:19 -07003010 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
Michael Chan1db82f22007-12-12 11:19:35 -08003011
Michael Chanbb4f98a2008-06-19 16:38:19 -07003012 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
Michael Chanb6016b72005-05-26 13:03:09 -07003013
Michael Chanbb4f98a2008-06-19 16:38:19 -07003014 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07003015
3016 mmiowb();
3017
3018 return rx_pkt;
3019
3020}
3021
3022/* MSI ISR - The only difference between this and the INTx ISR
3023 * is that the MSI interrupt is always serviced.
3024 */
3025static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01003026bnx2_msi(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07003027{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003028 struct bnx2_napi *bnapi = dev_instance;
3029 struct bnx2 *bp = bnapi->bp;
3030 struct net_device *dev = bp->dev;
Michael Chanb6016b72005-05-26 13:03:09 -07003031
Michael Chan43e80b82008-06-19 16:41:08 -07003032 prefetch(bnapi->status_blk.msi);
Michael Chanb6016b72005-05-26 13:03:09 -07003033 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3034 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3035 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3036
3037 /* Return here if interrupt is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07003038 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3039 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003040
Michael Chan35efa7c2007-12-20 19:56:37 -08003041 netif_rx_schedule(dev, &bnapi->napi);
Michael Chanb6016b72005-05-26 13:03:09 -07003042
Michael Chan73eef4c2005-08-25 15:39:15 -07003043 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003044}
3045
3046static irqreturn_t
Michael Chan8e6a72c2007-05-03 13:24:48 -07003047bnx2_msi_1shot(int irq, void *dev_instance)
3048{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003049 struct bnx2_napi *bnapi = dev_instance;
3050 struct bnx2 *bp = bnapi->bp;
3051 struct net_device *dev = bp->dev;
Michael Chan8e6a72c2007-05-03 13:24:48 -07003052
Michael Chan43e80b82008-06-19 16:41:08 -07003053 prefetch(bnapi->status_blk.msi);
Michael Chan8e6a72c2007-05-03 13:24:48 -07003054
3055 /* Return here if interrupt is disabled. */
3056 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3057 return IRQ_HANDLED;
3058
Michael Chan35efa7c2007-12-20 19:56:37 -08003059 netif_rx_schedule(dev, &bnapi->napi);
Michael Chan8e6a72c2007-05-03 13:24:48 -07003060
3061 return IRQ_HANDLED;
3062}
3063
3064static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01003065bnx2_interrupt(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07003066{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003067 struct bnx2_napi *bnapi = dev_instance;
3068 struct bnx2 *bp = bnapi->bp;
3069 struct net_device *dev = bp->dev;
Michael Chan43e80b82008-06-19 16:41:08 -07003070 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanb6016b72005-05-26 13:03:09 -07003071
3072 /* When using INTx, it is possible for the interrupt to arrive
3073 * at the CPU before the status block posted prior to the
3074 * interrupt. Reading a register will flush the status block.
3075 * When using MSI, the MSI message will always complete after
3076 * the status block write.
3077 */
Michael Chan35efa7c2007-12-20 19:56:37 -08003078 if ((sblk->status_idx == bnapi->last_status_idx) &&
Michael Chanb6016b72005-05-26 13:03:09 -07003079 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3080 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
Michael Chan73eef4c2005-08-25 15:39:15 -07003081 return IRQ_NONE;
Michael Chanb6016b72005-05-26 13:03:09 -07003082
3083 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3084 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3085 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3086
Michael Chanb8a7ce72007-07-07 22:51:03 -07003087 /* Read back to deassert IRQ immediately to avoid too many
3088 * spurious interrupts.
3089 */
3090 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3091
Michael Chanb6016b72005-05-26 13:03:09 -07003092 /* Return here if interrupt is shared and is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07003093 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3094 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003095
Michael Chan35efa7c2007-12-20 19:56:37 -08003096 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
3097 bnapi->last_status_idx = sblk->status_idx;
3098 __netif_rx_schedule(dev, &bnapi->napi);
Michael Chanb8a7ce72007-07-07 22:51:03 -07003099 }
Michael Chanb6016b72005-05-26 13:03:09 -07003100
Michael Chan73eef4c2005-08-25 15:39:15 -07003101 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003102}
3103
Michael Chan43e80b82008-06-19 16:41:08 -07003104static inline int
3105bnx2_has_fast_work(struct bnx2_napi *bnapi)
3106{
3107 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3108 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3109
3110 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3111 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3112 return 1;
3113 return 0;
3114}
3115
Michael Chan0d8a6572007-07-07 22:49:43 -07003116#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3117 STATUS_ATTN_BITS_TIMER_ABORT)
Michael Chanda3e4fb2007-05-03 13:24:23 -07003118
Michael Chanf4e418f2005-11-04 08:53:48 -08003119static inline int
Michael Chan35efa7c2007-12-20 19:56:37 -08003120bnx2_has_work(struct bnx2_napi *bnapi)
Michael Chanf4e418f2005-11-04 08:53:48 -08003121{
Michael Chan43e80b82008-06-19 16:41:08 -07003122 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanf4e418f2005-11-04 08:53:48 -08003123
Michael Chan43e80b82008-06-19 16:41:08 -07003124 if (bnx2_has_fast_work(bnapi))
Michael Chanf4e418f2005-11-04 08:53:48 -08003125 return 1;
3126
Michael Chanda3e4fb2007-05-03 13:24:23 -07003127 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3128 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
Michael Chanf4e418f2005-11-04 08:53:48 -08003129 return 1;
3130
3131 return 0;
3132}
3133
Michael Chan43e80b82008-06-19 16:41:08 -07003134static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chanb6016b72005-05-26 13:03:09 -07003135{
Michael Chan43e80b82008-06-19 16:41:08 -07003136 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanda3e4fb2007-05-03 13:24:23 -07003137 u32 status_attn_bits = sblk->status_attn_bits;
3138 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
Michael Chanb6016b72005-05-26 13:03:09 -07003139
Michael Chanda3e4fb2007-05-03 13:24:23 -07003140 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3141 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003142
Michael Chan35efa7c2007-12-20 19:56:37 -08003143 bnx2_phy_int(bp, bnapi);
Michael Chanbf5295b2006-03-23 01:11:56 -08003144
3145 /* This is needed to take care of transient status
3146 * during link changes.
3147 */
3148 REG_WR(bp, BNX2_HC_COMMAND,
3149 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3150 REG_RD(bp, BNX2_HC_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07003151 }
Michael Chan43e80b82008-06-19 16:41:08 -07003152}
3153
3154static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3155 int work_done, int budget)
3156{
3157 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3158 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07003159
Michael Chan35e90102008-06-19 16:37:42 -07003160 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
Michael Chan57851d82007-12-20 20:01:44 -08003161 bnx2_tx_int(bp, bnapi, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003162
Michael Chanbb4f98a2008-06-19 16:38:19 -07003163 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
Michael Chan35efa7c2007-12-20 19:56:37 -08003164 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003165
David S. Miller6f535762007-10-11 18:08:29 -07003166 return work_done;
3167}
Michael Chanf4e418f2005-11-04 08:53:48 -08003168
Michael Chanf0ea2e62008-06-19 16:41:57 -07003169static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3170{
3171 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3172 struct bnx2 *bp = bnapi->bp;
3173 int work_done = 0;
3174 struct status_block_msix *sblk = bnapi->status_blk.msix;
3175
3176 while (1) {
3177 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3178 if (unlikely(work_done >= budget))
3179 break;
3180
3181 bnapi->last_status_idx = sblk->status_idx;
3182 /* status idx must be read before checking for more work. */
3183 rmb();
3184 if (likely(!bnx2_has_fast_work(bnapi))) {
3185
3186 netif_rx_complete(bp->dev, napi);
3187 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3188 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3189 bnapi->last_status_idx);
3190 break;
3191 }
3192 }
3193 return work_done;
3194}
3195
David S. Miller6f535762007-10-11 18:08:29 -07003196static int bnx2_poll(struct napi_struct *napi, int budget)
3197{
Michael Chan35efa7c2007-12-20 19:56:37 -08003198 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3199 struct bnx2 *bp = bnapi->bp;
David S. Miller6f535762007-10-11 18:08:29 -07003200 int work_done = 0;
Michael Chan43e80b82008-06-19 16:41:08 -07003201 struct status_block *sblk = bnapi->status_blk.msi;
David S. Miller6f535762007-10-11 18:08:29 -07003202
3203 while (1) {
Michael Chan43e80b82008-06-19 16:41:08 -07003204 bnx2_poll_link(bp, bnapi);
3205
Michael Chan35efa7c2007-12-20 19:56:37 -08003206 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
David S. Miller6f535762007-10-11 18:08:29 -07003207
3208 if (unlikely(work_done >= budget))
3209 break;
3210
Michael Chan35efa7c2007-12-20 19:56:37 -08003211 /* bnapi->last_status_idx is used below to tell the hw how
Michael Chan6dee6422007-10-12 01:40:38 -07003212 * much work has been processed, so we must read it before
3213 * checking for more work.
3214 */
Michael Chan35efa7c2007-12-20 19:56:37 -08003215 bnapi->last_status_idx = sblk->status_idx;
Michael Chan6dee6422007-10-12 01:40:38 -07003216 rmb();
Michael Chan35efa7c2007-12-20 19:56:37 -08003217 if (likely(!bnx2_has_work(bnapi))) {
David S. Miller6f535762007-10-11 18:08:29 -07003218 netif_rx_complete(bp->dev, napi);
David S. Millerf86e82f2008-01-21 17:15:40 -08003219 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
David S. Miller6f535762007-10-11 18:08:29 -07003220 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3221 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
Michael Chan35efa7c2007-12-20 19:56:37 -08003222 bnapi->last_status_idx);
Michael Chan6dee6422007-10-12 01:40:38 -07003223 break;
David S. Miller6f535762007-10-11 18:08:29 -07003224 }
3225 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3226 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3227 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
Michael Chan35efa7c2007-12-20 19:56:37 -08003228 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003229
Michael Chan1269a8a2006-01-23 16:11:03 -08003230 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3231 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
Michael Chan35efa7c2007-12-20 19:56:37 -08003232 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003233 break;
Michael Chan1269a8a2006-01-23 16:11:03 -08003234 }
Michael Chanb6016b72005-05-26 13:03:09 -07003235 }
3236
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003237 return work_done;
Michael Chanb6016b72005-05-26 13:03:09 -07003238}
3239
Herbert Xu932ff272006-06-09 12:20:56 -07003240/* Called with rtnl_lock from vlan functions and also netif_tx_lock
Michael Chanb6016b72005-05-26 13:03:09 -07003241 * from set_multicast.
3242 */
3243static void
3244bnx2_set_rx_mode(struct net_device *dev)
3245{
Michael Chan972ec0d2006-01-23 16:12:43 -08003246 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07003247 u32 rx_mode, sort_mode;
Benjamin Li5fcaed02008-07-14 22:39:52 -07003248 struct dev_addr_list *uc_ptr;
Michael Chanb6016b72005-05-26 13:03:09 -07003249 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07003250
Michael Chan9f52b562008-10-09 12:21:46 -07003251 if (!netif_running(dev))
3252 return;
3253
Michael Chanc770a652005-08-25 15:38:39 -07003254 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003255
3256 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3257 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3258 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3259#ifdef BCM_VLAN
Michael Chan7c6337a2008-08-14 15:29:09 -07003260 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
Michael Chanb6016b72005-05-26 13:03:09 -07003261 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
Michael Chanb6016b72005-05-26 13:03:09 -07003262#else
Michael Chan7c6337a2008-08-14 15:29:09 -07003263 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
Michael Chane29054f2006-01-23 16:06:06 -08003264 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
Michael Chanb6016b72005-05-26 13:03:09 -07003265#endif
3266 if (dev->flags & IFF_PROMISC) {
3267 /* Promiscuous mode. */
3268 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
Michael Chan75108732006-11-19 14:06:40 -08003269 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3270 BNX2_RPM_SORT_USER0_PROM_VLAN;
Michael Chanb6016b72005-05-26 13:03:09 -07003271 }
3272 else if (dev->flags & IFF_ALLMULTI) {
3273 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3274 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3275 0xffffffff);
3276 }
3277 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3278 }
3279 else {
3280 /* Accept one or more multicast(s). */
3281 struct dev_mc_list *mclist;
3282 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3283 u32 regidx;
3284 u32 bit;
3285 u32 crc;
3286
3287 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3288
3289 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3290 i++, mclist = mclist->next) {
3291
3292 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3293 bit = crc & 0xff;
3294 regidx = (bit & 0xe0) >> 5;
3295 bit &= 0x1f;
3296 mc_filter[regidx] |= (1 << bit);
3297 }
3298
3299 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3300 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3301 mc_filter[i]);
3302 }
3303
3304 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3305 }
3306
Benjamin Li5fcaed02008-07-14 22:39:52 -07003307 uc_ptr = NULL;
3308 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3309 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3310 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3311 BNX2_RPM_SORT_USER0_PROM_VLAN;
3312 } else if (!(dev->flags & IFF_PROMISC)) {
3313 uc_ptr = dev->uc_list;
3314
3315 /* Add all entries into to the match filter list */
3316 for (i = 0; i < dev->uc_count; i++) {
3317 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3318 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3319 sort_mode |= (1 <<
3320 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3321 uc_ptr = uc_ptr->next;
3322 }
3323
3324 }
3325
Michael Chanb6016b72005-05-26 13:03:09 -07003326 if (rx_mode != bp->rx_mode) {
3327 bp->rx_mode = rx_mode;
3328 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3329 }
3330
3331 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3332 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3333 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3334
Michael Chanc770a652005-08-25 15:38:39 -07003335 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003336}
3337
3338static void
Al Virob491edd2007-12-22 19:44:51 +00003339load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
Michael Chanb6016b72005-05-26 13:03:09 -07003340 u32 rv2p_proc)
3341{
3342 int i;
3343 u32 val;
3344
Michael Chand25be1d2008-05-02 16:57:59 -07003345 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3346 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3347 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3348 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3349 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3350 }
Michael Chanb6016b72005-05-26 13:03:09 -07003351
3352 for (i = 0; i < rv2p_code_len; i += 8) {
Al Virob491edd2007-12-22 19:44:51 +00003353 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003354 rv2p_code++;
Al Virob491edd2007-12-22 19:44:51 +00003355 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003356 rv2p_code++;
3357
3358 if (rv2p_proc == RV2P_PROC1) {
3359 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3360 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3361 }
3362 else {
3363 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3364 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3365 }
3366 }
3367
3368 /* Reset the processor, un-stall is done later. */
3369 if (rv2p_proc == RV2P_PROC1) {
3370 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3371 }
3372 else {
3373 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3374 }
3375}
3376
Michael Chanaf3ee512006-11-19 14:09:25 -08003377static int
Benjamin Li10343cc2008-05-16 22:20:27 -07003378load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
Michael Chanb6016b72005-05-26 13:03:09 -07003379{
3380 u32 offset;
3381 u32 val;
Michael Chanaf3ee512006-11-19 14:09:25 -08003382 int rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003383
3384 /* Halt the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003385 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003386 val |= cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003387 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3388 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
Michael Chanb6016b72005-05-26 13:03:09 -07003389
3390 /* Load the Text area. */
3391 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
Michael Chanaf3ee512006-11-19 14:09:25 -08003392 if (fw->gz_text) {
Michael Chanb6016b72005-05-26 13:03:09 -07003393 int j;
3394
Michael Chanea1f8d52007-10-02 16:27:35 -07003395 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3396 fw->gz_text_len);
3397 if (rc < 0)
Denys Vlasenkob3448b02007-09-30 17:55:51 -07003398 return rc;
Michael Chanea1f8d52007-10-02 16:27:35 -07003399
Michael Chanb6016b72005-05-26 13:03:09 -07003400 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003401 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003402 }
3403 }
3404
3405 /* Load the Data area. */
3406 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3407 if (fw->data) {
3408 int j;
3409
3410 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003411 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
Michael Chanb6016b72005-05-26 13:03:09 -07003412 }
3413 }
3414
3415 /* Load the SBSS area. */
3416 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
Michael Chanea1f8d52007-10-02 16:27:35 -07003417 if (fw->sbss_len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003418 int j;
3419
3420 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003421 bnx2_reg_wr_ind(bp, offset, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003422 }
3423 }
3424
3425 /* Load the BSS area. */
3426 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
Michael Chanea1f8d52007-10-02 16:27:35 -07003427 if (fw->bss_len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003428 int j;
3429
3430 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003431 bnx2_reg_wr_ind(bp, offset, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003432 }
3433 }
3434
3435 /* Load the Read-Only area. */
3436 offset = cpu_reg->spad_base +
3437 (fw->rodata_addr - cpu_reg->mips_view_base);
3438 if (fw->rodata) {
3439 int j;
3440
3441 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003442 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
Michael Chanb6016b72005-05-26 13:03:09 -07003443 }
3444 }
3445
3446 /* Clear the pre-fetch instruction. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003447 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3448 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
Michael Chanb6016b72005-05-26 13:03:09 -07003449
3450 /* Start the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003451 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003452 val &= ~cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003453 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3454 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
Michael Chanaf3ee512006-11-19 14:09:25 -08003455
3456 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003457}
3458
Michael Chanfba9fe92006-06-12 22:21:25 -07003459static int
Michael Chanb6016b72005-05-26 13:03:09 -07003460bnx2_init_cpus(struct bnx2 *bp)
3461{
Michael Chanaf3ee512006-11-19 14:09:25 -08003462 struct fw_info *fw;
Michael Chan110d0ef2007-12-12 11:18:34 -08003463 int rc, rv2p_len;
3464 void *text, *rv2p;
Michael Chanb6016b72005-05-26 13:03:09 -07003465
3466 /* Initialize the RV2P processor. */
Denys Vlasenkob3448b02007-09-30 17:55:51 -07003467 text = vmalloc(FW_BUF_SIZE);
3468 if (!text)
3469 return -ENOMEM;
Michael Chan110d0ef2007-12-12 11:18:34 -08003470 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3471 rv2p = bnx2_xi_rv2p_proc1;
3472 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3473 } else {
3474 rv2p = bnx2_rv2p_proc1;
3475 rv2p_len = sizeof(bnx2_rv2p_proc1);
3476 }
3477 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
Michael Chanea1f8d52007-10-02 16:27:35 -07003478 if (rc < 0)
Michael Chanfba9fe92006-06-12 22:21:25 -07003479 goto init_cpu_err;
Michael Chanea1f8d52007-10-02 16:27:35 -07003480
Denys Vlasenkob3448b02007-09-30 17:55:51 -07003481 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
Michael Chanfba9fe92006-06-12 22:21:25 -07003482
Michael Chan110d0ef2007-12-12 11:18:34 -08003483 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3484 rv2p = bnx2_xi_rv2p_proc2;
3485 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3486 } else {
3487 rv2p = bnx2_rv2p_proc2;
3488 rv2p_len = sizeof(bnx2_rv2p_proc2);
3489 }
3490 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
Michael Chanea1f8d52007-10-02 16:27:35 -07003491 if (rc < 0)
Michael Chanfba9fe92006-06-12 22:21:25 -07003492 goto init_cpu_err;
Michael Chanea1f8d52007-10-02 16:27:35 -07003493
Denys Vlasenkob3448b02007-09-30 17:55:51 -07003494 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
Michael Chanb6016b72005-05-26 13:03:09 -07003495
3496 /* Initialize the RX Processor. */
Michael Chand43584c2006-11-19 14:14:35 -08003497 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3498 fw = &bnx2_rxp_fw_09;
3499 else
3500 fw = &bnx2_rxp_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003501
Michael Chanea1f8d52007-10-02 16:27:35 -07003502 fw->text = text;
Benjamin Li10343cc2008-05-16 22:20:27 -07003503 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
Michael Chanfba9fe92006-06-12 22:21:25 -07003504 if (rc)
3505 goto init_cpu_err;
3506
Michael Chanb6016b72005-05-26 13:03:09 -07003507 /* Initialize the TX Processor. */
Michael Chand43584c2006-11-19 14:14:35 -08003508 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3509 fw = &bnx2_txp_fw_09;
3510 else
3511 fw = &bnx2_txp_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003512
Michael Chanea1f8d52007-10-02 16:27:35 -07003513 fw->text = text;
Benjamin Li10343cc2008-05-16 22:20:27 -07003514 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
Michael Chanfba9fe92006-06-12 22:21:25 -07003515 if (rc)
3516 goto init_cpu_err;
3517
Michael Chanb6016b72005-05-26 13:03:09 -07003518 /* Initialize the TX Patch-up Processor. */
Michael Chand43584c2006-11-19 14:14:35 -08003519 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3520 fw = &bnx2_tpat_fw_09;
3521 else
3522 fw = &bnx2_tpat_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003523
Michael Chanea1f8d52007-10-02 16:27:35 -07003524 fw->text = text;
Benjamin Li10343cc2008-05-16 22:20:27 -07003525 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
Michael Chanfba9fe92006-06-12 22:21:25 -07003526 if (rc)
3527 goto init_cpu_err;
3528
Michael Chanb6016b72005-05-26 13:03:09 -07003529 /* Initialize the Completion Processor. */
Michael Chand43584c2006-11-19 14:14:35 -08003530 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3531 fw = &bnx2_com_fw_09;
3532 else
3533 fw = &bnx2_com_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003534
Michael Chanea1f8d52007-10-02 16:27:35 -07003535 fw->text = text;
Benjamin Li10343cc2008-05-16 22:20:27 -07003536 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
Michael Chanfba9fe92006-06-12 22:21:25 -07003537 if (rc)
3538 goto init_cpu_err;
3539
Michael Chand43584c2006-11-19 14:14:35 -08003540 /* Initialize the Command Processor. */
Michael Chan110d0ef2007-12-12 11:18:34 -08003541 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chand43584c2006-11-19 14:14:35 -08003542 fw = &bnx2_cp_fw_09;
Michael Chan110d0ef2007-12-12 11:18:34 -08003543 else
3544 fw = &bnx2_cp_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003545
Michael Chan110d0ef2007-12-12 11:18:34 -08003546 fw->text = text;
Benjamin Li10343cc2008-05-16 22:20:27 -07003547 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
Michael Chan110d0ef2007-12-12 11:18:34 -08003548
Michael Chanfba9fe92006-06-12 22:21:25 -07003549init_cpu_err:
Michael Chanea1f8d52007-10-02 16:27:35 -07003550 vfree(text);
Michael Chanfba9fe92006-06-12 22:21:25 -07003551 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003552}
3553
3554static int
Pavel Machek829ca9a2005-09-03 15:56:56 -07003555bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
Michael Chanb6016b72005-05-26 13:03:09 -07003556{
3557 u16 pmcsr;
3558
3559 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3560
3561 switch (state) {
Pavel Machek829ca9a2005-09-03 15:56:56 -07003562 case PCI_D0: {
Michael Chanb6016b72005-05-26 13:03:09 -07003563 u32 val;
3564
3565 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3566 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3567 PCI_PM_CTRL_PME_STATUS);
3568
3569 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3570 /* delay required during transition out of D3hot */
3571 msleep(20);
3572
3573 val = REG_RD(bp, BNX2_EMAC_MODE);
3574 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3575 val &= ~BNX2_EMAC_MODE_MPKT;
3576 REG_WR(bp, BNX2_EMAC_MODE, val);
3577
3578 val = REG_RD(bp, BNX2_RPM_CONFIG);
3579 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3580 REG_WR(bp, BNX2_RPM_CONFIG, val);
3581 break;
3582 }
Pavel Machek829ca9a2005-09-03 15:56:56 -07003583 case PCI_D3hot: {
Michael Chanb6016b72005-05-26 13:03:09 -07003584 int i;
3585 u32 val, wol_msg;
3586
3587 if (bp->wol) {
3588 u32 advertising;
3589 u8 autoneg;
3590
3591 autoneg = bp->autoneg;
3592 advertising = bp->advertising;
3593
Michael Chan239cd342007-10-17 19:26:15 -07003594 if (bp->phy_port == PORT_TP) {
3595 bp->autoneg = AUTONEG_SPEED;
3596 bp->advertising = ADVERTISED_10baseT_Half |
3597 ADVERTISED_10baseT_Full |
3598 ADVERTISED_100baseT_Half |
3599 ADVERTISED_100baseT_Full |
3600 ADVERTISED_Autoneg;
3601 }
Michael Chanb6016b72005-05-26 13:03:09 -07003602
Michael Chan239cd342007-10-17 19:26:15 -07003603 spin_lock_bh(&bp->phy_lock);
3604 bnx2_setup_phy(bp, bp->phy_port);
3605 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003606
3607 bp->autoneg = autoneg;
3608 bp->advertising = advertising;
3609
Benjamin Li5fcaed02008-07-14 22:39:52 -07003610 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003611
3612 val = REG_RD(bp, BNX2_EMAC_MODE);
3613
3614 /* Enable port mode. */
3615 val &= ~BNX2_EMAC_MODE_PORT;
Michael Chan239cd342007-10-17 19:26:15 -07003616 val |= BNX2_EMAC_MODE_MPKT_RCVD |
Michael Chanb6016b72005-05-26 13:03:09 -07003617 BNX2_EMAC_MODE_ACPI_RCVD |
Michael Chanb6016b72005-05-26 13:03:09 -07003618 BNX2_EMAC_MODE_MPKT;
Michael Chan239cd342007-10-17 19:26:15 -07003619 if (bp->phy_port == PORT_TP)
3620 val |= BNX2_EMAC_MODE_PORT_MII;
3621 else {
3622 val |= BNX2_EMAC_MODE_PORT_GMII;
3623 if (bp->line_speed == SPEED_2500)
3624 val |= BNX2_EMAC_MODE_25G_MODE;
3625 }
Michael Chanb6016b72005-05-26 13:03:09 -07003626
3627 REG_WR(bp, BNX2_EMAC_MODE, val);
3628
3629 /* receive all multicast */
3630 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3631 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3632 0xffffffff);
3633 }
3634 REG_WR(bp, BNX2_EMAC_RX_MODE,
3635 BNX2_EMAC_RX_MODE_SORT_MODE);
3636
3637 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3638 BNX2_RPM_SORT_USER0_MC_EN;
3639 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3640 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3641 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3642 BNX2_RPM_SORT_USER0_ENA);
3643
3644 /* Need to enable EMAC and RPM for WOL. */
3645 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3646 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3647 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3648 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3649
3650 val = REG_RD(bp, BNX2_RPM_CONFIG);
3651 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3652 REG_WR(bp, BNX2_RPM_CONFIG, val);
3653
3654 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3655 }
3656 else {
3657 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3658 }
3659
David S. Millerf86e82f2008-01-21 17:15:40 -08003660 if (!(bp->flags & BNX2_FLAG_NO_WOL))
Michael Chana2f13892008-07-14 22:38:23 -07003661 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3662 1, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003663
3664 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3665 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3666 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3667
3668 if (bp->wol)
3669 pmcsr |= 3;
3670 }
3671 else {
3672 pmcsr |= 3;
3673 }
3674 if (bp->wol) {
3675 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3676 }
3677 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3678 pmcsr);
3679
3680 /* No more memory access after this point until
3681 * device is brought back to D0.
3682 */
3683 udelay(50);
3684 break;
3685 }
3686 default:
3687 return -EINVAL;
3688 }
3689 return 0;
3690}
3691
3692static int
3693bnx2_acquire_nvram_lock(struct bnx2 *bp)
3694{
3695 u32 val;
3696 int j;
3697
3698 /* Request access to the flash interface. */
3699 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3700 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3701 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3702 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3703 break;
3704
3705 udelay(5);
3706 }
3707
3708 if (j >= NVRAM_TIMEOUT_COUNT)
3709 return -EBUSY;
3710
3711 return 0;
3712}
3713
3714static int
3715bnx2_release_nvram_lock(struct bnx2 *bp)
3716{
3717 int j;
3718 u32 val;
3719
3720 /* Relinquish nvram interface. */
3721 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3722
3723 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3724 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3725 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3726 break;
3727
3728 udelay(5);
3729 }
3730
3731 if (j >= NVRAM_TIMEOUT_COUNT)
3732 return -EBUSY;
3733
3734 return 0;
3735}
3736
3737
3738static int
3739bnx2_enable_nvram_write(struct bnx2 *bp)
3740{
3741 u32 val;
3742
3743 val = REG_RD(bp, BNX2_MISC_CFG);
3744 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3745
Michael Chane30372c2007-07-16 18:26:23 -07003746 if (bp->flash_info->flags & BNX2_NV_WREN) {
Michael Chanb6016b72005-05-26 13:03:09 -07003747 int j;
3748
3749 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3750 REG_WR(bp, BNX2_NVM_COMMAND,
3751 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3752
3753 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3754 udelay(5);
3755
3756 val = REG_RD(bp, BNX2_NVM_COMMAND);
3757 if (val & BNX2_NVM_COMMAND_DONE)
3758 break;
3759 }
3760
3761 if (j >= NVRAM_TIMEOUT_COUNT)
3762 return -EBUSY;
3763 }
3764 return 0;
3765}
3766
3767static void
3768bnx2_disable_nvram_write(struct bnx2 *bp)
3769{
3770 u32 val;
3771
3772 val = REG_RD(bp, BNX2_MISC_CFG);
3773 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3774}
3775
3776
3777static void
3778bnx2_enable_nvram_access(struct bnx2 *bp)
3779{
3780 u32 val;
3781
3782 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3783 /* Enable both bits, even on read. */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003784 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
Michael Chanb6016b72005-05-26 13:03:09 -07003785 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3786}
3787
3788static void
3789bnx2_disable_nvram_access(struct bnx2 *bp)
3790{
3791 u32 val;
3792
3793 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3794 /* Disable both bits, even after read. */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003795 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
Michael Chanb6016b72005-05-26 13:03:09 -07003796 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3797 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3798}
3799
3800static int
3801bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3802{
3803 u32 cmd;
3804 int j;
3805
Michael Chane30372c2007-07-16 18:26:23 -07003806 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
Michael Chanb6016b72005-05-26 13:03:09 -07003807 /* Buffered flash, no erase needed */
3808 return 0;
3809
3810 /* Build an erase command */
3811 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3812 BNX2_NVM_COMMAND_DOIT;
3813
3814 /* Need to clear DONE bit separately. */
3815 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3816
3817 /* Address of the NVRAM to read from. */
3818 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3819
3820 /* Issue an erase command. */
3821 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3822
3823 /* Wait for completion. */
3824 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3825 u32 val;
3826
3827 udelay(5);
3828
3829 val = REG_RD(bp, BNX2_NVM_COMMAND);
3830 if (val & BNX2_NVM_COMMAND_DONE)
3831 break;
3832 }
3833
3834 if (j >= NVRAM_TIMEOUT_COUNT)
3835 return -EBUSY;
3836
3837 return 0;
3838}
3839
3840static int
3841bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3842{
3843 u32 cmd;
3844 int j;
3845
3846 /* Build the command word. */
3847 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3848
Michael Chane30372c2007-07-16 18:26:23 -07003849 /* Calculate an offset of a buffered flash, not needed for 5709. */
3850 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07003851 offset = ((offset / bp->flash_info->page_size) <<
3852 bp->flash_info->page_bits) +
3853 (offset % bp->flash_info->page_size);
3854 }
3855
3856 /* Need to clear DONE bit separately. */
3857 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3858
3859 /* Address of the NVRAM to read from. */
3860 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3861
3862 /* Issue a read command. */
3863 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3864
3865 /* Wait for completion. */
3866 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3867 u32 val;
3868
3869 udelay(5);
3870
3871 val = REG_RD(bp, BNX2_NVM_COMMAND);
3872 if (val & BNX2_NVM_COMMAND_DONE) {
Al Virob491edd2007-12-22 19:44:51 +00003873 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3874 memcpy(ret_val, &v, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07003875 break;
3876 }
3877 }
3878 if (j >= NVRAM_TIMEOUT_COUNT)
3879 return -EBUSY;
3880
3881 return 0;
3882}
3883
3884
3885static int
3886bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3887{
Al Virob491edd2007-12-22 19:44:51 +00003888 u32 cmd;
3889 __be32 val32;
Michael Chanb6016b72005-05-26 13:03:09 -07003890 int j;
3891
3892 /* Build the command word. */
3893 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3894
Michael Chane30372c2007-07-16 18:26:23 -07003895 /* Calculate an offset of a buffered flash, not needed for 5709. */
3896 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07003897 offset = ((offset / bp->flash_info->page_size) <<
3898 bp->flash_info->page_bits) +
3899 (offset % bp->flash_info->page_size);
3900 }
3901
3902 /* Need to clear DONE bit separately. */
3903 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3904
3905 memcpy(&val32, val, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07003906
3907 /* Write the data. */
Al Virob491edd2007-12-22 19:44:51 +00003908 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
Michael Chanb6016b72005-05-26 13:03:09 -07003909
3910 /* Address of the NVRAM to write to. */
3911 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3912
3913 /* Issue the write command. */
3914 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3915
3916 /* Wait for completion. */
3917 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3918 udelay(5);
3919
3920 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3921 break;
3922 }
3923 if (j >= NVRAM_TIMEOUT_COUNT)
3924 return -EBUSY;
3925
3926 return 0;
3927}
3928
3929static int
3930bnx2_init_nvram(struct bnx2 *bp)
3931{
3932 u32 val;
Michael Chane30372c2007-07-16 18:26:23 -07003933 int j, entry_count, rc = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003934 struct flash_spec *flash;
3935
Michael Chane30372c2007-07-16 18:26:23 -07003936 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3937 bp->flash_info = &flash_5709;
3938 goto get_flash_size;
3939 }
3940
Michael Chanb6016b72005-05-26 13:03:09 -07003941 /* Determine the selected interface. */
3942 val = REG_RD(bp, BNX2_NVM_CFG1);
3943
Denis Chengff8ac602007-09-02 18:30:18 +08003944 entry_count = ARRAY_SIZE(flash_table);
Michael Chanb6016b72005-05-26 13:03:09 -07003945
Michael Chanb6016b72005-05-26 13:03:09 -07003946 if (val & 0x40000000) {
3947
3948 /* Flash interface has been reconfigured */
3949 for (j = 0, flash = &flash_table[0]; j < entry_count;
Michael Chan37137702005-11-04 08:49:17 -08003950 j++, flash++) {
3951 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3952 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003953 bp->flash_info = flash;
3954 break;
3955 }
3956 }
3957 }
3958 else {
Michael Chan37137702005-11-04 08:49:17 -08003959 u32 mask;
Michael Chanb6016b72005-05-26 13:03:09 -07003960 /* Not yet been reconfigured */
3961
Michael Chan37137702005-11-04 08:49:17 -08003962 if (val & (1 << 23))
3963 mask = FLASH_BACKUP_STRAP_MASK;
3964 else
3965 mask = FLASH_STRAP_MASK;
3966
Michael Chanb6016b72005-05-26 13:03:09 -07003967 for (j = 0, flash = &flash_table[0]; j < entry_count;
3968 j++, flash++) {
3969
Michael Chan37137702005-11-04 08:49:17 -08003970 if ((val & mask) == (flash->strapping & mask)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003971 bp->flash_info = flash;
3972
3973 /* Request access to the flash interface. */
3974 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3975 return rc;
3976
3977 /* Enable access to flash interface */
3978 bnx2_enable_nvram_access(bp);
3979
3980 /* Reconfigure the flash interface */
3981 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3982 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3983 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3984 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3985
3986 /* Disable access to flash interface */
3987 bnx2_disable_nvram_access(bp);
3988 bnx2_release_nvram_lock(bp);
3989
3990 break;
3991 }
3992 }
3993 } /* if (val & 0x40000000) */
3994
3995 if (j == entry_count) {
3996 bp->flash_info = NULL;
John W. Linville2f23c522005-11-10 12:57:33 -08003997 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
Michael Chan1122db72006-01-23 16:11:42 -08003998 return -ENODEV;
Michael Chanb6016b72005-05-26 13:03:09 -07003999 }
4000
Michael Chane30372c2007-07-16 18:26:23 -07004001get_flash_size:
Michael Chan2726d6e2008-01-29 21:35:05 -08004002 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
Michael Chan1122db72006-01-23 16:11:42 -08004003 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4004 if (val)
4005 bp->flash_size = val;
4006 else
4007 bp->flash_size = bp->flash_info->total_size;
4008
Michael Chanb6016b72005-05-26 13:03:09 -07004009 return rc;
4010}
4011
4012static int
4013bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4014 int buf_size)
4015{
4016 int rc = 0;
4017 u32 cmd_flags, offset32, len32, extra;
4018
4019 if (buf_size == 0)
4020 return 0;
4021
4022 /* Request access to the flash interface. */
4023 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4024 return rc;
4025
4026 /* Enable access to flash interface */
4027 bnx2_enable_nvram_access(bp);
4028
4029 len32 = buf_size;
4030 offset32 = offset;
4031 extra = 0;
4032
4033 cmd_flags = 0;
4034
4035 if (offset32 & 3) {
4036 u8 buf[4];
4037 u32 pre_len;
4038
4039 offset32 &= ~3;
4040 pre_len = 4 - (offset & 3);
4041
4042 if (pre_len >= len32) {
4043 pre_len = len32;
4044 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4045 BNX2_NVM_COMMAND_LAST;
4046 }
4047 else {
4048 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4049 }
4050
4051 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4052
4053 if (rc)
4054 return rc;
4055
4056 memcpy(ret_buf, buf + (offset & 3), pre_len);
4057
4058 offset32 += 4;
4059 ret_buf += pre_len;
4060 len32 -= pre_len;
4061 }
4062 if (len32 & 3) {
4063 extra = 4 - (len32 & 3);
4064 len32 = (len32 + 4) & ~3;
4065 }
4066
4067 if (len32 == 4) {
4068 u8 buf[4];
4069
4070 if (cmd_flags)
4071 cmd_flags = BNX2_NVM_COMMAND_LAST;
4072 else
4073 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4074 BNX2_NVM_COMMAND_LAST;
4075
4076 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4077
4078 memcpy(ret_buf, buf, 4 - extra);
4079 }
4080 else if (len32 > 0) {
4081 u8 buf[4];
4082
4083 /* Read the first word. */
4084 if (cmd_flags)
4085 cmd_flags = 0;
4086 else
4087 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4088
4089 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4090
4091 /* Advance to the next dword. */
4092 offset32 += 4;
4093 ret_buf += 4;
4094 len32 -= 4;
4095
4096 while (len32 > 4 && rc == 0) {
4097 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4098
4099 /* Advance to the next dword. */
4100 offset32 += 4;
4101 ret_buf += 4;
4102 len32 -= 4;
4103 }
4104
4105 if (rc)
4106 return rc;
4107
4108 cmd_flags = BNX2_NVM_COMMAND_LAST;
4109 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4110
4111 memcpy(ret_buf, buf, 4 - extra);
4112 }
4113
4114 /* Disable access to flash interface */
4115 bnx2_disable_nvram_access(bp);
4116
4117 bnx2_release_nvram_lock(bp);
4118
4119 return rc;
4120}
4121
4122static int
4123bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4124 int buf_size)
4125{
4126 u32 written, offset32, len32;
Michael Chane6be7632007-01-08 19:56:13 -08004127 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07004128 int rc = 0;
4129 int align_start, align_end;
4130
4131 buf = data_buf;
4132 offset32 = offset;
4133 len32 = buf_size;
4134 align_start = align_end = 0;
4135
4136 if ((align_start = (offset32 & 3))) {
4137 offset32 &= ~3;
Michael Chanc8738792007-03-30 14:53:06 -07004138 len32 += align_start;
4139 if (len32 < 4)
4140 len32 = 4;
Michael Chanb6016b72005-05-26 13:03:09 -07004141 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4142 return rc;
4143 }
4144
4145 if (len32 & 3) {
Michael Chanc8738792007-03-30 14:53:06 -07004146 align_end = 4 - (len32 & 3);
4147 len32 += align_end;
4148 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4149 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004150 }
4151
4152 if (align_start || align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004153 align_buf = kmalloc(len32, GFP_KERNEL);
4154 if (align_buf == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07004155 return -ENOMEM;
4156 if (align_start) {
Michael Chane6be7632007-01-08 19:56:13 -08004157 memcpy(align_buf, start, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004158 }
4159 if (align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004160 memcpy(align_buf + len32 - 4, end, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004161 }
Michael Chane6be7632007-01-08 19:56:13 -08004162 memcpy(align_buf + align_start, data_buf, buf_size);
4163 buf = align_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07004164 }
4165
Michael Chane30372c2007-07-16 18:26:23 -07004166 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanae181bc2006-05-22 16:39:20 -07004167 flash_buffer = kmalloc(264, GFP_KERNEL);
4168 if (flash_buffer == NULL) {
4169 rc = -ENOMEM;
4170 goto nvram_write_end;
4171 }
4172 }
4173
Michael Chanb6016b72005-05-26 13:03:09 -07004174 written = 0;
4175 while ((written < len32) && (rc == 0)) {
4176 u32 page_start, page_end, data_start, data_end;
4177 u32 addr, cmd_flags;
4178 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07004179
4180 /* Find the page_start addr */
4181 page_start = offset32 + written;
4182 page_start -= (page_start % bp->flash_info->page_size);
4183 /* Find the page_end addr */
4184 page_end = page_start + bp->flash_info->page_size;
4185 /* Find the data_start addr */
4186 data_start = (written == 0) ? offset32 : page_start;
4187 /* Find the data_end addr */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004188 data_end = (page_end > offset32 + len32) ?
Michael Chanb6016b72005-05-26 13:03:09 -07004189 (offset32 + len32) : page_end;
4190
4191 /* Request access to the flash interface. */
4192 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4193 goto nvram_write_end;
4194
4195 /* Enable access to flash interface */
4196 bnx2_enable_nvram_access(bp);
4197
4198 cmd_flags = BNX2_NVM_COMMAND_FIRST;
Michael Chane30372c2007-07-16 18:26:23 -07004199 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004200 int j;
4201
4202 /* Read the whole page into the buffer
4203 * (non-buffer flash only) */
4204 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4205 if (j == (bp->flash_info->page_size - 4)) {
4206 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4207 }
4208 rc = bnx2_nvram_read_dword(bp,
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004209 page_start + j,
4210 &flash_buffer[j],
Michael Chanb6016b72005-05-26 13:03:09 -07004211 cmd_flags);
4212
4213 if (rc)
4214 goto nvram_write_end;
4215
4216 cmd_flags = 0;
4217 }
4218 }
4219
4220 /* Enable writes to flash interface (unlock write-protect) */
4221 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4222 goto nvram_write_end;
4223
Michael Chanb6016b72005-05-26 13:03:09 -07004224 /* Loop to write back the buffer data from page_start to
4225 * data_start */
4226 i = 0;
Michael Chane30372c2007-07-16 18:26:23 -07004227 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanc8738792007-03-30 14:53:06 -07004228 /* Erase the page */
4229 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4230 goto nvram_write_end;
4231
4232 /* Re-enable the write again for the actual write */
4233 bnx2_enable_nvram_write(bp);
4234
Michael Chanb6016b72005-05-26 13:03:09 -07004235 for (addr = page_start; addr < data_start;
4236 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004237
Michael Chanb6016b72005-05-26 13:03:09 -07004238 rc = bnx2_nvram_write_dword(bp, addr,
4239 &flash_buffer[i], cmd_flags);
4240
4241 if (rc != 0)
4242 goto nvram_write_end;
4243
4244 cmd_flags = 0;
4245 }
4246 }
4247
4248 /* Loop to write the new data from data_start to data_end */
Michael Chanbae25762006-05-22 16:38:38 -07004249 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
Michael Chanb6016b72005-05-26 13:03:09 -07004250 if ((addr == page_end - 4) ||
Michael Chane30372c2007-07-16 18:26:23 -07004251 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
Michael Chanb6016b72005-05-26 13:03:09 -07004252 (addr == data_end - 4))) {
4253
4254 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4255 }
4256 rc = bnx2_nvram_write_dword(bp, addr, buf,
4257 cmd_flags);
4258
4259 if (rc != 0)
4260 goto nvram_write_end;
4261
4262 cmd_flags = 0;
4263 buf += 4;
4264 }
4265
4266 /* Loop to write back the buffer data from data_end
4267 * to page_end */
Michael Chane30372c2007-07-16 18:26:23 -07004268 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004269 for (addr = data_end; addr < page_end;
4270 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004271
Michael Chanb6016b72005-05-26 13:03:09 -07004272 if (addr == page_end-4) {
4273 cmd_flags = BNX2_NVM_COMMAND_LAST;
4274 }
4275 rc = bnx2_nvram_write_dword(bp, addr,
4276 &flash_buffer[i], cmd_flags);
4277
4278 if (rc != 0)
4279 goto nvram_write_end;
4280
4281 cmd_flags = 0;
4282 }
4283 }
4284
4285 /* Disable writes to flash interface (lock write-protect) */
4286 bnx2_disable_nvram_write(bp);
4287
4288 /* Disable access to flash interface */
4289 bnx2_disable_nvram_access(bp);
4290 bnx2_release_nvram_lock(bp);
4291
4292 /* Increment written */
4293 written += data_end - data_start;
4294 }
4295
4296nvram_write_end:
Michael Chane6be7632007-01-08 19:56:13 -08004297 kfree(flash_buffer);
4298 kfree(align_buf);
Michael Chanb6016b72005-05-26 13:03:09 -07004299 return rc;
4300}
4301
Michael Chan0d8a6572007-07-07 22:49:43 -07004302static void
Michael Chan7c62e832008-07-14 22:39:03 -07004303bnx2_init_fw_cap(struct bnx2 *bp)
Michael Chan0d8a6572007-07-07 22:49:43 -07004304{
Michael Chan7c62e832008-07-14 22:39:03 -07004305 u32 val, sig = 0;
Michael Chan0d8a6572007-07-07 22:49:43 -07004306
Michael Chan583c28e2008-01-21 19:51:35 -08004307 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
Michael Chan7c62e832008-07-14 22:39:03 -07004308 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4309
4310 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4311 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
Michael Chan0d8a6572007-07-07 22:49:43 -07004312
Michael Chan2726d6e2008-01-29 21:35:05 -08004313 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07004314 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4315 return;
4316
Michael Chan7c62e832008-07-14 22:39:03 -07004317 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4318 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4319 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4320 }
4321
4322 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4323 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4324 u32 link;
4325
Michael Chan583c28e2008-01-21 19:51:35 -08004326 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
Michael Chan0d8a6572007-07-07 22:49:43 -07004327
Michael Chan7c62e832008-07-14 22:39:03 -07004328 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4329 if (link & BNX2_LINK_STATUS_SERDES_LINK)
Michael Chan0d8a6572007-07-07 22:49:43 -07004330 bp->phy_port = PORT_FIBRE;
4331 else
4332 bp->phy_port = PORT_TP;
Michael Chan489310a2007-10-10 16:16:31 -07004333
Michael Chan7c62e832008-07-14 22:39:03 -07004334 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4335 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
Michael Chan0d8a6572007-07-07 22:49:43 -07004336 }
Michael Chan7c62e832008-07-14 22:39:03 -07004337
4338 if (netif_running(bp->dev) && sig)
4339 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
Michael Chan0d8a6572007-07-07 22:49:43 -07004340}
4341
Michael Chanb4b36042007-12-20 19:59:30 -08004342static void
4343bnx2_setup_msix_tbl(struct bnx2 *bp)
4344{
4345 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4346
4347 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4348 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4349}
4350
Michael Chanb6016b72005-05-26 13:03:09 -07004351static int
4352bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4353{
4354 u32 val;
4355 int i, rc = 0;
Michael Chan489310a2007-10-10 16:16:31 -07004356 u8 old_port;
Michael Chanb6016b72005-05-26 13:03:09 -07004357
4358 /* Wait for the current PCI transaction to complete before
4359 * issuing a reset. */
4360 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4361 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4362 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4363 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4364 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4365 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4366 udelay(5);
4367
Michael Chanb090ae22006-01-23 16:07:10 -08004368 /* Wait for the firmware to tell us it is ok to issue a reset. */
Michael Chana2f13892008-07-14 22:38:23 -07004369 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
Michael Chanb090ae22006-01-23 16:07:10 -08004370
Michael Chanb6016b72005-05-26 13:03:09 -07004371 /* Deposit a driver reset signature so the firmware knows that
4372 * this is a soft reset. */
Michael Chan2726d6e2008-01-29 21:35:05 -08004373 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4374 BNX2_DRV_RESET_SIGNATURE_MAGIC);
Michael Chanb6016b72005-05-26 13:03:09 -07004375
Michael Chanb6016b72005-05-26 13:03:09 -07004376 /* Do a dummy read to force the chip to complete all current transaction
4377 * before we issue a reset. */
4378 val = REG_RD(bp, BNX2_MISC_ID);
4379
Michael Chan234754d2006-11-19 14:11:41 -08004380 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4381 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4382 REG_RD(bp, BNX2_MISC_COMMAND);
4383 udelay(5);
Michael Chanb6016b72005-05-26 13:03:09 -07004384
Michael Chan234754d2006-11-19 14:11:41 -08004385 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4386 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
Michael Chanb6016b72005-05-26 13:03:09 -07004387
Michael Chan234754d2006-11-19 14:11:41 -08004388 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004389
Michael Chan234754d2006-11-19 14:11:41 -08004390 } else {
4391 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4392 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4393 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4394
4395 /* Chip reset. */
4396 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4397
Michael Chan594a9df2007-08-28 15:39:42 -07004398 /* Reading back any register after chip reset will hang the
4399 * bus on 5706 A0 and A1. The msleep below provides plenty
4400 * of margin for write posting.
4401 */
Michael Chan234754d2006-11-19 14:11:41 -08004402 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
Arjan van de Ven8e545882007-08-28 14:34:43 -07004403 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4404 msleep(20);
Michael Chanb6016b72005-05-26 13:03:09 -07004405
Michael Chan234754d2006-11-19 14:11:41 -08004406 /* Reset takes approximate 30 usec */
4407 for (i = 0; i < 10; i++) {
4408 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4409 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4410 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4411 break;
4412 udelay(10);
4413 }
4414
4415 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4416 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4417 printk(KERN_ERR PFX "Chip reset did not complete\n");
4418 return -EBUSY;
4419 }
Michael Chanb6016b72005-05-26 13:03:09 -07004420 }
4421
4422 /* Make sure byte swapping is properly configured. */
4423 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4424 if (val != 0x01020304) {
4425 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4426 return -ENODEV;
4427 }
4428
Michael Chanb6016b72005-05-26 13:03:09 -07004429 /* Wait for the firmware to finish its initialization. */
Michael Chana2f13892008-07-14 22:38:23 -07004430 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
Michael Chanb090ae22006-01-23 16:07:10 -08004431 if (rc)
4432 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004433
Michael Chan0d8a6572007-07-07 22:49:43 -07004434 spin_lock_bh(&bp->phy_lock);
Michael Chan489310a2007-10-10 16:16:31 -07004435 old_port = bp->phy_port;
Michael Chan7c62e832008-07-14 22:39:03 -07004436 bnx2_init_fw_cap(bp);
Michael Chan583c28e2008-01-21 19:51:35 -08004437 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4438 old_port != bp->phy_port)
Michael Chan0d8a6572007-07-07 22:49:43 -07004439 bnx2_set_default_remote_link(bp);
4440 spin_unlock_bh(&bp->phy_lock);
4441
Michael Chanb6016b72005-05-26 13:03:09 -07004442 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4443 /* Adjust the voltage regular to two steps lower. The default
4444 * of this register is 0x0000000e. */
4445 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4446
4447 /* Remove bad rbuf memory from the free pool. */
4448 rc = bnx2_alloc_bad_rbuf(bp);
4449 }
4450
David S. Millerf86e82f2008-01-21 17:15:40 -08004451 if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanb4b36042007-12-20 19:59:30 -08004452 bnx2_setup_msix_tbl(bp);
4453
Michael Chanb6016b72005-05-26 13:03:09 -07004454 return rc;
4455}
4456
4457static int
4458bnx2_init_chip(struct bnx2 *bp)
4459{
4460 u32 val;
Michael Chanb4b36042007-12-20 19:59:30 -08004461 int rc, i;
Michael Chanb6016b72005-05-26 13:03:09 -07004462
4463 /* Make sure the interrupt is not active. */
4464 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4465
4466 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4467 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4468#ifdef __BIG_ENDIAN
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004469 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004470#endif
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004471 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004472 DMA_READ_CHANS << 12 |
4473 DMA_WRITE_CHANS << 16;
4474
4475 val |= (0x2 << 20) | (1 << 11);
4476
David S. Millerf86e82f2008-01-21 17:15:40 -08004477 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
Michael Chanb6016b72005-05-26 13:03:09 -07004478 val |= (1 << 23);
4479
4480 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
David S. Millerf86e82f2008-01-21 17:15:40 -08004481 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
Michael Chanb6016b72005-05-26 13:03:09 -07004482 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4483
4484 REG_WR(bp, BNX2_DMA_CONFIG, val);
4485
4486 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4487 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4488 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4489 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4490 }
4491
David S. Millerf86e82f2008-01-21 17:15:40 -08004492 if (bp->flags & BNX2_FLAG_PCIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07004493 u16 val16;
4494
4495 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4496 &val16);
4497 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4498 val16 & ~PCI_X_CMD_ERO);
4499 }
4500
4501 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4502 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4503 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4504 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4505
4506 /* Initialize context mapping and zero out the quick contexts. The
4507 * context block must have already been enabled. */
Michael Chan641bdcd2007-06-04 21:22:24 -07004508 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4509 rc = bnx2_init_5709_context(bp);
4510 if (rc)
4511 return rc;
4512 } else
Michael Chan59b47d82006-11-19 14:10:45 -08004513 bnx2_init_context(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07004514
Michael Chanfba9fe92006-06-12 22:21:25 -07004515 if ((rc = bnx2_init_cpus(bp)) != 0)
4516 return rc;
4517
Michael Chanb6016b72005-05-26 13:03:09 -07004518 bnx2_init_nvram(bp);
4519
Benjamin Li5fcaed02008-07-14 22:39:52 -07004520 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07004521
4522 val = REG_RD(bp, BNX2_MQ_CONFIG);
4523 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4524 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
Michael Chan68c9f752007-04-24 15:35:53 -07004525 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4526 val |= BNX2_MQ_CONFIG_HALT_DIS;
4527
Michael Chanb6016b72005-05-26 13:03:09 -07004528 REG_WR(bp, BNX2_MQ_CONFIG, val);
4529
4530 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4531 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4532 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4533
4534 val = (BCM_PAGE_BITS - 8) << 24;
4535 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4536
4537 /* Configure page size. */
4538 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4539 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4540 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4541 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4542
4543 val = bp->mac_addr[0] +
4544 (bp->mac_addr[1] << 8) +
4545 (bp->mac_addr[2] << 16) +
4546 bp->mac_addr[3] +
4547 (bp->mac_addr[4] << 8) +
4548 (bp->mac_addr[5] << 16);
4549 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4550
4551 /* Program the MTU. Also include 4 bytes for CRC32. */
4552 val = bp->dev->mtu + ETH_HLEN + 4;
4553 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4554 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4555 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4556
Michael Chanb4b36042007-12-20 19:59:30 -08004557 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4558 bp->bnx2_napi[i].last_status_idx = 0;
4559
Michael Chanb6016b72005-05-26 13:03:09 -07004560 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4561
4562 /* Set up how to generate a link change interrupt. */
4563 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4564
4565 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4566 (u64) bp->status_blk_mapping & 0xffffffff);
4567 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4568
4569 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4570 (u64) bp->stats_blk_mapping & 0xffffffff);
4571 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4572 (u64) bp->stats_blk_mapping >> 32);
4573
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004574 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
Michael Chanb6016b72005-05-26 13:03:09 -07004575 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4576
4577 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4578 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4579
4580 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4581 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4582
4583 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4584
4585 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4586
4587 REG_WR(bp, BNX2_HC_COM_TICKS,
4588 (bp->com_ticks_int << 16) | bp->com_ticks);
4589
4590 REG_WR(bp, BNX2_HC_CMD_TICKS,
4591 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4592
Michael Chan02537b062007-06-04 21:24:07 -07004593 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4594 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4595 else
Michael Chan7ea69202007-07-16 18:27:10 -07004596 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
Michael Chanb6016b72005-05-26 13:03:09 -07004597 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4598
4599 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
Michael Chan8e6a72c2007-05-03 13:24:48 -07004600 val = BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004601 else {
Michael Chan8e6a72c2007-05-03 13:24:48 -07004602 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4603 BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004604 }
4605
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004606 if (bp->irq_nvecs > 1) {
Michael Chanc76c0472007-12-20 20:01:19 -08004607 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4608 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4609
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004610 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4611 }
4612
4613 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4614 val |= BNX2_HC_CONFIG_ONE_SHOT;
4615
4616 REG_WR(bp, BNX2_HC_CONFIG, val);
4617
4618 for (i = 1; i < bp->irq_nvecs; i++) {
4619 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4620 BNX2_HC_SB_CONFIG_1;
4621
Michael Chan6f743ca2008-01-29 21:34:08 -08004622 REG_WR(bp, base,
Michael Chanc76c0472007-12-20 20:01:19 -08004623 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004624 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
Michael Chanc76c0472007-12-20 20:01:19 -08004625 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4626
Michael Chan6f743ca2008-01-29 21:34:08 -08004627 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08004628 (bp->tx_quick_cons_trip_int << 16) |
4629 bp->tx_quick_cons_trip);
4630
Michael Chan6f743ca2008-01-29 21:34:08 -08004631 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08004632 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4633
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004634 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4635 (bp->rx_quick_cons_trip_int << 16) |
4636 bp->rx_quick_cons_trip);
4637
4638 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4639 (bp->rx_ticks_int << 16) | bp->rx_ticks);
Michael Chanc76c0472007-12-20 20:01:19 -08004640 }
4641
Michael Chanb6016b72005-05-26 13:03:09 -07004642 /* Clear internal stats counters. */
4643 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4644
Michael Chanda3e4fb2007-05-03 13:24:23 -07004645 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
Michael Chanb6016b72005-05-26 13:03:09 -07004646
4647 /* Initialize the receive filter. */
4648 bnx2_set_rx_mode(bp->dev);
4649
Michael Chan0aa38df2007-06-04 21:23:06 -07004650 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4651 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4652 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4653 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4654 }
Michael Chanb090ae22006-01-23 16:07:10 -08004655 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
Michael Chana2f13892008-07-14 22:38:23 -07004656 1, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07004657
Michael Chandf149d72007-07-07 22:51:36 -07004658 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
Michael Chanb6016b72005-05-26 13:03:09 -07004659 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4660
4661 udelay(20);
4662
Michael Chanbf5295b2006-03-23 01:11:56 -08004663 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4664
Michael Chanb090ae22006-01-23 16:07:10 -08004665 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004666}
4667
Michael Chan59b47d82006-11-19 14:10:45 -08004668static void
Michael Chanc76c0472007-12-20 20:01:19 -08004669bnx2_clear_ring_states(struct bnx2 *bp)
4670{
4671 struct bnx2_napi *bnapi;
Michael Chan35e90102008-06-19 16:37:42 -07004672 struct bnx2_tx_ring_info *txr;
Michael Chanbb4f98a2008-06-19 16:38:19 -07004673 struct bnx2_rx_ring_info *rxr;
Michael Chanc76c0472007-12-20 20:01:19 -08004674 int i;
4675
4676 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4677 bnapi = &bp->bnx2_napi[i];
Michael Chan35e90102008-06-19 16:37:42 -07004678 txr = &bnapi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07004679 rxr = &bnapi->rx_ring;
Michael Chanc76c0472007-12-20 20:01:19 -08004680
Michael Chan35e90102008-06-19 16:37:42 -07004681 txr->tx_cons = 0;
4682 txr->hw_tx_cons = 0;
Michael Chanbb4f98a2008-06-19 16:38:19 -07004683 rxr->rx_prod_bseq = 0;
4684 rxr->rx_prod = 0;
4685 rxr->rx_cons = 0;
4686 rxr->rx_pg_prod = 0;
4687 rxr->rx_pg_cons = 0;
Michael Chanc76c0472007-12-20 20:01:19 -08004688 }
4689}
4690
4691static void
Michael Chan35e90102008-06-19 16:37:42 -07004692bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
Michael Chan59b47d82006-11-19 14:10:45 -08004693{
4694 u32 val, offset0, offset1, offset2, offset3;
Michael Chan62a83132008-01-29 21:35:40 -08004695 u32 cid_addr = GET_CID_ADDR(cid);
Michael Chan59b47d82006-11-19 14:10:45 -08004696
4697 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4698 offset0 = BNX2_L2CTX_TYPE_XI;
4699 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4700 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4701 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4702 } else {
4703 offset0 = BNX2_L2CTX_TYPE;
4704 offset1 = BNX2_L2CTX_CMD_TYPE;
4705 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4706 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4707 }
4708 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
Michael Chan62a83132008-01-29 21:35:40 -08004709 bnx2_ctx_wr(bp, cid_addr, offset0, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004710
4711 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
Michael Chan62a83132008-01-29 21:35:40 -08004712 bnx2_ctx_wr(bp, cid_addr, offset1, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004713
Michael Chan35e90102008-06-19 16:37:42 -07004714 val = (u64) txr->tx_desc_mapping >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08004715 bnx2_ctx_wr(bp, cid_addr, offset2, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004716
Michael Chan35e90102008-06-19 16:37:42 -07004717 val = (u64) txr->tx_desc_mapping & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08004718 bnx2_ctx_wr(bp, cid_addr, offset3, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004719}
Michael Chanb6016b72005-05-26 13:03:09 -07004720
4721static void
Michael Chan35e90102008-06-19 16:37:42 -07004722bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
Michael Chanb6016b72005-05-26 13:03:09 -07004723{
4724 struct tx_bd *txbd;
Michael Chanc76c0472007-12-20 20:01:19 -08004725 u32 cid = TX_CID;
4726 struct bnx2_napi *bnapi;
Michael Chan35e90102008-06-19 16:37:42 -07004727 struct bnx2_tx_ring_info *txr;
Michael Chanc76c0472007-12-20 20:01:19 -08004728
Michael Chan35e90102008-06-19 16:37:42 -07004729 bnapi = &bp->bnx2_napi[ring_num];
4730 txr = &bnapi->tx_ring;
4731
4732 if (ring_num == 0)
4733 cid = TX_CID;
4734 else
4735 cid = TX_TSS_CID + ring_num - 1;
Michael Chanb6016b72005-05-26 13:03:09 -07004736
Michael Chan2f8af122006-08-15 01:39:10 -07004737 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4738
Michael Chan35e90102008-06-19 16:37:42 -07004739 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004740
Michael Chan35e90102008-06-19 16:37:42 -07004741 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4742 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
Michael Chanb6016b72005-05-26 13:03:09 -07004743
Michael Chan35e90102008-06-19 16:37:42 -07004744 txr->tx_prod = 0;
4745 txr->tx_prod_bseq = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004746
Michael Chan35e90102008-06-19 16:37:42 -07004747 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4748 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
Michael Chanb6016b72005-05-26 13:03:09 -07004749
Michael Chan35e90102008-06-19 16:37:42 -07004750 bnx2_init_tx_context(bp, cid, txr);
Michael Chanb6016b72005-05-26 13:03:09 -07004751}
4752
4753static void
Michael Chan5d5d0012007-12-12 11:17:43 -08004754bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4755 int num_rings)
Michael Chanb6016b72005-05-26 13:03:09 -07004756{
Michael Chanb6016b72005-05-26 13:03:09 -07004757 int i;
Michael Chan5d5d0012007-12-12 11:17:43 -08004758 struct rx_bd *rxbd;
Michael Chanb6016b72005-05-26 13:03:09 -07004759
Michael Chan5d5d0012007-12-12 11:17:43 -08004760 for (i = 0; i < num_rings; i++) {
Michael Chan13daffa2006-03-20 17:49:20 -08004761 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07004762
Michael Chan5d5d0012007-12-12 11:17:43 -08004763 rxbd = &rx_ring[i][0];
Michael Chan13daffa2006-03-20 17:49:20 -08004764 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
Michael Chan5d5d0012007-12-12 11:17:43 -08004765 rxbd->rx_bd_len = buf_size;
Michael Chan13daffa2006-03-20 17:49:20 -08004766 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4767 }
Michael Chan5d5d0012007-12-12 11:17:43 -08004768 if (i == (num_rings - 1))
Michael Chan13daffa2006-03-20 17:49:20 -08004769 j = 0;
4770 else
4771 j = i + 1;
Michael Chan5d5d0012007-12-12 11:17:43 -08004772 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4773 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
Michael Chan13daffa2006-03-20 17:49:20 -08004774 }
Michael Chan5d5d0012007-12-12 11:17:43 -08004775}
4776
4777static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07004778bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
Michael Chan5d5d0012007-12-12 11:17:43 -08004779{
4780 int i;
4781 u16 prod, ring_prod;
Michael Chanbb4f98a2008-06-19 16:38:19 -07004782 u32 cid, rx_cid_addr, val;
4783 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4784 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chan5d5d0012007-12-12 11:17:43 -08004785
Michael Chanbb4f98a2008-06-19 16:38:19 -07004786 if (ring_num == 0)
4787 cid = RX_CID;
4788 else
4789 cid = RX_RSS_CID + ring_num - 1;
4790
4791 rx_cid_addr = GET_CID_ADDR(cid);
4792
4793 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
Michael Chan5d5d0012007-12-12 11:17:43 -08004794 bp->rx_buf_use_size, bp->rx_max_ring);
4795
Michael Chanbb4f98a2008-06-19 16:38:19 -07004796 bnx2_init_rx_context(bp, cid);
Michael Chan83e3fc82008-01-29 21:37:17 -08004797
4798 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4799 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4800 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4801 }
4802
Michael Chan62a83132008-01-29 21:35:40 -08004803 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
Michael Chan47bf4242007-12-12 11:19:12 -08004804 if (bp->rx_pg_ring_size) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07004805 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4806 rxr->rx_pg_desc_mapping,
Michael Chan47bf4242007-12-12 11:19:12 -08004807 PAGE_SIZE, bp->rx_max_pg_ring);
4808 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
Michael Chan62a83132008-01-29 21:35:40 -08004809 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4810 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004811 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
Michael Chan47bf4242007-12-12 11:19:12 -08004812
Michael Chanbb4f98a2008-06-19 16:38:19 -07004813 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08004814 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
Michael Chan47bf4242007-12-12 11:19:12 -08004815
Michael Chanbb4f98a2008-06-19 16:38:19 -07004816 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08004817 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
Michael Chan47bf4242007-12-12 11:19:12 -08004818
4819 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4820 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4821 }
Michael Chanb6016b72005-05-26 13:03:09 -07004822
Michael Chanbb4f98a2008-06-19 16:38:19 -07004823 val = (u64) rxr->rx_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08004824 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004825
Michael Chanbb4f98a2008-06-19 16:38:19 -07004826 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08004827 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004828
Michael Chanbb4f98a2008-06-19 16:38:19 -07004829 ring_prod = prod = rxr->rx_pg_prod;
Michael Chan47bf4242007-12-12 11:19:12 -08004830 for (i = 0; i < bp->rx_pg_ring_size; i++) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07004831 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
Michael Chan47bf4242007-12-12 11:19:12 -08004832 break;
4833 prod = NEXT_RX_BD(prod);
4834 ring_prod = RX_PG_RING_IDX(prod);
4835 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07004836 rxr->rx_pg_prod = prod;
Michael Chan47bf4242007-12-12 11:19:12 -08004837
Michael Chanbb4f98a2008-06-19 16:38:19 -07004838 ring_prod = prod = rxr->rx_prod;
Michael Chan236b6392006-03-20 17:49:02 -08004839 for (i = 0; i < bp->rx_ring_size; i++) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07004840 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
Michael Chanb6016b72005-05-26 13:03:09 -07004841 break;
Michael Chanb6016b72005-05-26 13:03:09 -07004842 prod = NEXT_RX_BD(prod);
4843 ring_prod = RX_RING_IDX(prod);
4844 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07004845 rxr->rx_prod = prod;
Michael Chanb6016b72005-05-26 13:03:09 -07004846
Michael Chanbb4f98a2008-06-19 16:38:19 -07004847 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4848 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4849 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
Michael Chanb6016b72005-05-26 13:03:09 -07004850
Michael Chanbb4f98a2008-06-19 16:38:19 -07004851 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4852 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4853
4854 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07004855}
4856
Michael Chan35e90102008-06-19 16:37:42 -07004857static void
4858bnx2_init_all_rings(struct bnx2 *bp)
4859{
4860 int i;
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004861 u32 val;
Michael Chan35e90102008-06-19 16:37:42 -07004862
4863 bnx2_clear_ring_states(bp);
4864
4865 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4866 for (i = 0; i < bp->num_tx_rings; i++)
4867 bnx2_init_tx_ring(bp, i);
4868
4869 if (bp->num_tx_rings > 1)
4870 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4871 (TX_TSS_CID << 7));
4872
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004873 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4874 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4875
Michael Chanbb4f98a2008-06-19 16:38:19 -07004876 for (i = 0; i < bp->num_rx_rings; i++)
4877 bnx2_init_rx_ring(bp, i);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004878
4879 if (bp->num_rx_rings > 1) {
4880 u32 tbl_32;
4881 u8 *tbl = (u8 *) &tbl_32;
4882
4883 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4884 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4885
4886 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4887 tbl[i % 4] = i % (bp->num_rx_rings - 1);
4888 if ((i % 4) == 3)
4889 bnx2_reg_wr_ind(bp,
4890 BNX2_RXP_SCRATCH_RSS_TBL + i,
4891 cpu_to_be32(tbl_32));
4892 }
4893
4894 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4895 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4896
4897 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4898
4899 }
Michael Chan35e90102008-06-19 16:37:42 -07004900}
4901
Michael Chan5d5d0012007-12-12 11:17:43 -08004902static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
Michael Chan13daffa2006-03-20 17:49:20 -08004903{
Michael Chan5d5d0012007-12-12 11:17:43 -08004904 u32 max, num_rings = 1;
Michael Chan13daffa2006-03-20 17:49:20 -08004905
Michael Chan5d5d0012007-12-12 11:17:43 -08004906 while (ring_size > MAX_RX_DESC_CNT) {
4907 ring_size -= MAX_RX_DESC_CNT;
Michael Chan13daffa2006-03-20 17:49:20 -08004908 num_rings++;
4909 }
4910 /* round to next power of 2 */
Michael Chan5d5d0012007-12-12 11:17:43 -08004911 max = max_size;
Michael Chan13daffa2006-03-20 17:49:20 -08004912 while ((max & num_rings) == 0)
4913 max >>= 1;
4914
4915 if (num_rings != max)
4916 max <<= 1;
4917
Michael Chan5d5d0012007-12-12 11:17:43 -08004918 return max;
4919}
4920
4921static void
4922bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4923{
Michael Chan84eaa182007-12-12 11:19:57 -08004924 u32 rx_size, rx_space, jumbo_size;
Michael Chan5d5d0012007-12-12 11:17:43 -08004925
4926 /* 8 for CRC and VLAN */
Benjamin Lid89cb6a2008-05-16 22:18:57 -07004927 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
Michael Chan5d5d0012007-12-12 11:17:43 -08004928
Michael Chan84eaa182007-12-12 11:19:57 -08004929 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4930 sizeof(struct skb_shared_info);
4931
Benjamin Li601d3d12008-05-16 22:19:35 -07004932 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
Michael Chan47bf4242007-12-12 11:19:12 -08004933 bp->rx_pg_ring_size = 0;
4934 bp->rx_max_pg_ring = 0;
4935 bp->rx_max_pg_ring_idx = 0;
David S. Millerf86e82f2008-01-21 17:15:40 -08004936 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
Michael Chan84eaa182007-12-12 11:19:57 -08004937 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4938
4939 jumbo_size = size * pages;
4940 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4941 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4942
4943 bp->rx_pg_ring_size = jumbo_size;
4944 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4945 MAX_RX_PG_RINGS);
4946 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
Benjamin Li601d3d12008-05-16 22:19:35 -07004947 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
Michael Chan84eaa182007-12-12 11:19:57 -08004948 bp->rx_copy_thresh = 0;
4949 }
Michael Chan5d5d0012007-12-12 11:17:43 -08004950
4951 bp->rx_buf_use_size = rx_size;
4952 /* hw alignment */
4953 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
Benjamin Lid89cb6a2008-05-16 22:18:57 -07004954 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
Michael Chan5d5d0012007-12-12 11:17:43 -08004955 bp->rx_ring_size = size;
4956 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
Michael Chan13daffa2006-03-20 17:49:20 -08004957 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4958}
4959
4960static void
Michael Chanb6016b72005-05-26 13:03:09 -07004961bnx2_free_tx_skbs(struct bnx2 *bp)
4962{
4963 int i;
4964
Michael Chan35e90102008-06-19 16:37:42 -07004965 for (i = 0; i < bp->num_tx_rings; i++) {
4966 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4967 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
4968 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07004969
Michael Chan35e90102008-06-19 16:37:42 -07004970 if (txr->tx_buf_ring == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07004971 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07004972
Michael Chan35e90102008-06-19 16:37:42 -07004973 for (j = 0; j < TX_DESC_CNT; ) {
4974 struct sw_bd *tx_buf = &txr->tx_buf_ring[j];
4975 struct sk_buff *skb = tx_buf->skb;
4976 int k, last;
4977
4978 if (skb == NULL) {
4979 j++;
4980 continue;
4981 }
4982
4983 pci_unmap_single(bp->pdev,
4984 pci_unmap_addr(tx_buf, mapping),
Michael Chanb6016b72005-05-26 13:03:09 -07004985 skb_headlen(skb), PCI_DMA_TODEVICE);
4986
Michael Chan35e90102008-06-19 16:37:42 -07004987 tx_buf->skb = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07004988
Michael Chan35e90102008-06-19 16:37:42 -07004989 last = skb_shinfo(skb)->nr_frags;
4990 for (k = 0; k < last; k++) {
4991 tx_buf = &txr->tx_buf_ring[j + k + 1];
4992 pci_unmap_page(bp->pdev,
4993 pci_unmap_addr(tx_buf, mapping),
4994 skb_shinfo(skb)->frags[j].size,
4995 PCI_DMA_TODEVICE);
4996 }
4997 dev_kfree_skb(skb);
4998 j += k + 1;
Michael Chanb6016b72005-05-26 13:03:09 -07004999 }
Michael Chanb6016b72005-05-26 13:03:09 -07005000 }
Michael Chanb6016b72005-05-26 13:03:09 -07005001}
5002
5003static void
5004bnx2_free_rx_skbs(struct bnx2 *bp)
5005{
5006 int i;
5007
Michael Chanbb4f98a2008-06-19 16:38:19 -07005008 for (i = 0; i < bp->num_rx_rings; i++) {
5009 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5010 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5011 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07005012
Michael Chanbb4f98a2008-06-19 16:38:19 -07005013 if (rxr->rx_buf_ring == NULL)
5014 return;
Michael Chanb6016b72005-05-26 13:03:09 -07005015
Michael Chanbb4f98a2008-06-19 16:38:19 -07005016 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5017 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5018 struct sk_buff *skb = rx_buf->skb;
Michael Chanb6016b72005-05-26 13:03:09 -07005019
Michael Chanbb4f98a2008-06-19 16:38:19 -07005020 if (skb == NULL)
5021 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005022
Michael Chanbb4f98a2008-06-19 16:38:19 -07005023 pci_unmap_single(bp->pdev,
5024 pci_unmap_addr(rx_buf, mapping),
5025 bp->rx_buf_use_size,
5026 PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07005027
Michael Chanbb4f98a2008-06-19 16:38:19 -07005028 rx_buf->skb = NULL;
5029
5030 dev_kfree_skb(skb);
5031 }
5032 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5033 bnx2_free_rx_page(bp, rxr, j);
Michael Chanb6016b72005-05-26 13:03:09 -07005034 }
5035}
5036
5037static void
5038bnx2_free_skbs(struct bnx2 *bp)
5039{
5040 bnx2_free_tx_skbs(bp);
5041 bnx2_free_rx_skbs(bp);
5042}
5043
5044static int
5045bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5046{
5047 int rc;
5048
5049 rc = bnx2_reset_chip(bp, reset_code);
5050 bnx2_free_skbs(bp);
5051 if (rc)
5052 return rc;
5053
Michael Chanfba9fe92006-06-12 22:21:25 -07005054 if ((rc = bnx2_init_chip(bp)) != 0)
5055 return rc;
5056
Michael Chan35e90102008-06-19 16:37:42 -07005057 bnx2_init_all_rings(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005058 return 0;
5059}
5060
5061static int
Michael Chan9a120bc2008-05-16 22:17:45 -07005062bnx2_init_nic(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07005063{
5064 int rc;
5065
5066 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5067 return rc;
5068
Michael Chan80be4432006-11-19 14:07:28 -08005069 spin_lock_bh(&bp->phy_lock);
Michael Chan9a120bc2008-05-16 22:17:45 -07005070 bnx2_init_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07005071 bnx2_set_link(bp);
Michael Chan543a8272008-05-02 16:56:44 -07005072 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5073 bnx2_remote_phy_event(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07005074 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07005075 return 0;
5076}
5077
5078static int
Michael Chan74bf4ba2008-10-09 12:21:08 -07005079bnx2_shutdown_chip(struct bnx2 *bp)
5080{
5081 u32 reset_code;
5082
5083 if (bp->flags & BNX2_FLAG_NO_WOL)
5084 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5085 else if (bp->wol)
5086 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5087 else
5088 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5089
5090 return bnx2_reset_chip(bp, reset_code);
5091}
5092
5093static int
Michael Chanb6016b72005-05-26 13:03:09 -07005094bnx2_test_registers(struct bnx2 *bp)
5095{
5096 int ret;
Michael Chan5bae30c2007-05-03 13:18:46 -07005097 int i, is_5709;
Arjan van de Venf71e1302006-03-03 21:33:57 -05005098 static const struct {
Michael Chanb6016b72005-05-26 13:03:09 -07005099 u16 offset;
5100 u16 flags;
Michael Chan5bae30c2007-05-03 13:18:46 -07005101#define BNX2_FL_NOT_5709 1
Michael Chanb6016b72005-05-26 13:03:09 -07005102 u32 rw_mask;
5103 u32 ro_mask;
5104 } reg_tbl[] = {
5105 { 0x006c, 0, 0x00000000, 0x0000003f },
5106 { 0x0090, 0, 0xffffffff, 0x00000000 },
5107 { 0x0094, 0, 0x00000000, 0x00000000 },
5108
Michael Chan5bae30c2007-05-03 13:18:46 -07005109 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5110 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5111 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5112 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5113 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5114 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5115 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5116 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5117 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
Michael Chanb6016b72005-05-26 13:03:09 -07005118
Michael Chan5bae30c2007-05-03 13:18:46 -07005119 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5120 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5121 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5122 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5123 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5124 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
Michael Chanb6016b72005-05-26 13:03:09 -07005125
Michael Chan5bae30c2007-05-03 13:18:46 -07005126 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5127 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5128 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005129
5130 { 0x1000, 0, 0x00000000, 0x00000001 },
Michael Chan15b169c2008-05-02 16:57:08 -07005131 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
Michael Chanb6016b72005-05-26 13:03:09 -07005132
5133 { 0x1408, 0, 0x01c00800, 0x00000000 },
5134 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5135 { 0x14a8, 0, 0x00000000, 0x000001ff },
Michael Chan5b0c76a2005-11-04 08:45:49 -08005136 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005137 { 0x14b0, 0, 0x00000002, 0x00000001 },
5138 { 0x14b8, 0, 0x00000000, 0x00000000 },
5139 { 0x14c0, 0, 0x00000000, 0x00000009 },
5140 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5141 { 0x14cc, 0, 0x00000000, 0x00000001 },
5142 { 0x14d0, 0, 0xffffffff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005143
5144 { 0x1800, 0, 0x00000000, 0x00000001 },
5145 { 0x1804, 0, 0x00000000, 0x00000003 },
Michael Chanb6016b72005-05-26 13:03:09 -07005146
5147 { 0x2800, 0, 0x00000000, 0x00000001 },
5148 { 0x2804, 0, 0x00000000, 0x00003f01 },
5149 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5150 { 0x2810, 0, 0xffff0000, 0x00000000 },
5151 { 0x2814, 0, 0xffff0000, 0x00000000 },
5152 { 0x2818, 0, 0xffff0000, 0x00000000 },
5153 { 0x281c, 0, 0xffff0000, 0x00000000 },
5154 { 0x2834, 0, 0xffffffff, 0x00000000 },
5155 { 0x2840, 0, 0x00000000, 0xffffffff },
5156 { 0x2844, 0, 0x00000000, 0xffffffff },
5157 { 0x2848, 0, 0xffffffff, 0x00000000 },
5158 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5159
5160 { 0x2c00, 0, 0x00000000, 0x00000011 },
5161 { 0x2c04, 0, 0x00000000, 0x00030007 },
5162
Michael Chanb6016b72005-05-26 13:03:09 -07005163 { 0x3c00, 0, 0x00000000, 0x00000001 },
5164 { 0x3c04, 0, 0x00000000, 0x00070000 },
5165 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5166 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5167 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5168 { 0x3c14, 0, 0x00000000, 0xffffffff },
5169 { 0x3c18, 0, 0x00000000, 0xffffffff },
5170 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5171 { 0x3c20, 0, 0xffffff00, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005172
5173 { 0x5004, 0, 0x00000000, 0x0000007f },
5174 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005175
Michael Chanb6016b72005-05-26 13:03:09 -07005176 { 0x5c00, 0, 0x00000000, 0x00000001 },
5177 { 0x5c04, 0, 0x00000000, 0x0003000f },
5178 { 0x5c08, 0, 0x00000003, 0x00000000 },
5179 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5180 { 0x5c10, 0, 0x00000000, 0xffffffff },
5181 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5182 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5183 { 0x5c88, 0, 0x00000000, 0x00077373 },
5184 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5185
5186 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5187 { 0x680c, 0, 0xffffffff, 0x00000000 },
5188 { 0x6810, 0, 0xffffffff, 0x00000000 },
5189 { 0x6814, 0, 0xffffffff, 0x00000000 },
5190 { 0x6818, 0, 0xffffffff, 0x00000000 },
5191 { 0x681c, 0, 0xffffffff, 0x00000000 },
5192 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5193 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5194 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5195 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5196 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5197 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5198 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5199 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5200 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5201 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5202 { 0x684c, 0, 0xffffffff, 0x00000000 },
5203 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5204 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5205 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5206 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5207 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5208 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5209
5210 { 0xffff, 0, 0x00000000, 0x00000000 },
5211 };
5212
5213 ret = 0;
Michael Chan5bae30c2007-05-03 13:18:46 -07005214 is_5709 = 0;
5215 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5216 is_5709 = 1;
5217
Michael Chanb6016b72005-05-26 13:03:09 -07005218 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5219 u32 offset, rw_mask, ro_mask, save_val, val;
Michael Chan5bae30c2007-05-03 13:18:46 -07005220 u16 flags = reg_tbl[i].flags;
5221
5222 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5223 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005224
5225 offset = (u32) reg_tbl[i].offset;
5226 rw_mask = reg_tbl[i].rw_mask;
5227 ro_mask = reg_tbl[i].ro_mask;
5228
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005229 save_val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005230
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005231 writel(0, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005232
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005233 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005234 if ((val & rw_mask) != 0) {
5235 goto reg_test_err;
5236 }
5237
5238 if ((val & ro_mask) != (save_val & ro_mask)) {
5239 goto reg_test_err;
5240 }
5241
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005242 writel(0xffffffff, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005243
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005244 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005245 if ((val & rw_mask) != rw_mask) {
5246 goto reg_test_err;
5247 }
5248
5249 if ((val & ro_mask) != (save_val & ro_mask)) {
5250 goto reg_test_err;
5251 }
5252
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005253 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005254 continue;
5255
5256reg_test_err:
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005257 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005258 ret = -ENODEV;
5259 break;
5260 }
5261 return ret;
5262}
5263
5264static int
5265bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5266{
Arjan van de Venf71e1302006-03-03 21:33:57 -05005267 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
Michael Chanb6016b72005-05-26 13:03:09 -07005268 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5269 int i;
5270
5271 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5272 u32 offset;
5273
5274 for (offset = 0; offset < size; offset += 4) {
5275
Michael Chan2726d6e2008-01-29 21:35:05 -08005276 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
Michael Chanb6016b72005-05-26 13:03:09 -07005277
Michael Chan2726d6e2008-01-29 21:35:05 -08005278 if (bnx2_reg_rd_ind(bp, start + offset) !=
Michael Chanb6016b72005-05-26 13:03:09 -07005279 test_pattern[i]) {
5280 return -ENODEV;
5281 }
5282 }
5283 }
5284 return 0;
5285}
5286
5287static int
5288bnx2_test_memory(struct bnx2 *bp)
5289{
5290 int ret = 0;
5291 int i;
Michael Chan5bae30c2007-05-03 13:18:46 -07005292 static struct mem_entry {
Michael Chanb6016b72005-05-26 13:03:09 -07005293 u32 offset;
5294 u32 len;
Michael Chan5bae30c2007-05-03 13:18:46 -07005295 } mem_tbl_5706[] = {
Michael Chanb6016b72005-05-26 13:03:09 -07005296 { 0x60000, 0x4000 },
Michael Chan5b0c76a2005-11-04 08:45:49 -08005297 { 0xa0000, 0x3000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005298 { 0xe0000, 0x4000 },
5299 { 0x120000, 0x4000 },
5300 { 0x1a0000, 0x4000 },
5301 { 0x160000, 0x4000 },
5302 { 0xffffffff, 0 },
Michael Chan5bae30c2007-05-03 13:18:46 -07005303 },
5304 mem_tbl_5709[] = {
5305 { 0x60000, 0x4000 },
5306 { 0xa0000, 0x3000 },
5307 { 0xe0000, 0x4000 },
5308 { 0x120000, 0x4000 },
5309 { 0x1a0000, 0x4000 },
5310 { 0xffffffff, 0 },
Michael Chanb6016b72005-05-26 13:03:09 -07005311 };
Michael Chan5bae30c2007-05-03 13:18:46 -07005312 struct mem_entry *mem_tbl;
5313
5314 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5315 mem_tbl = mem_tbl_5709;
5316 else
5317 mem_tbl = mem_tbl_5706;
Michael Chanb6016b72005-05-26 13:03:09 -07005318
5319 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5320 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5321 mem_tbl[i].len)) != 0) {
5322 return ret;
5323 }
5324 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005325
Michael Chanb6016b72005-05-26 13:03:09 -07005326 return ret;
5327}
5328
Michael Chanbc5a0692006-01-23 16:13:22 -08005329#define BNX2_MAC_LOOPBACK 0
5330#define BNX2_PHY_LOOPBACK 1
5331
Michael Chanb6016b72005-05-26 13:03:09 -07005332static int
Michael Chanbc5a0692006-01-23 16:13:22 -08005333bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
Michael Chanb6016b72005-05-26 13:03:09 -07005334{
5335 unsigned int pkt_size, num_pkts, i;
5336 struct sk_buff *skb, *rx_skb;
5337 unsigned char *packet;
Michael Chanbc5a0692006-01-23 16:13:22 -08005338 u16 rx_start_idx, rx_idx;
Michael Chanb6016b72005-05-26 13:03:09 -07005339 dma_addr_t map;
5340 struct tx_bd *txbd;
5341 struct sw_bd *rx_buf;
5342 struct l2_fhdr *rx_hdr;
5343 int ret = -ENODEV;
Michael Chanc76c0472007-12-20 20:01:19 -08005344 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
Michael Chan35e90102008-06-19 16:37:42 -07005345 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005346 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanc76c0472007-12-20 20:01:19 -08005347
5348 tx_napi = bnapi;
Michael Chanb6016b72005-05-26 13:03:09 -07005349
Michael Chan35e90102008-06-19 16:37:42 -07005350 txr = &tx_napi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005351 rxr = &bnapi->rx_ring;
Michael Chanbc5a0692006-01-23 16:13:22 -08005352 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5353 bp->loopback = MAC_LOOPBACK;
5354 bnx2_set_mac_loopback(bp);
5355 }
5356 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
Michael Chan583c28e2008-01-21 19:51:35 -08005357 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan489310a2007-10-10 16:16:31 -07005358 return 0;
5359
Michael Chan80be4432006-11-19 14:07:28 -08005360 bp->loopback = PHY_LOOPBACK;
Michael Chanbc5a0692006-01-23 16:13:22 -08005361 bnx2_set_phy_loopback(bp);
5362 }
5363 else
5364 return -EINVAL;
Michael Chanb6016b72005-05-26 13:03:09 -07005365
Michael Chan84eaa182007-12-12 11:19:57 -08005366 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
Michael Chan932f3772006-08-15 01:39:36 -07005367 skb = netdev_alloc_skb(bp->dev, pkt_size);
John W. Linvilleb6cbc3b62005-11-10 12:58:00 -08005368 if (!skb)
5369 return -ENOMEM;
Michael Chanb6016b72005-05-26 13:03:09 -07005370 packet = skb_put(skb, pkt_size);
Michael Chan66342922006-12-14 15:57:04 -08005371 memcpy(packet, bp->dev->dev_addr, 6);
Michael Chanb6016b72005-05-26 13:03:09 -07005372 memset(packet + 6, 0x0, 8);
5373 for (i = 14; i < pkt_size; i++)
5374 packet[i] = (unsigned char) (i & 0xff);
5375
5376 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5377 PCI_DMA_TODEVICE);
5378
Michael Chanbf5295b2006-03-23 01:11:56 -08005379 REG_WR(bp, BNX2_HC_COMMAND,
5380 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5381
Michael Chanb6016b72005-05-26 13:03:09 -07005382 REG_RD(bp, BNX2_HC_COMMAND);
5383
5384 udelay(5);
Michael Chan35efa7c2007-12-20 19:56:37 -08005385 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005386
Michael Chanb6016b72005-05-26 13:03:09 -07005387 num_pkts = 0;
5388
Michael Chan35e90102008-06-19 16:37:42 -07005389 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
Michael Chanb6016b72005-05-26 13:03:09 -07005390
5391 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5392 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5393 txbd->tx_bd_mss_nbytes = pkt_size;
5394 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5395
5396 num_pkts++;
Michael Chan35e90102008-06-19 16:37:42 -07005397 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5398 txr->tx_prod_bseq += pkt_size;
Michael Chanb6016b72005-05-26 13:03:09 -07005399
Michael Chan35e90102008-06-19 16:37:42 -07005400 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5401 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07005402
5403 udelay(100);
5404
Michael Chanbf5295b2006-03-23 01:11:56 -08005405 REG_WR(bp, BNX2_HC_COMMAND,
5406 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5407
Michael Chanb6016b72005-05-26 13:03:09 -07005408 REG_RD(bp, BNX2_HC_COMMAND);
5409
5410 udelay(5);
5411
5412 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
Michael Chan745720e2006-06-29 12:37:41 -07005413 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07005414
Michael Chan35e90102008-06-19 16:37:42 -07005415 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
Michael Chanb6016b72005-05-26 13:03:09 -07005416 goto loopback_test_done;
Michael Chanb6016b72005-05-26 13:03:09 -07005417
Michael Chan35efa7c2007-12-20 19:56:37 -08005418 rx_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005419 if (rx_idx != rx_start_idx + num_pkts) {
5420 goto loopback_test_done;
5421 }
5422
Michael Chanbb4f98a2008-06-19 16:38:19 -07005423 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
Michael Chanb6016b72005-05-26 13:03:09 -07005424 rx_skb = rx_buf->skb;
5425
5426 rx_hdr = (struct l2_fhdr *) rx_skb->data;
Benjamin Lid89cb6a2008-05-16 22:18:57 -07005427 skb_reserve(rx_skb, BNX2_RX_OFFSET);
Michael Chanb6016b72005-05-26 13:03:09 -07005428
5429 pci_dma_sync_single_for_cpu(bp->pdev,
5430 pci_unmap_addr(rx_buf, mapping),
5431 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5432
Michael Chanade2bfe2006-01-23 16:09:51 -08005433 if (rx_hdr->l2_fhdr_status &
Michael Chanb6016b72005-05-26 13:03:09 -07005434 (L2_FHDR_ERRORS_BAD_CRC |
5435 L2_FHDR_ERRORS_PHY_DECODE |
5436 L2_FHDR_ERRORS_ALIGNMENT |
5437 L2_FHDR_ERRORS_TOO_SHORT |
5438 L2_FHDR_ERRORS_GIANT_FRAME)) {
5439
5440 goto loopback_test_done;
5441 }
5442
5443 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5444 goto loopback_test_done;
5445 }
5446
5447 for (i = 14; i < pkt_size; i++) {
5448 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5449 goto loopback_test_done;
5450 }
5451 }
5452
5453 ret = 0;
5454
5455loopback_test_done:
5456 bp->loopback = 0;
5457 return ret;
5458}
5459
Michael Chanbc5a0692006-01-23 16:13:22 -08005460#define BNX2_MAC_LOOPBACK_FAILED 1
5461#define BNX2_PHY_LOOPBACK_FAILED 2
5462#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5463 BNX2_PHY_LOOPBACK_FAILED)
5464
5465static int
5466bnx2_test_loopback(struct bnx2 *bp)
5467{
5468 int rc = 0;
5469
5470 if (!netif_running(bp->dev))
5471 return BNX2_LOOPBACK_FAILED;
5472
5473 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5474 spin_lock_bh(&bp->phy_lock);
Michael Chan9a120bc2008-05-16 22:17:45 -07005475 bnx2_init_phy(bp, 1);
Michael Chanbc5a0692006-01-23 16:13:22 -08005476 spin_unlock_bh(&bp->phy_lock);
5477 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5478 rc |= BNX2_MAC_LOOPBACK_FAILED;
5479 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5480 rc |= BNX2_PHY_LOOPBACK_FAILED;
5481 return rc;
5482}
5483
Michael Chanb6016b72005-05-26 13:03:09 -07005484#define NVRAM_SIZE 0x200
5485#define CRC32_RESIDUAL 0xdebb20e3
5486
5487static int
5488bnx2_test_nvram(struct bnx2 *bp)
5489{
Al Virob491edd2007-12-22 19:44:51 +00005490 __be32 buf[NVRAM_SIZE / 4];
Michael Chanb6016b72005-05-26 13:03:09 -07005491 u8 *data = (u8 *) buf;
5492 int rc = 0;
5493 u32 magic, csum;
5494
5495 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5496 goto test_nvram_done;
5497
5498 magic = be32_to_cpu(buf[0]);
5499 if (magic != 0x669955aa) {
5500 rc = -ENODEV;
5501 goto test_nvram_done;
5502 }
5503
5504 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5505 goto test_nvram_done;
5506
5507 csum = ether_crc_le(0x100, data);
5508 if (csum != CRC32_RESIDUAL) {
5509 rc = -ENODEV;
5510 goto test_nvram_done;
5511 }
5512
5513 csum = ether_crc_le(0x100, data + 0x100);
5514 if (csum != CRC32_RESIDUAL) {
5515 rc = -ENODEV;
5516 }
5517
5518test_nvram_done:
5519 return rc;
5520}
5521
5522static int
5523bnx2_test_link(struct bnx2 *bp)
5524{
5525 u32 bmsr;
5526
Michael Chan9f52b562008-10-09 12:21:46 -07005527 if (!netif_running(bp->dev))
5528 return -ENODEV;
5529
Michael Chan583c28e2008-01-21 19:51:35 -08005530 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan489310a2007-10-10 16:16:31 -07005531 if (bp->link_up)
5532 return 0;
5533 return -ENODEV;
5534 }
Michael Chanc770a652005-08-25 15:38:39 -07005535 spin_lock_bh(&bp->phy_lock);
Michael Chan27a005b2007-05-03 13:23:41 -07005536 bnx2_enable_bmsr1(bp);
5537 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5538 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5539 bnx2_disable_bmsr1(bp);
Michael Chanc770a652005-08-25 15:38:39 -07005540 spin_unlock_bh(&bp->phy_lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005541
Michael Chanb6016b72005-05-26 13:03:09 -07005542 if (bmsr & BMSR_LSTATUS) {
5543 return 0;
5544 }
5545 return -ENODEV;
5546}
5547
5548static int
5549bnx2_test_intr(struct bnx2 *bp)
5550{
5551 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07005552 u16 status_idx;
5553
5554 if (!netif_running(bp->dev))
5555 return -ENODEV;
5556
5557 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5558
5559 /* This register is not touched during run-time. */
Michael Chanbf5295b2006-03-23 01:11:56 -08005560 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -07005561 REG_RD(bp, BNX2_HC_COMMAND);
5562
5563 for (i = 0; i < 10; i++) {
5564 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5565 status_idx) {
5566
5567 break;
5568 }
5569
5570 msleep_interruptible(10);
5571 }
5572 if (i < 10)
5573 return 0;
5574
5575 return -ENODEV;
5576}
5577
Michael Chan38ea3682008-02-23 19:48:57 -08005578/* Determining link for parallel detection. */
Michael Chanb2fadea2008-01-21 17:07:06 -08005579static int
5580bnx2_5706_serdes_has_link(struct bnx2 *bp)
5581{
5582 u32 mode_ctl, an_dbg, exp;
5583
Michael Chan38ea3682008-02-23 19:48:57 -08005584 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5585 return 0;
5586
Michael Chanb2fadea2008-01-21 17:07:06 -08005587 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5588 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5589
5590 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5591 return 0;
5592
5593 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5594 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5595 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5596
Michael Chanf3014c02008-01-29 21:33:03 -08005597 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
Michael Chanb2fadea2008-01-21 17:07:06 -08005598 return 0;
5599
5600 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5601 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5602 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5603
5604 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5605 return 0;
5606
5607 return 1;
5608}
5609
Michael Chanb6016b72005-05-26 13:03:09 -07005610static void
Michael Chan48b01e22006-11-19 14:08:00 -08005611bnx2_5706_serdes_timer(struct bnx2 *bp)
5612{
Michael Chanb2fadea2008-01-21 17:07:06 -08005613 int check_link = 1;
5614
Michael Chan48b01e22006-11-19 14:08:00 -08005615 spin_lock(&bp->phy_lock);
Michael Chanb2fadea2008-01-21 17:07:06 -08005616 if (bp->serdes_an_pending) {
Michael Chan48b01e22006-11-19 14:08:00 -08005617 bp->serdes_an_pending--;
Michael Chanb2fadea2008-01-21 17:07:06 -08005618 check_link = 0;
5619 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005620 u32 bmcr;
5621
Benjamin Liac392ab2008-09-18 16:40:49 -07005622 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chan48b01e22006-11-19 14:08:00 -08005623
Michael Chanca58c3a2007-05-03 13:22:52 -07005624 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005625
5626 if (bmcr & BMCR_ANENABLE) {
Michael Chanb2fadea2008-01-21 17:07:06 -08005627 if (bnx2_5706_serdes_has_link(bp)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005628 bmcr &= ~BMCR_ANENABLE;
5629 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
Michael Chanca58c3a2007-05-03 13:22:52 -07005630 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan583c28e2008-01-21 19:51:35 -08005631 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08005632 }
5633 }
5634 }
5635 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
Michael Chan583c28e2008-01-21 19:51:35 -08005636 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005637 u32 phy2;
5638
5639 bnx2_write_phy(bp, 0x17, 0x0f01);
5640 bnx2_read_phy(bp, 0x15, &phy2);
5641 if (phy2 & 0x20) {
5642 u32 bmcr;
5643
Michael Chanca58c3a2007-05-03 13:22:52 -07005644 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005645 bmcr |= BMCR_ANENABLE;
Michael Chanca58c3a2007-05-03 13:22:52 -07005646 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005647
Michael Chan583c28e2008-01-21 19:51:35 -08005648 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08005649 }
5650 } else
Benjamin Liac392ab2008-09-18 16:40:49 -07005651 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chan48b01e22006-11-19 14:08:00 -08005652
Michael Chana2724e22008-02-23 19:47:44 -08005653 if (check_link) {
Michael Chanb2fadea2008-01-21 17:07:06 -08005654 u32 val;
5655
5656 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5657 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5658 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5659
Michael Chana2724e22008-02-23 19:47:44 -08005660 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5661 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5662 bnx2_5706s_force_link_dn(bp, 1);
5663 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5664 } else
5665 bnx2_set_link(bp);
5666 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5667 bnx2_set_link(bp);
Michael Chanb2fadea2008-01-21 17:07:06 -08005668 }
Michael Chan48b01e22006-11-19 14:08:00 -08005669 spin_unlock(&bp->phy_lock);
5670}
5671
5672static void
Michael Chanf8dd0642006-11-19 14:08:29 -08005673bnx2_5708_serdes_timer(struct bnx2 *bp)
5674{
Michael Chan583c28e2008-01-21 19:51:35 -08005675 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07005676 return;
5677
Michael Chan583c28e2008-01-21 19:51:35 -08005678 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
Michael Chanf8dd0642006-11-19 14:08:29 -08005679 bp->serdes_an_pending = 0;
5680 return;
5681 }
5682
5683 spin_lock(&bp->phy_lock);
5684 if (bp->serdes_an_pending)
5685 bp->serdes_an_pending--;
5686 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5687 u32 bmcr;
5688
Michael Chanca58c3a2007-05-03 13:22:52 -07005689 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanf8dd0642006-11-19 14:08:29 -08005690 if (bmcr & BMCR_ANENABLE) {
Michael Chan605a9e22007-05-03 13:23:13 -07005691 bnx2_enable_forced_2g5(bp);
Michael Chanf8dd0642006-11-19 14:08:29 -08005692 bp->current_interval = SERDES_FORCED_TIMEOUT;
5693 } else {
Michael Chan605a9e22007-05-03 13:23:13 -07005694 bnx2_disable_forced_2g5(bp);
Michael Chanf8dd0642006-11-19 14:08:29 -08005695 bp->serdes_an_pending = 2;
Benjamin Liac392ab2008-09-18 16:40:49 -07005696 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanf8dd0642006-11-19 14:08:29 -08005697 }
5698
5699 } else
Benjamin Liac392ab2008-09-18 16:40:49 -07005700 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanf8dd0642006-11-19 14:08:29 -08005701
5702 spin_unlock(&bp->phy_lock);
5703}
5704
5705static void
Michael Chanb6016b72005-05-26 13:03:09 -07005706bnx2_timer(unsigned long data)
5707{
5708 struct bnx2 *bp = (struct bnx2 *) data;
Michael Chanb6016b72005-05-26 13:03:09 -07005709
Michael Chancd339a02005-08-25 15:35:24 -07005710 if (!netif_running(bp->dev))
5711 return;
5712
Michael Chanb6016b72005-05-26 13:03:09 -07005713 if (atomic_read(&bp->intr_sem) != 0)
5714 goto bnx2_restart_timer;
5715
Michael Chandf149d72007-07-07 22:51:36 -07005716 bnx2_send_heart_beat(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005717
Michael Chan2726d6e2008-01-29 21:35:05 -08005718 bp->stats_blk->stat_FwRxDrop =
5719 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
Michael Chancea94db2006-06-12 22:16:13 -07005720
Michael Chan02537b062007-06-04 21:24:07 -07005721 /* workaround occasional corrupted counters */
5722 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5723 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5724 BNX2_HC_COMMAND_STATS_NOW);
5725
Michael Chan583c28e2008-01-21 19:51:35 -08005726 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanf8dd0642006-11-19 14:08:29 -08005727 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5728 bnx2_5706_serdes_timer(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07005729 else
Michael Chanf8dd0642006-11-19 14:08:29 -08005730 bnx2_5708_serdes_timer(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005731 }
5732
5733bnx2_restart_timer:
Michael Chancd339a02005-08-25 15:35:24 -07005734 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07005735}
5736
Michael Chan8e6a72c2007-05-03 13:24:48 -07005737static int
5738bnx2_request_irq(struct bnx2 *bp)
5739{
Michael Chan6d866ff2007-12-20 19:56:09 -08005740 unsigned long flags;
Michael Chanb4b36042007-12-20 19:59:30 -08005741 struct bnx2_irq *irq;
5742 int rc = 0, i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07005743
David S. Millerf86e82f2008-01-21 17:15:40 -08005744 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
Michael Chan6d866ff2007-12-20 19:56:09 -08005745 flags = 0;
5746 else
5747 flags = IRQF_SHARED;
Michael Chanb4b36042007-12-20 19:59:30 -08005748
5749 for (i = 0; i < bp->irq_nvecs; i++) {
5750 irq = &bp->irq_tbl[i];
Michael Chanc76c0472007-12-20 20:01:19 -08005751 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
Michael Chanf0ea2e62008-06-19 16:41:57 -07005752 &bp->bnx2_napi[i]);
Michael Chanb4b36042007-12-20 19:59:30 -08005753 if (rc)
5754 break;
5755 irq->requested = 1;
5756 }
Michael Chan8e6a72c2007-05-03 13:24:48 -07005757 return rc;
5758}
5759
5760static void
5761bnx2_free_irq(struct bnx2 *bp)
5762{
Michael Chanb4b36042007-12-20 19:59:30 -08005763 struct bnx2_irq *irq;
5764 int i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07005765
Michael Chanb4b36042007-12-20 19:59:30 -08005766 for (i = 0; i < bp->irq_nvecs; i++) {
5767 irq = &bp->irq_tbl[i];
5768 if (irq->requested)
Michael Chanf0ea2e62008-06-19 16:41:57 -07005769 free_irq(irq->vector, &bp->bnx2_napi[i]);
Michael Chanb4b36042007-12-20 19:59:30 -08005770 irq->requested = 0;
Michael Chan6d866ff2007-12-20 19:56:09 -08005771 }
David S. Millerf86e82f2008-01-21 17:15:40 -08005772 if (bp->flags & BNX2_FLAG_USING_MSI)
Michael Chanb4b36042007-12-20 19:59:30 -08005773 pci_disable_msi(bp->pdev);
David S. Millerf86e82f2008-01-21 17:15:40 -08005774 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanb4b36042007-12-20 19:59:30 -08005775 pci_disable_msix(bp->pdev);
5776
David S. Millerf86e82f2008-01-21 17:15:40 -08005777 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
Michael Chanb4b36042007-12-20 19:59:30 -08005778}
5779
5780static void
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005781bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
Michael Chanb4b36042007-12-20 19:59:30 -08005782{
Michael Chan57851d82007-12-20 20:01:44 -08005783 int i, rc;
5784 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5785
Michael Chanb4b36042007-12-20 19:59:30 -08005786 bnx2_setup_msix_tbl(bp);
5787 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5788 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5789 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
Michael Chan57851d82007-12-20 20:01:44 -08005790
5791 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5792 msix_ent[i].entry = i;
5793 msix_ent[i].vector = 0;
Michael Chan35e90102008-06-19 16:37:42 -07005794
5795 strcpy(bp->irq_tbl[i].name, bp->dev->name);
Michael Chanf0ea2e62008-06-19 16:41:57 -07005796 bp->irq_tbl[i].handler = bnx2_msi_1shot;
Michael Chan57851d82007-12-20 20:01:44 -08005797 }
5798
5799 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5800 if (rc != 0)
5801 return;
5802
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005803 bp->irq_nvecs = msix_vecs;
David S. Millerf86e82f2008-01-21 17:15:40 -08005804 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan57851d82007-12-20 20:01:44 -08005805 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5806 bp->irq_tbl[i].vector = msix_ent[i].vector;
Michael Chan6d866ff2007-12-20 19:56:09 -08005807}
5808
5809static void
5810bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5811{
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005812 int cpus = num_online_cpus();
Benjamin Li706bf242008-07-18 17:55:11 -07005813 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005814
Michael Chan6d866ff2007-12-20 19:56:09 -08005815 bp->irq_tbl[0].handler = bnx2_interrupt;
5816 strcpy(bp->irq_tbl[0].name, bp->dev->name);
Michael Chanb4b36042007-12-20 19:59:30 -08005817 bp->irq_nvecs = 1;
5818 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08005819
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005820 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5821 bnx2_enable_msix(bp, msix_vecs);
Michael Chanb4b36042007-12-20 19:59:30 -08005822
David S. Millerf86e82f2008-01-21 17:15:40 -08005823 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5824 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
Michael Chan6d866ff2007-12-20 19:56:09 -08005825 if (pci_enable_msi(bp->pdev) == 0) {
David S. Millerf86e82f2008-01-21 17:15:40 -08005826 bp->flags |= BNX2_FLAG_USING_MSI;
Michael Chan6d866ff2007-12-20 19:56:09 -08005827 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
David S. Millerf86e82f2008-01-21 17:15:40 -08005828 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan6d866ff2007-12-20 19:56:09 -08005829 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5830 } else
5831 bp->irq_tbl[0].handler = bnx2_msi;
Michael Chanb4b36042007-12-20 19:59:30 -08005832
5833 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08005834 }
5835 }
Benjamin Li706bf242008-07-18 17:55:11 -07005836
5837 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5838 bp->dev->real_num_tx_queues = bp->num_tx_rings;
5839
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005840 bp->num_rx_rings = bp->irq_nvecs;
Michael Chan8e6a72c2007-05-03 13:24:48 -07005841}
5842
Michael Chanb6016b72005-05-26 13:03:09 -07005843/* Called with rtnl_lock */
5844static int
5845bnx2_open(struct net_device *dev)
5846{
Michael Chan972ec0d2006-01-23 16:12:43 -08005847 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005848 int rc;
5849
Michael Chan1b2f9222007-05-03 13:20:19 -07005850 netif_carrier_off(dev);
5851
Pavel Machek829ca9a2005-09-03 15:56:56 -07005852 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07005853 bnx2_disable_int(bp);
5854
Michael Chan6d866ff2007-12-20 19:56:09 -08005855 bnx2_setup_int_mode(bp, disable_msi);
Michael Chan35efa7c2007-12-20 19:56:37 -08005856 bnx2_napi_enable(bp);
Michael Chan35e90102008-06-19 16:37:42 -07005857 rc = bnx2_alloc_mem(bp);
Michael Chan2739a8b2008-06-19 16:44:10 -07005858 if (rc)
5859 goto open_err;
Michael Chan35e90102008-06-19 16:37:42 -07005860
Michael Chan8e6a72c2007-05-03 13:24:48 -07005861 rc = bnx2_request_irq(bp);
Michael Chan2739a8b2008-06-19 16:44:10 -07005862 if (rc)
5863 goto open_err;
Michael Chanb6016b72005-05-26 13:03:09 -07005864
Michael Chan9a120bc2008-05-16 22:17:45 -07005865 rc = bnx2_init_nic(bp, 1);
Michael Chan2739a8b2008-06-19 16:44:10 -07005866 if (rc)
5867 goto open_err;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005868
Michael Chancd339a02005-08-25 15:35:24 -07005869 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07005870
5871 atomic_set(&bp->intr_sem, 0);
5872
5873 bnx2_enable_int(bp);
5874
David S. Millerf86e82f2008-01-21 17:15:40 -08005875 if (bp->flags & BNX2_FLAG_USING_MSI) {
Michael Chanb6016b72005-05-26 13:03:09 -07005876 /* Test MSI to make sure it is working
5877 * If MSI test fails, go back to INTx mode
5878 */
5879 if (bnx2_test_intr(bp) != 0) {
5880 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5881 " using MSI, switching to INTx mode. Please"
5882 " report this failure to the PCI maintainer"
5883 " and include system chipset information.\n",
5884 bp->dev->name);
5885
5886 bnx2_disable_int(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07005887 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005888
Michael Chan6d866ff2007-12-20 19:56:09 -08005889 bnx2_setup_int_mode(bp, 1);
5890
Michael Chan9a120bc2008-05-16 22:17:45 -07005891 rc = bnx2_init_nic(bp, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07005892
Michael Chan8e6a72c2007-05-03 13:24:48 -07005893 if (!rc)
5894 rc = bnx2_request_irq(bp);
5895
Michael Chanb6016b72005-05-26 13:03:09 -07005896 if (rc) {
Michael Chanb6016b72005-05-26 13:03:09 -07005897 del_timer_sync(&bp->timer);
Michael Chan2739a8b2008-06-19 16:44:10 -07005898 goto open_err;
Michael Chanb6016b72005-05-26 13:03:09 -07005899 }
5900 bnx2_enable_int(bp);
5901 }
5902 }
David S. Millerf86e82f2008-01-21 17:15:40 -08005903 if (bp->flags & BNX2_FLAG_USING_MSI)
Michael Chanb6016b72005-05-26 13:03:09 -07005904 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
David S. Millerf86e82f2008-01-21 17:15:40 -08005905 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chan57851d82007-12-20 20:01:44 -08005906 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
Michael Chanb6016b72005-05-26 13:03:09 -07005907
Benjamin Li706bf242008-07-18 17:55:11 -07005908 netif_tx_start_all_queues(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005909
5910 return 0;
Michael Chan2739a8b2008-06-19 16:44:10 -07005911
5912open_err:
5913 bnx2_napi_disable(bp);
5914 bnx2_free_skbs(bp);
5915 bnx2_free_irq(bp);
5916 bnx2_free_mem(bp);
5917 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07005918}
5919
5920static void
David Howellsc4028952006-11-22 14:57:56 +00005921bnx2_reset_task(struct work_struct *work)
Michael Chanb6016b72005-05-26 13:03:09 -07005922{
David Howellsc4028952006-11-22 14:57:56 +00005923 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
Michael Chanb6016b72005-05-26 13:03:09 -07005924
Michael Chanafdc08b2005-08-25 15:34:29 -07005925 if (!netif_running(bp->dev))
5926 return;
5927
Michael Chanb6016b72005-05-26 13:03:09 -07005928 bnx2_netif_stop(bp);
5929
Michael Chan9a120bc2008-05-16 22:17:45 -07005930 bnx2_init_nic(bp, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07005931
5932 atomic_set(&bp->intr_sem, 1);
5933 bnx2_netif_start(bp);
5934}
5935
5936static void
5937bnx2_tx_timeout(struct net_device *dev)
5938{
Michael Chan972ec0d2006-01-23 16:12:43 -08005939 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005940
5941 /* This allows the netif to be shutdown gracefully before resetting */
5942 schedule_work(&bp->reset_task);
5943}
5944
5945#ifdef BCM_VLAN
5946/* Called with rtnl_lock */
5947static void
5948bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5949{
Michael Chan972ec0d2006-01-23 16:12:43 -08005950 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005951
5952 bnx2_netif_stop(bp);
5953
5954 bp->vlgrp = vlgrp;
5955 bnx2_set_rx_mode(dev);
Michael Chan7c62e832008-07-14 22:39:03 -07005956 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5957 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07005958
5959 bnx2_netif_start(bp);
5960}
Michael Chanb6016b72005-05-26 13:03:09 -07005961#endif
5962
Herbert Xu932ff272006-06-09 12:20:56 -07005963/* Called with netif_tx_lock.
Michael Chan2f8af122006-08-15 01:39:10 -07005964 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5965 * netif_wake_queue().
Michael Chanb6016b72005-05-26 13:03:09 -07005966 */
5967static int
5968bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5969{
Michael Chan972ec0d2006-01-23 16:12:43 -08005970 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005971 dma_addr_t mapping;
5972 struct tx_bd *txbd;
5973 struct sw_bd *tx_buf;
5974 u32 len, vlan_tag_flags, last_frag, mss;
5975 u16 prod, ring_prod;
5976 int i;
Benjamin Li706bf242008-07-18 17:55:11 -07005977 struct bnx2_napi *bnapi;
5978 struct bnx2_tx_ring_info *txr;
5979 struct netdev_queue *txq;
5980
5981 /* Determine which tx ring we will be placed on */
5982 i = skb_get_queue_mapping(skb);
5983 bnapi = &bp->bnx2_napi[i];
5984 txr = &bnapi->tx_ring;
5985 txq = netdev_get_tx_queue(dev, i);
Michael Chanb6016b72005-05-26 13:03:09 -07005986
Michael Chan35e90102008-06-19 16:37:42 -07005987 if (unlikely(bnx2_tx_avail(bp, txr) <
Michael Chana550c992007-12-20 19:56:59 -08005988 (skb_shinfo(skb)->nr_frags + 1))) {
Benjamin Li706bf242008-07-18 17:55:11 -07005989 netif_tx_stop_queue(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07005990 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5991 dev->name);
5992
5993 return NETDEV_TX_BUSY;
5994 }
5995 len = skb_headlen(skb);
Michael Chan35e90102008-06-19 16:37:42 -07005996 prod = txr->tx_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07005997 ring_prod = TX_RING_IDX(prod);
5998
5999 vlan_tag_flags = 0;
Patrick McHardy84fa7932006-08-29 16:44:56 -07006000 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Michael Chanb6016b72005-05-26 13:03:09 -07006001 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6002 }
6003
Michael Chan729b85c2008-08-14 15:29:39 -07006004#ifdef BCM_VLAN
Al Viro79ea13c2008-01-24 02:06:46 -08006005 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
Michael Chanb6016b72005-05-26 13:03:09 -07006006 vlan_tag_flags |=
6007 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6008 }
Michael Chan729b85c2008-08-14 15:29:39 -07006009#endif
Michael Chanfde82052007-05-03 17:23:35 -07006010 if ((mss = skb_shinfo(skb)->gso_size)) {
Michael Chana1efb4b2008-10-09 12:24:39 -07006011 u32 tcp_opt_len;
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006012 struct iphdr *iph;
Michael Chanb6016b72005-05-26 13:03:09 -07006013
Michael Chanb6016b72005-05-26 13:03:09 -07006014 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6015
Michael Chan4666f872007-05-03 13:22:28 -07006016 tcp_opt_len = tcp_optlen(skb);
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07006017
Michael Chan4666f872007-05-03 13:22:28 -07006018 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6019 u32 tcp_off = skb_transport_offset(skb) -
6020 sizeof(struct ipv6hdr) - ETH_HLEN;
Michael Chanb6016b72005-05-26 13:03:09 -07006021
Michael Chan4666f872007-05-03 13:22:28 -07006022 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6023 TX_BD_FLAGS_SW_FLAGS;
6024 if (likely(tcp_off == 0))
6025 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6026 else {
6027 tcp_off >>= 3;
6028 vlan_tag_flags |= ((tcp_off & 0x3) <<
6029 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6030 ((tcp_off & 0x10) <<
6031 TX_BD_FLAGS_TCP6_OFF4_SHL);
6032 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6033 }
6034 } else {
Michael Chan4666f872007-05-03 13:22:28 -07006035 iph = ip_hdr(skb);
Michael Chan4666f872007-05-03 13:22:28 -07006036 if (tcp_opt_len || (iph->ihl > 5)) {
6037 vlan_tag_flags |= ((iph->ihl - 5) +
6038 (tcp_opt_len >> 2)) << 8;
6039 }
Michael Chanb6016b72005-05-26 13:03:09 -07006040 }
Michael Chan4666f872007-05-03 13:22:28 -07006041 } else
Michael Chanb6016b72005-05-26 13:03:09 -07006042 mss = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07006043
6044 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006045
Michael Chan35e90102008-06-19 16:37:42 -07006046 tx_buf = &txr->tx_buf_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006047 tx_buf->skb = skb;
6048 pci_unmap_addr_set(tx_buf, mapping, mapping);
6049
Michael Chan35e90102008-06-19 16:37:42 -07006050 txbd = &txr->tx_desc_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006051
6052 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6053 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6054 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6055 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6056
6057 last_frag = skb_shinfo(skb)->nr_frags;
6058
6059 for (i = 0; i < last_frag; i++) {
6060 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6061
6062 prod = NEXT_TX_BD(prod);
6063 ring_prod = TX_RING_IDX(prod);
Michael Chan35e90102008-06-19 16:37:42 -07006064 txbd = &txr->tx_desc_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006065
6066 len = frag->size;
6067 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6068 len, PCI_DMA_TODEVICE);
Michael Chan35e90102008-06-19 16:37:42 -07006069 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod],
Michael Chanb6016b72005-05-26 13:03:09 -07006070 mapping, mapping);
6071
6072 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6073 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6074 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6075 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6076
6077 }
6078 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6079
6080 prod = NEXT_TX_BD(prod);
Michael Chan35e90102008-06-19 16:37:42 -07006081 txr->tx_prod_bseq += skb->len;
Michael Chanb6016b72005-05-26 13:03:09 -07006082
Michael Chan35e90102008-06-19 16:37:42 -07006083 REG_WR16(bp, txr->tx_bidx_addr, prod);
6084 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07006085
6086 mmiowb();
6087
Michael Chan35e90102008-06-19 16:37:42 -07006088 txr->tx_prod = prod;
Michael Chanb6016b72005-05-26 13:03:09 -07006089 dev->trans_start = jiffies;
6090
Michael Chan35e90102008-06-19 16:37:42 -07006091 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
Benjamin Li706bf242008-07-18 17:55:11 -07006092 netif_tx_stop_queue(txq);
Michael Chan35e90102008-06-19 16:37:42 -07006093 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
Benjamin Li706bf242008-07-18 17:55:11 -07006094 netif_tx_wake_queue(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07006095 }
6096
6097 return NETDEV_TX_OK;
6098}
6099
6100/* Called with rtnl_lock */
6101static int
6102bnx2_close(struct net_device *dev)
6103{
Michael Chan972ec0d2006-01-23 16:12:43 -08006104 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006105
David S. Miller4bb073c2008-06-12 02:22:02 -07006106 cancel_work_sync(&bp->reset_task);
Michael Chanafdc08b2005-08-25 15:34:29 -07006107
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006108 bnx2_disable_int_sync(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08006109 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006110 del_timer_sync(&bp->timer);
Michael Chan74bf4ba2008-10-09 12:21:08 -07006111 bnx2_shutdown_chip(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07006112 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006113 bnx2_free_skbs(bp);
6114 bnx2_free_mem(bp);
6115 bp->link_up = 0;
6116 netif_carrier_off(bp->dev);
Pavel Machek829ca9a2005-09-03 15:56:56 -07006117 bnx2_set_power_state(bp, PCI_D3hot);
Michael Chanb6016b72005-05-26 13:03:09 -07006118 return 0;
6119}
6120
6121#define GET_NET_STATS64(ctr) \
6122 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6123 (unsigned long) (ctr##_lo)
6124
6125#define GET_NET_STATS32(ctr) \
6126 (ctr##_lo)
6127
6128#if (BITS_PER_LONG == 64)
6129#define GET_NET_STATS GET_NET_STATS64
6130#else
6131#define GET_NET_STATS GET_NET_STATS32
6132#endif
6133
6134static struct net_device_stats *
6135bnx2_get_stats(struct net_device *dev)
6136{
Michael Chan972ec0d2006-01-23 16:12:43 -08006137 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006138 struct statistics_block *stats_blk = bp->stats_blk;
6139 struct net_device_stats *net_stats = &bp->net_stats;
6140
6141 if (bp->stats_blk == NULL) {
6142 return net_stats;
6143 }
6144 net_stats->rx_packets =
6145 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6146 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6147 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6148
6149 net_stats->tx_packets =
6150 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6151 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6152 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6153
6154 net_stats->rx_bytes =
6155 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6156
6157 net_stats->tx_bytes =
6158 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6159
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006160 net_stats->multicast =
Michael Chanb6016b72005-05-26 13:03:09 -07006161 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6162
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006163 net_stats->collisions =
Michael Chanb6016b72005-05-26 13:03:09 -07006164 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6165
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006166 net_stats->rx_length_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006167 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6168 stats_blk->stat_EtherStatsOverrsizePkts);
6169
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006170 net_stats->rx_over_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006171 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6172
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006173 net_stats->rx_frame_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006174 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6175
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006176 net_stats->rx_crc_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006177 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6178
6179 net_stats->rx_errors = net_stats->rx_length_errors +
6180 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6181 net_stats->rx_crc_errors;
6182
6183 net_stats->tx_aborted_errors =
6184 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6185 stats_blk->stat_Dot3StatsLateCollisions);
6186
Michael Chan5b0c76a2005-11-04 08:45:49 -08006187 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6188 (CHIP_ID(bp) == CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07006189 net_stats->tx_carrier_errors = 0;
6190 else {
6191 net_stats->tx_carrier_errors =
6192 (unsigned long)
6193 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6194 }
6195
6196 net_stats->tx_errors =
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006197 (unsigned long)
Michael Chanb6016b72005-05-26 13:03:09 -07006198 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6199 +
6200 net_stats->tx_aborted_errors +
6201 net_stats->tx_carrier_errors;
6202
Michael Chancea94db2006-06-12 22:16:13 -07006203 net_stats->rx_missed_errors =
6204 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6205 stats_blk->stat_FwRxDrop);
6206
Michael Chanb6016b72005-05-26 13:03:09 -07006207 return net_stats;
6208}
6209
6210/* All ethtool functions called with rtnl_lock */
6211
6212static int
6213bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6214{
Michael Chan972ec0d2006-01-23 16:12:43 -08006215 struct bnx2 *bp = netdev_priv(dev);
Michael Chan7b6b8342007-07-07 22:50:15 -07006216 int support_serdes = 0, support_copper = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07006217
6218 cmd->supported = SUPPORTED_Autoneg;
Michael Chan583c28e2008-01-21 19:51:35 -08006219 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07006220 support_serdes = 1;
6221 support_copper = 1;
6222 } else if (bp->phy_port == PORT_FIBRE)
6223 support_serdes = 1;
6224 else
6225 support_copper = 1;
6226
6227 if (support_serdes) {
Michael Chanb6016b72005-05-26 13:03:09 -07006228 cmd->supported |= SUPPORTED_1000baseT_Full |
6229 SUPPORTED_FIBRE;
Michael Chan583c28e2008-01-21 19:51:35 -08006230 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan605a9e22007-05-03 13:23:13 -07006231 cmd->supported |= SUPPORTED_2500baseX_Full;
Michael Chanb6016b72005-05-26 13:03:09 -07006232
Michael Chanb6016b72005-05-26 13:03:09 -07006233 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006234 if (support_copper) {
Michael Chanb6016b72005-05-26 13:03:09 -07006235 cmd->supported |= SUPPORTED_10baseT_Half |
6236 SUPPORTED_10baseT_Full |
6237 SUPPORTED_100baseT_Half |
6238 SUPPORTED_100baseT_Full |
6239 SUPPORTED_1000baseT_Full |
6240 SUPPORTED_TP;
6241
Michael Chanb6016b72005-05-26 13:03:09 -07006242 }
6243
Michael Chan7b6b8342007-07-07 22:50:15 -07006244 spin_lock_bh(&bp->phy_lock);
6245 cmd->port = bp->phy_port;
Michael Chanb6016b72005-05-26 13:03:09 -07006246 cmd->advertising = bp->advertising;
6247
6248 if (bp->autoneg & AUTONEG_SPEED) {
6249 cmd->autoneg = AUTONEG_ENABLE;
6250 }
6251 else {
6252 cmd->autoneg = AUTONEG_DISABLE;
6253 }
6254
6255 if (netif_carrier_ok(dev)) {
6256 cmd->speed = bp->line_speed;
6257 cmd->duplex = bp->duplex;
6258 }
6259 else {
6260 cmd->speed = -1;
6261 cmd->duplex = -1;
6262 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006263 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006264
6265 cmd->transceiver = XCVR_INTERNAL;
6266 cmd->phy_address = bp->phy_addr;
6267
6268 return 0;
6269}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006270
Michael Chanb6016b72005-05-26 13:03:09 -07006271static int
6272bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6273{
Michael Chan972ec0d2006-01-23 16:12:43 -08006274 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006275 u8 autoneg = bp->autoneg;
6276 u8 req_duplex = bp->req_duplex;
6277 u16 req_line_speed = bp->req_line_speed;
6278 u32 advertising = bp->advertising;
Michael Chan7b6b8342007-07-07 22:50:15 -07006279 int err = -EINVAL;
6280
6281 spin_lock_bh(&bp->phy_lock);
6282
6283 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6284 goto err_out_unlock;
6285
Michael Chan583c28e2008-01-21 19:51:35 -08006286 if (cmd->port != bp->phy_port &&
6287 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
Michael Chan7b6b8342007-07-07 22:50:15 -07006288 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006289
Michael Chand6b14482008-07-14 22:37:21 -07006290 /* If device is down, we can store the settings only if the user
6291 * is setting the currently active port.
6292 */
6293 if (!netif_running(dev) && cmd->port != bp->phy_port)
6294 goto err_out_unlock;
6295
Michael Chanb6016b72005-05-26 13:03:09 -07006296 if (cmd->autoneg == AUTONEG_ENABLE) {
6297 autoneg |= AUTONEG_SPEED;
6298
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006299 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
Michael Chanb6016b72005-05-26 13:03:09 -07006300
6301 /* allow advertising 1 speed */
6302 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6303 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6304 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6305 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6306
Michael Chan7b6b8342007-07-07 22:50:15 -07006307 if (cmd->port == PORT_FIBRE)
6308 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006309
6310 advertising = cmd->advertising;
6311
Michael Chan27a005b2007-05-03 13:23:41 -07006312 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
Michael Chan583c28e2008-01-21 19:51:35 -08006313 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
Michael Chan7b6b8342007-07-07 22:50:15 -07006314 (cmd->port == PORT_TP))
6315 goto err_out_unlock;
6316 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
Michael Chanb6016b72005-05-26 13:03:09 -07006317 advertising = cmd->advertising;
Michael Chan7b6b8342007-07-07 22:50:15 -07006318 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6319 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006320 else {
Michael Chan7b6b8342007-07-07 22:50:15 -07006321 if (cmd->port == PORT_FIBRE)
Michael Chanb6016b72005-05-26 13:03:09 -07006322 advertising = ETHTOOL_ALL_FIBRE_SPEED;
Michael Chan7b6b8342007-07-07 22:50:15 -07006323 else
Michael Chanb6016b72005-05-26 13:03:09 -07006324 advertising = ETHTOOL_ALL_COPPER_SPEED;
Michael Chanb6016b72005-05-26 13:03:09 -07006325 }
6326 advertising |= ADVERTISED_Autoneg;
6327 }
6328 else {
Michael Chan7b6b8342007-07-07 22:50:15 -07006329 if (cmd->port == PORT_FIBRE) {
Michael Chan80be4432006-11-19 14:07:28 -08006330 if ((cmd->speed != SPEED_1000 &&
6331 cmd->speed != SPEED_2500) ||
6332 (cmd->duplex != DUPLEX_FULL))
Michael Chan7b6b8342007-07-07 22:50:15 -07006333 goto err_out_unlock;
Michael Chan80be4432006-11-19 14:07:28 -08006334
6335 if (cmd->speed == SPEED_2500 &&
Michael Chan583c28e2008-01-21 19:51:35 -08006336 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan7b6b8342007-07-07 22:50:15 -07006337 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006338 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006339 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6340 goto err_out_unlock;
6341
Michael Chanb6016b72005-05-26 13:03:09 -07006342 autoneg &= ~AUTONEG_SPEED;
6343 req_line_speed = cmd->speed;
6344 req_duplex = cmd->duplex;
6345 advertising = 0;
6346 }
6347
6348 bp->autoneg = autoneg;
6349 bp->advertising = advertising;
6350 bp->req_line_speed = req_line_speed;
6351 bp->req_duplex = req_duplex;
6352
Michael Chand6b14482008-07-14 22:37:21 -07006353 err = 0;
6354 /* If device is down, the new settings will be picked up when it is
6355 * brought up.
6356 */
6357 if (netif_running(dev))
6358 err = bnx2_setup_phy(bp, cmd->port);
Michael Chanb6016b72005-05-26 13:03:09 -07006359
Michael Chan7b6b8342007-07-07 22:50:15 -07006360err_out_unlock:
Michael Chanc770a652005-08-25 15:38:39 -07006361 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006362
Michael Chan7b6b8342007-07-07 22:50:15 -07006363 return err;
Michael Chanb6016b72005-05-26 13:03:09 -07006364}
6365
6366static void
6367bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6368{
Michael Chan972ec0d2006-01-23 16:12:43 -08006369 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006370
6371 strcpy(info->driver, DRV_MODULE_NAME);
6372 strcpy(info->version, DRV_MODULE_VERSION);
6373 strcpy(info->bus_info, pci_name(bp->pdev));
Michael Chan58fc2ea2007-07-07 22:52:02 -07006374 strcpy(info->fw_version, bp->fw_version);
Michael Chanb6016b72005-05-26 13:03:09 -07006375}
6376
Michael Chan244ac4f2006-03-20 17:48:46 -08006377#define BNX2_REGDUMP_LEN (32 * 1024)
6378
6379static int
6380bnx2_get_regs_len(struct net_device *dev)
6381{
6382 return BNX2_REGDUMP_LEN;
6383}
6384
6385static void
6386bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6387{
6388 u32 *p = _p, i, offset;
6389 u8 *orig_p = _p;
6390 struct bnx2 *bp = netdev_priv(dev);
6391 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6392 0x0800, 0x0880, 0x0c00, 0x0c10,
6393 0x0c30, 0x0d08, 0x1000, 0x101c,
6394 0x1040, 0x1048, 0x1080, 0x10a4,
6395 0x1400, 0x1490, 0x1498, 0x14f0,
6396 0x1500, 0x155c, 0x1580, 0x15dc,
6397 0x1600, 0x1658, 0x1680, 0x16d8,
6398 0x1800, 0x1820, 0x1840, 0x1854,
6399 0x1880, 0x1894, 0x1900, 0x1984,
6400 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6401 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6402 0x2000, 0x2030, 0x23c0, 0x2400,
6403 0x2800, 0x2820, 0x2830, 0x2850,
6404 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6405 0x3c00, 0x3c94, 0x4000, 0x4010,
6406 0x4080, 0x4090, 0x43c0, 0x4458,
6407 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6408 0x4fc0, 0x5010, 0x53c0, 0x5444,
6409 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6410 0x5fc0, 0x6000, 0x6400, 0x6428,
6411 0x6800, 0x6848, 0x684c, 0x6860,
6412 0x6888, 0x6910, 0x8000 };
6413
6414 regs->version = 0;
6415
6416 memset(p, 0, BNX2_REGDUMP_LEN);
6417
6418 if (!netif_running(bp->dev))
6419 return;
6420
6421 i = 0;
6422 offset = reg_boundaries[0];
6423 p += offset;
6424 while (offset < BNX2_REGDUMP_LEN) {
6425 *p++ = REG_RD(bp, offset);
6426 offset += 4;
6427 if (offset == reg_boundaries[i + 1]) {
6428 offset = reg_boundaries[i + 2];
6429 p = (u32 *) (orig_p + offset);
6430 i += 2;
6431 }
6432 }
6433}
6434
Michael Chanb6016b72005-05-26 13:03:09 -07006435static void
6436bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6437{
Michael Chan972ec0d2006-01-23 16:12:43 -08006438 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006439
David S. Millerf86e82f2008-01-21 17:15:40 -08006440 if (bp->flags & BNX2_FLAG_NO_WOL) {
Michael Chanb6016b72005-05-26 13:03:09 -07006441 wol->supported = 0;
6442 wol->wolopts = 0;
6443 }
6444 else {
6445 wol->supported = WAKE_MAGIC;
6446 if (bp->wol)
6447 wol->wolopts = WAKE_MAGIC;
6448 else
6449 wol->wolopts = 0;
6450 }
6451 memset(&wol->sopass, 0, sizeof(wol->sopass));
6452}
6453
6454static int
6455bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6456{
Michael Chan972ec0d2006-01-23 16:12:43 -08006457 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006458
6459 if (wol->wolopts & ~WAKE_MAGIC)
6460 return -EINVAL;
6461
6462 if (wol->wolopts & WAKE_MAGIC) {
David S. Millerf86e82f2008-01-21 17:15:40 -08006463 if (bp->flags & BNX2_FLAG_NO_WOL)
Michael Chanb6016b72005-05-26 13:03:09 -07006464 return -EINVAL;
6465
6466 bp->wol = 1;
6467 }
6468 else {
6469 bp->wol = 0;
6470 }
6471 return 0;
6472}
6473
6474static int
6475bnx2_nway_reset(struct net_device *dev)
6476{
Michael Chan972ec0d2006-01-23 16:12:43 -08006477 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006478 u32 bmcr;
6479
Michael Chan9f52b562008-10-09 12:21:46 -07006480 if (!netif_running(dev))
6481 return -EAGAIN;
6482
Michael Chanb6016b72005-05-26 13:03:09 -07006483 if (!(bp->autoneg & AUTONEG_SPEED)) {
6484 return -EINVAL;
6485 }
6486
Michael Chanc770a652005-08-25 15:38:39 -07006487 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006488
Michael Chan583c28e2008-01-21 19:51:35 -08006489 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07006490 int rc;
6491
6492 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6493 spin_unlock_bh(&bp->phy_lock);
6494 return rc;
6495 }
6496
Michael Chanb6016b72005-05-26 13:03:09 -07006497 /* Force a link down visible on the other side */
Michael Chan583c28e2008-01-21 19:51:35 -08006498 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanca58c3a2007-05-03 13:22:52 -07006499 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chanc770a652005-08-25 15:38:39 -07006500 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006501
6502 msleep(20);
6503
Michael Chanc770a652005-08-25 15:38:39 -07006504 spin_lock_bh(&bp->phy_lock);
Michael Chanf8dd0642006-11-19 14:08:29 -08006505
6506 bp->current_interval = SERDES_AN_TIMEOUT;
6507 bp->serdes_an_pending = 1;
6508 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07006509 }
6510
Michael Chanca58c3a2007-05-03 13:22:52 -07006511 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07006512 bmcr &= ~BMCR_LOOPBACK;
Michael Chanca58c3a2007-05-03 13:22:52 -07006513 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
Michael Chanb6016b72005-05-26 13:03:09 -07006514
Michael Chanc770a652005-08-25 15:38:39 -07006515 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006516
6517 return 0;
6518}
6519
6520static int
6521bnx2_get_eeprom_len(struct net_device *dev)
6522{
Michael Chan972ec0d2006-01-23 16:12:43 -08006523 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006524
Michael Chan1122db72006-01-23 16:11:42 -08006525 if (bp->flash_info == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07006526 return 0;
6527
Michael Chan1122db72006-01-23 16:11:42 -08006528 return (int) bp->flash_size;
Michael Chanb6016b72005-05-26 13:03:09 -07006529}
6530
6531static int
6532bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6533 u8 *eebuf)
6534{
Michael Chan972ec0d2006-01-23 16:12:43 -08006535 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006536 int rc;
6537
Michael Chan9f52b562008-10-09 12:21:46 -07006538 if (!netif_running(dev))
6539 return -EAGAIN;
6540
John W. Linville1064e942005-11-10 12:58:24 -08006541 /* parameters already validated in ethtool_get_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07006542
6543 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6544
6545 return rc;
6546}
6547
6548static int
6549bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6550 u8 *eebuf)
6551{
Michael Chan972ec0d2006-01-23 16:12:43 -08006552 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006553 int rc;
6554
Michael Chan9f52b562008-10-09 12:21:46 -07006555 if (!netif_running(dev))
6556 return -EAGAIN;
6557
John W. Linville1064e942005-11-10 12:58:24 -08006558 /* parameters already validated in ethtool_set_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07006559
6560 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6561
6562 return rc;
6563}
6564
6565static int
6566bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6567{
Michael Chan972ec0d2006-01-23 16:12:43 -08006568 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006569
6570 memset(coal, 0, sizeof(struct ethtool_coalesce));
6571
6572 coal->rx_coalesce_usecs = bp->rx_ticks;
6573 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6574 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6575 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6576
6577 coal->tx_coalesce_usecs = bp->tx_ticks;
6578 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6579 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6580 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6581
6582 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6583
6584 return 0;
6585}
6586
6587static int
6588bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6589{
Michael Chan972ec0d2006-01-23 16:12:43 -08006590 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006591
6592 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6593 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6594
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006595 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
Michael Chanb6016b72005-05-26 13:03:09 -07006596 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6597
6598 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6599 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6600
6601 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6602 if (bp->rx_quick_cons_trip_int > 0xff)
6603 bp->rx_quick_cons_trip_int = 0xff;
6604
6605 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6606 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6607
6608 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6609 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6610
6611 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6612 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6613
6614 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6615 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6616 0xff;
6617
6618 bp->stats_ticks = coal->stats_block_coalesce_usecs;
Michael Chan02537b062007-06-04 21:24:07 -07006619 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6620 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6621 bp->stats_ticks = USEC_PER_SEC;
6622 }
Michael Chan7ea69202007-07-16 18:27:10 -07006623 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6624 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6625 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07006626
6627 if (netif_running(bp->dev)) {
6628 bnx2_netif_stop(bp);
Michael Chan9a120bc2008-05-16 22:17:45 -07006629 bnx2_init_nic(bp, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07006630 bnx2_netif_start(bp);
6631 }
6632
6633 return 0;
6634}
6635
6636static void
6637bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6638{
Michael Chan972ec0d2006-01-23 16:12:43 -08006639 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006640
Michael Chan13daffa2006-03-20 17:49:20 -08006641 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07006642 ering->rx_mini_max_pending = 0;
Michael Chan47bf4242007-12-12 11:19:12 -08006643 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07006644
6645 ering->rx_pending = bp->rx_ring_size;
6646 ering->rx_mini_pending = 0;
Michael Chan47bf4242007-12-12 11:19:12 -08006647 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
Michael Chanb6016b72005-05-26 13:03:09 -07006648
6649 ering->tx_max_pending = MAX_TX_DESC_CNT;
6650 ering->tx_pending = bp->tx_ring_size;
6651}
6652
6653static int
Michael Chan5d5d0012007-12-12 11:17:43 -08006654bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
Michael Chanb6016b72005-05-26 13:03:09 -07006655{
Michael Chan13daffa2006-03-20 17:49:20 -08006656 if (netif_running(bp->dev)) {
6657 bnx2_netif_stop(bp);
6658 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6659 bnx2_free_skbs(bp);
6660 bnx2_free_mem(bp);
6661 }
6662
Michael Chan5d5d0012007-12-12 11:17:43 -08006663 bnx2_set_rx_ring_size(bp, rx);
6664 bp->tx_ring_size = tx;
Michael Chanb6016b72005-05-26 13:03:09 -07006665
6666 if (netif_running(bp->dev)) {
Michael Chan13daffa2006-03-20 17:49:20 -08006667 int rc;
6668
6669 rc = bnx2_alloc_mem(bp);
6670 if (rc)
6671 return rc;
Michael Chan9a120bc2008-05-16 22:17:45 -07006672 bnx2_init_nic(bp, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07006673 bnx2_netif_start(bp);
6674 }
Michael Chanb6016b72005-05-26 13:03:09 -07006675 return 0;
6676}
6677
Michael Chan5d5d0012007-12-12 11:17:43 -08006678static int
6679bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6680{
6681 struct bnx2 *bp = netdev_priv(dev);
6682 int rc;
6683
6684 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6685 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6686 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6687
6688 return -EINVAL;
6689 }
6690 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6691 return rc;
6692}
6693
Michael Chanb6016b72005-05-26 13:03:09 -07006694static void
6695bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6696{
Michael Chan972ec0d2006-01-23 16:12:43 -08006697 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006698
6699 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6700 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6701 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6702}
6703
6704static int
6705bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6706{
Michael Chan972ec0d2006-01-23 16:12:43 -08006707 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006708
6709 bp->req_flow_ctrl = 0;
6710 if (epause->rx_pause)
6711 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6712 if (epause->tx_pause)
6713 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6714
6715 if (epause->autoneg) {
6716 bp->autoneg |= AUTONEG_FLOW_CTRL;
6717 }
6718 else {
6719 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6720 }
6721
Michael Chan9f52b562008-10-09 12:21:46 -07006722 if (netif_running(dev)) {
6723 spin_lock_bh(&bp->phy_lock);
6724 bnx2_setup_phy(bp, bp->phy_port);
6725 spin_unlock_bh(&bp->phy_lock);
6726 }
Michael Chanb6016b72005-05-26 13:03:09 -07006727
6728 return 0;
6729}
6730
6731static u32
6732bnx2_get_rx_csum(struct net_device *dev)
6733{
Michael Chan972ec0d2006-01-23 16:12:43 -08006734 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006735
6736 return bp->rx_csum;
6737}
6738
6739static int
6740bnx2_set_rx_csum(struct net_device *dev, u32 data)
6741{
Michael Chan972ec0d2006-01-23 16:12:43 -08006742 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006743
6744 bp->rx_csum = data;
6745 return 0;
6746}
6747
Michael Chanb11d6212006-06-29 12:31:21 -07006748static int
6749bnx2_set_tso(struct net_device *dev, u32 data)
6750{
Michael Chan4666f872007-05-03 13:22:28 -07006751 struct bnx2 *bp = netdev_priv(dev);
6752
6753 if (data) {
Michael Chanb11d6212006-06-29 12:31:21 -07006754 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
Michael Chan4666f872007-05-03 13:22:28 -07006755 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6756 dev->features |= NETIF_F_TSO6;
6757 } else
6758 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6759 NETIF_F_TSO_ECN);
Michael Chanb11d6212006-06-29 12:31:21 -07006760 return 0;
6761}
6762
Michael Chancea94db2006-06-12 22:16:13 -07006763#define BNX2_NUM_STATS 46
Michael Chanb6016b72005-05-26 13:03:09 -07006764
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006765static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07006766 char string[ETH_GSTRING_LEN];
6767} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6768 { "rx_bytes" },
6769 { "rx_error_bytes" },
6770 { "tx_bytes" },
6771 { "tx_error_bytes" },
6772 { "rx_ucast_packets" },
6773 { "rx_mcast_packets" },
6774 { "rx_bcast_packets" },
6775 { "tx_ucast_packets" },
6776 { "tx_mcast_packets" },
6777 { "tx_bcast_packets" },
6778 { "tx_mac_errors" },
6779 { "tx_carrier_errors" },
6780 { "rx_crc_errors" },
6781 { "rx_align_errors" },
6782 { "tx_single_collisions" },
6783 { "tx_multi_collisions" },
6784 { "tx_deferred" },
6785 { "tx_excess_collisions" },
6786 { "tx_late_collisions" },
6787 { "tx_total_collisions" },
6788 { "rx_fragments" },
6789 { "rx_jabbers" },
6790 { "rx_undersize_packets" },
6791 { "rx_oversize_packets" },
6792 { "rx_64_byte_packets" },
6793 { "rx_65_to_127_byte_packets" },
6794 { "rx_128_to_255_byte_packets" },
6795 { "rx_256_to_511_byte_packets" },
6796 { "rx_512_to_1023_byte_packets" },
6797 { "rx_1024_to_1522_byte_packets" },
6798 { "rx_1523_to_9022_byte_packets" },
6799 { "tx_64_byte_packets" },
6800 { "tx_65_to_127_byte_packets" },
6801 { "tx_128_to_255_byte_packets" },
6802 { "tx_256_to_511_byte_packets" },
6803 { "tx_512_to_1023_byte_packets" },
6804 { "tx_1024_to_1522_byte_packets" },
6805 { "tx_1523_to_9022_byte_packets" },
6806 { "rx_xon_frames" },
6807 { "rx_xoff_frames" },
6808 { "tx_xon_frames" },
6809 { "tx_xoff_frames" },
6810 { "rx_mac_ctrl_frames" },
6811 { "rx_filtered_packets" },
6812 { "rx_discards" },
Michael Chancea94db2006-06-12 22:16:13 -07006813 { "rx_fw_discards" },
Michael Chanb6016b72005-05-26 13:03:09 -07006814};
6815
6816#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6817
Arjan van de Venf71e1302006-03-03 21:33:57 -05006818static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07006819 STATS_OFFSET32(stat_IfHCInOctets_hi),
6820 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6821 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6822 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6823 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6824 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6825 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6826 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6827 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6828 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6829 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006830 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6831 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6832 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6833 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6834 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6835 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6836 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6837 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6838 STATS_OFFSET32(stat_EtherStatsCollisions),
6839 STATS_OFFSET32(stat_EtherStatsFragments),
6840 STATS_OFFSET32(stat_EtherStatsJabbers),
6841 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6842 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6843 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6844 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6845 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6846 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6847 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6848 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6849 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6850 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6851 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6852 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6853 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6854 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6855 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6856 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6857 STATS_OFFSET32(stat_XonPauseFramesReceived),
6858 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6859 STATS_OFFSET32(stat_OutXonSent),
6860 STATS_OFFSET32(stat_OutXoffSent),
6861 STATS_OFFSET32(stat_MacControlFramesReceived),
6862 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6863 STATS_OFFSET32(stat_IfInMBUFDiscards),
Michael Chancea94db2006-06-12 22:16:13 -07006864 STATS_OFFSET32(stat_FwRxDrop),
Michael Chanb6016b72005-05-26 13:03:09 -07006865};
6866
6867/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6868 * skipped because of errata.
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006869 */
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006870static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07006871 8,0,8,8,8,8,8,8,8,8,
6872 4,0,4,4,4,4,4,4,4,4,
6873 4,4,4,4,4,4,4,4,4,4,
6874 4,4,4,4,4,4,4,4,4,4,
Michael Chancea94db2006-06-12 22:16:13 -07006875 4,4,4,4,4,4,
Michael Chanb6016b72005-05-26 13:03:09 -07006876};
6877
Michael Chan5b0c76a2005-11-04 08:45:49 -08006878static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6879 8,0,8,8,8,8,8,8,8,8,
6880 4,4,4,4,4,4,4,4,4,4,
6881 4,4,4,4,4,4,4,4,4,4,
6882 4,4,4,4,4,4,4,4,4,4,
Michael Chancea94db2006-06-12 22:16:13 -07006883 4,4,4,4,4,4,
Michael Chan5b0c76a2005-11-04 08:45:49 -08006884};
6885
Michael Chanb6016b72005-05-26 13:03:09 -07006886#define BNX2_NUM_TESTS 6
6887
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006888static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07006889 char string[ETH_GSTRING_LEN];
6890} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6891 { "register_test (offline)" },
6892 { "memory_test (offline)" },
6893 { "loopback_test (offline)" },
6894 { "nvram_test (online)" },
6895 { "interrupt_test (online)" },
6896 { "link_test (online)" },
6897};
6898
6899static int
Jeff Garzikb9f2c042007-10-03 18:07:32 -07006900bnx2_get_sset_count(struct net_device *dev, int sset)
Michael Chanb6016b72005-05-26 13:03:09 -07006901{
Jeff Garzikb9f2c042007-10-03 18:07:32 -07006902 switch (sset) {
6903 case ETH_SS_TEST:
6904 return BNX2_NUM_TESTS;
6905 case ETH_SS_STATS:
6906 return BNX2_NUM_STATS;
6907 default:
6908 return -EOPNOTSUPP;
6909 }
Michael Chanb6016b72005-05-26 13:03:09 -07006910}
6911
6912static void
6913bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6914{
Michael Chan972ec0d2006-01-23 16:12:43 -08006915 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006916
Michael Chan9f52b562008-10-09 12:21:46 -07006917 bnx2_set_power_state(bp, PCI_D0);
6918
Michael Chanb6016b72005-05-26 13:03:09 -07006919 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6920 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Michael Chan80be4432006-11-19 14:07:28 -08006921 int i;
6922
Michael Chanb6016b72005-05-26 13:03:09 -07006923 bnx2_netif_stop(bp);
6924 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6925 bnx2_free_skbs(bp);
6926
6927 if (bnx2_test_registers(bp) != 0) {
6928 buf[0] = 1;
6929 etest->flags |= ETH_TEST_FL_FAILED;
6930 }
6931 if (bnx2_test_memory(bp) != 0) {
6932 buf[1] = 1;
6933 etest->flags |= ETH_TEST_FL_FAILED;
6934 }
Michael Chanbc5a0692006-01-23 16:13:22 -08006935 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
Michael Chanb6016b72005-05-26 13:03:09 -07006936 etest->flags |= ETH_TEST_FL_FAILED;
Michael Chanb6016b72005-05-26 13:03:09 -07006937
Michael Chan9f52b562008-10-09 12:21:46 -07006938 if (!netif_running(bp->dev))
6939 bnx2_shutdown_chip(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006940 else {
Michael Chan9a120bc2008-05-16 22:17:45 -07006941 bnx2_init_nic(bp, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07006942 bnx2_netif_start(bp);
6943 }
6944
6945 /* wait for link up */
Michael Chan80be4432006-11-19 14:07:28 -08006946 for (i = 0; i < 7; i++) {
6947 if (bp->link_up)
6948 break;
6949 msleep_interruptible(1000);
6950 }
Michael Chanb6016b72005-05-26 13:03:09 -07006951 }
6952
6953 if (bnx2_test_nvram(bp) != 0) {
6954 buf[3] = 1;
6955 etest->flags |= ETH_TEST_FL_FAILED;
6956 }
6957 if (bnx2_test_intr(bp) != 0) {
6958 buf[4] = 1;
6959 etest->flags |= ETH_TEST_FL_FAILED;
6960 }
6961
6962 if (bnx2_test_link(bp) != 0) {
6963 buf[5] = 1;
6964 etest->flags |= ETH_TEST_FL_FAILED;
6965
6966 }
Michael Chan9f52b562008-10-09 12:21:46 -07006967 if (!netif_running(bp->dev))
6968 bnx2_set_power_state(bp, PCI_D3hot);
Michael Chanb6016b72005-05-26 13:03:09 -07006969}
6970
6971static void
6972bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6973{
6974 switch (stringset) {
6975 case ETH_SS_STATS:
6976 memcpy(buf, bnx2_stats_str_arr,
6977 sizeof(bnx2_stats_str_arr));
6978 break;
6979 case ETH_SS_TEST:
6980 memcpy(buf, bnx2_tests_str_arr,
6981 sizeof(bnx2_tests_str_arr));
6982 break;
6983 }
6984}
6985
Michael Chanb6016b72005-05-26 13:03:09 -07006986static void
6987bnx2_get_ethtool_stats(struct net_device *dev,
6988 struct ethtool_stats *stats, u64 *buf)
6989{
Michael Chan972ec0d2006-01-23 16:12:43 -08006990 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006991 int i;
6992 u32 *hw_stats = (u32 *) bp->stats_blk;
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006993 u8 *stats_len_arr = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07006994
6995 if (hw_stats == NULL) {
6996 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6997 return;
6998 }
6999
Michael Chan5b0c76a2005-11-04 08:45:49 -08007000 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7001 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7002 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7003 (CHIP_ID(bp) == CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07007004 stats_len_arr = bnx2_5706_stats_len_arr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007005 else
7006 stats_len_arr = bnx2_5708_stats_len_arr;
Michael Chanb6016b72005-05-26 13:03:09 -07007007
7008 for (i = 0; i < BNX2_NUM_STATS; i++) {
7009 if (stats_len_arr[i] == 0) {
7010 /* skip this counter */
7011 buf[i] = 0;
7012 continue;
7013 }
7014 if (stats_len_arr[i] == 4) {
7015 /* 4-byte counter */
7016 buf[i] = (u64)
7017 *(hw_stats + bnx2_stats_offset_arr[i]);
7018 continue;
7019 }
7020 /* 8-byte counter */
7021 buf[i] = (((u64) *(hw_stats +
7022 bnx2_stats_offset_arr[i])) << 32) +
7023 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7024 }
7025}
7026
7027static int
7028bnx2_phys_id(struct net_device *dev, u32 data)
7029{
Michael Chan972ec0d2006-01-23 16:12:43 -08007030 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007031 int i;
7032 u32 save;
7033
Michael Chan9f52b562008-10-09 12:21:46 -07007034 bnx2_set_power_state(bp, PCI_D0);
7035
Michael Chanb6016b72005-05-26 13:03:09 -07007036 if (data == 0)
7037 data = 2;
7038
7039 save = REG_RD(bp, BNX2_MISC_CFG);
7040 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7041
7042 for (i = 0; i < (data * 2); i++) {
7043 if ((i % 2) == 0) {
7044 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7045 }
7046 else {
7047 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7048 BNX2_EMAC_LED_1000MB_OVERRIDE |
7049 BNX2_EMAC_LED_100MB_OVERRIDE |
7050 BNX2_EMAC_LED_10MB_OVERRIDE |
7051 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7052 BNX2_EMAC_LED_TRAFFIC);
7053 }
7054 msleep_interruptible(500);
7055 if (signal_pending(current))
7056 break;
7057 }
7058 REG_WR(bp, BNX2_EMAC_LED, 0);
7059 REG_WR(bp, BNX2_MISC_CFG, save);
Michael Chan9f52b562008-10-09 12:21:46 -07007060
7061 if (!netif_running(dev))
7062 bnx2_set_power_state(bp, PCI_D3hot);
7063
Michael Chanb6016b72005-05-26 13:03:09 -07007064 return 0;
7065}
7066
Michael Chan4666f872007-05-03 13:22:28 -07007067static int
7068bnx2_set_tx_csum(struct net_device *dev, u32 data)
7069{
7070 struct bnx2 *bp = netdev_priv(dev);
7071
7072 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chan6460d942007-07-14 19:07:52 -07007073 return (ethtool_op_set_tx_ipv6_csum(dev, data));
Michael Chan4666f872007-05-03 13:22:28 -07007074 else
7075 return (ethtool_op_set_tx_csum(dev, data));
7076}
7077
Jeff Garzik7282d492006-09-13 14:30:00 -04007078static const struct ethtool_ops bnx2_ethtool_ops = {
Michael Chanb6016b72005-05-26 13:03:09 -07007079 .get_settings = bnx2_get_settings,
7080 .set_settings = bnx2_set_settings,
7081 .get_drvinfo = bnx2_get_drvinfo,
Michael Chan244ac4f2006-03-20 17:48:46 -08007082 .get_regs_len = bnx2_get_regs_len,
7083 .get_regs = bnx2_get_regs,
Michael Chanb6016b72005-05-26 13:03:09 -07007084 .get_wol = bnx2_get_wol,
7085 .set_wol = bnx2_set_wol,
7086 .nway_reset = bnx2_nway_reset,
7087 .get_link = ethtool_op_get_link,
7088 .get_eeprom_len = bnx2_get_eeprom_len,
7089 .get_eeprom = bnx2_get_eeprom,
7090 .set_eeprom = bnx2_set_eeprom,
7091 .get_coalesce = bnx2_get_coalesce,
7092 .set_coalesce = bnx2_set_coalesce,
7093 .get_ringparam = bnx2_get_ringparam,
7094 .set_ringparam = bnx2_set_ringparam,
7095 .get_pauseparam = bnx2_get_pauseparam,
7096 .set_pauseparam = bnx2_set_pauseparam,
7097 .get_rx_csum = bnx2_get_rx_csum,
7098 .set_rx_csum = bnx2_set_rx_csum,
Michael Chan4666f872007-05-03 13:22:28 -07007099 .set_tx_csum = bnx2_set_tx_csum,
Michael Chanb6016b72005-05-26 13:03:09 -07007100 .set_sg = ethtool_op_set_sg,
Michael Chanb11d6212006-06-29 12:31:21 -07007101 .set_tso = bnx2_set_tso,
Michael Chanb6016b72005-05-26 13:03:09 -07007102 .self_test = bnx2_self_test,
7103 .get_strings = bnx2_get_strings,
7104 .phys_id = bnx2_phys_id,
Michael Chanb6016b72005-05-26 13:03:09 -07007105 .get_ethtool_stats = bnx2_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007106 .get_sset_count = bnx2_get_sset_count,
Michael Chanb6016b72005-05-26 13:03:09 -07007107};
7108
7109/* Called with rtnl_lock */
7110static int
7111bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7112{
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007113 struct mii_ioctl_data *data = if_mii(ifr);
Michael Chan972ec0d2006-01-23 16:12:43 -08007114 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007115 int err;
7116
7117 switch(cmd) {
7118 case SIOCGMIIPHY:
7119 data->phy_id = bp->phy_addr;
7120
7121 /* fallthru */
7122 case SIOCGMIIREG: {
7123 u32 mii_regval;
7124
Michael Chan583c28e2008-01-21 19:51:35 -08007125 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07007126 return -EOPNOTSUPP;
7127
Michael Chandad3e452007-05-03 13:18:03 -07007128 if (!netif_running(dev))
7129 return -EAGAIN;
7130
Michael Chanc770a652005-08-25 15:38:39 -07007131 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007132 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
Michael Chanc770a652005-08-25 15:38:39 -07007133 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007134
7135 data->val_out = mii_regval;
7136
7137 return err;
7138 }
7139
7140 case SIOCSMIIREG:
7141 if (!capable(CAP_NET_ADMIN))
7142 return -EPERM;
7143
Michael Chan583c28e2008-01-21 19:51:35 -08007144 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07007145 return -EOPNOTSUPP;
7146
Michael Chandad3e452007-05-03 13:18:03 -07007147 if (!netif_running(dev))
7148 return -EAGAIN;
7149
Michael Chanc770a652005-08-25 15:38:39 -07007150 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007151 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
Michael Chanc770a652005-08-25 15:38:39 -07007152 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007153
7154 return err;
7155
7156 default:
7157 /* do nothing */
7158 break;
7159 }
7160 return -EOPNOTSUPP;
7161}
7162
7163/* Called with rtnl_lock */
7164static int
7165bnx2_change_mac_addr(struct net_device *dev, void *p)
7166{
7167 struct sockaddr *addr = p;
Michael Chan972ec0d2006-01-23 16:12:43 -08007168 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007169
Michael Chan73eef4c2005-08-25 15:39:15 -07007170 if (!is_valid_ether_addr(addr->sa_data))
7171 return -EINVAL;
7172
Michael Chanb6016b72005-05-26 13:03:09 -07007173 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7174 if (netif_running(dev))
Benjamin Li5fcaed02008-07-14 22:39:52 -07007175 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07007176
7177 return 0;
7178}
7179
7180/* Called with rtnl_lock */
7181static int
7182bnx2_change_mtu(struct net_device *dev, int new_mtu)
7183{
Michael Chan972ec0d2006-01-23 16:12:43 -08007184 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007185
7186 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7187 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7188 return -EINVAL;
7189
7190 dev->mtu = new_mtu;
Michael Chan5d5d0012007-12-12 11:17:43 -08007191 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
Michael Chanb6016b72005-05-26 13:03:09 -07007192}
7193
7194#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7195static void
7196poll_bnx2(struct net_device *dev)
7197{
Michael Chan972ec0d2006-01-23 16:12:43 -08007198 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007199
7200 disable_irq(bp->pdev->irq);
David Howells7d12e782006-10-05 14:55:46 +01007201 bnx2_interrupt(bp->pdev->irq, dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007202 enable_irq(bp->pdev->irq);
7203}
7204#endif
7205
Michael Chan253c8b72007-01-08 19:56:01 -08007206static void __devinit
7207bnx2_get_5709_media(struct bnx2 *bp)
7208{
7209 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7210 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7211 u32 strap;
7212
7213 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7214 return;
7215 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
Michael Chan583c28e2008-01-21 19:51:35 -08007216 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007217 return;
7218 }
7219
7220 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7221 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7222 else
7223 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7224
7225 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7226 switch (strap) {
7227 case 0x4:
7228 case 0x5:
7229 case 0x6:
Michael Chan583c28e2008-01-21 19:51:35 -08007230 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007231 return;
7232 }
7233 } else {
7234 switch (strap) {
7235 case 0x1:
7236 case 0x2:
7237 case 0x4:
Michael Chan583c28e2008-01-21 19:51:35 -08007238 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007239 return;
7240 }
7241 }
7242}
7243
Michael Chan883e5152007-05-03 13:25:11 -07007244static void __devinit
7245bnx2_get_pci_speed(struct bnx2 *bp)
7246{
7247 u32 reg;
7248
7249 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7250 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7251 u32 clkreg;
7252
David S. Millerf86e82f2008-01-21 17:15:40 -08007253 bp->flags |= BNX2_FLAG_PCIX;
Michael Chan883e5152007-05-03 13:25:11 -07007254
7255 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7256
7257 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7258 switch (clkreg) {
7259 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7260 bp->bus_speed_mhz = 133;
7261 break;
7262
7263 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7264 bp->bus_speed_mhz = 100;
7265 break;
7266
7267 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7268 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7269 bp->bus_speed_mhz = 66;
7270 break;
7271
7272 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7273 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7274 bp->bus_speed_mhz = 50;
7275 break;
7276
7277 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7278 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7279 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7280 bp->bus_speed_mhz = 33;
7281 break;
7282 }
7283 }
7284 else {
7285 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7286 bp->bus_speed_mhz = 66;
7287 else
7288 bp->bus_speed_mhz = 33;
7289 }
7290
7291 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
David S. Millerf86e82f2008-01-21 17:15:40 -08007292 bp->flags |= BNX2_FLAG_PCI_32BIT;
Michael Chan883e5152007-05-03 13:25:11 -07007293
7294}
7295
Michael Chanb6016b72005-05-26 13:03:09 -07007296static int __devinit
7297bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7298{
7299 struct bnx2 *bp;
7300 unsigned long mem_len;
Michael Chan58fc2ea2007-07-07 22:52:02 -07007301 int rc, i, j;
Michael Chanb6016b72005-05-26 13:03:09 -07007302 u32 reg;
Michael Chan40453c82007-05-03 13:19:18 -07007303 u64 dma_mask, persist_dma_mask;
Michael Chanb6016b72005-05-26 13:03:09 -07007304
Michael Chanb6016b72005-05-26 13:03:09 -07007305 SET_NETDEV_DEV(dev, &pdev->dev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007306 bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007307
7308 bp->flags = 0;
7309 bp->phy_flags = 0;
7310
7311 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7312 rc = pci_enable_device(pdev);
7313 if (rc) {
Joe Perches898eb712007-10-18 03:06:30 -07007314 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007315 goto err_out;
7316 }
7317
7318 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007319 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007320 "Cannot find PCI device base address, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007321 rc = -ENODEV;
7322 goto err_out_disable;
7323 }
7324
7325 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7326 if (rc) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007327 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007328 goto err_out_disable;
7329 }
7330
7331 pci_set_master(pdev);
Wendy Xiong6ff2da42008-05-16 22:18:21 -07007332 pci_save_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07007333
7334 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7335 if (bp->pm_cap == 0) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007336 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007337 "Cannot find power management capability, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007338 rc = -EIO;
7339 goto err_out_release;
7340 }
7341
Michael Chanb6016b72005-05-26 13:03:09 -07007342 bp->dev = dev;
7343 bp->pdev = pdev;
7344
7345 spin_lock_init(&bp->phy_lock);
Michael Chan1b8227c2007-05-03 13:24:05 -07007346 spin_lock_init(&bp->indirect_lock);
David Howellsc4028952006-11-22 14:57:56 +00007347 INIT_WORK(&bp->reset_task, bnx2_reset_task);
Michael Chanb6016b72005-05-26 13:03:09 -07007348
7349 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
Benjamin Li706bf242008-07-18 17:55:11 -07007350 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
Michael Chanb6016b72005-05-26 13:03:09 -07007351 dev->mem_end = dev->mem_start + mem_len;
7352 dev->irq = pdev->irq;
7353
7354 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7355
7356 if (!bp->regview) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007357 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007358 rc = -ENOMEM;
7359 goto err_out_release;
7360 }
7361
7362 /* Configure byte swap and enable write to the reg_window registers.
7363 * Rely on CPU to do target byte swapping on big endian systems
7364 * The chip's target access swapping will not swap all accesses
7365 */
7366 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7367 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7368 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7369
Pavel Machek829ca9a2005-09-03 15:56:56 -07007370 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07007371
7372 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7373
Michael Chan883e5152007-05-03 13:25:11 -07007374 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7375 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7376 dev_err(&pdev->dev,
7377 "Cannot find PCIE capability, aborting.\n");
7378 rc = -EIO;
7379 goto err_out_unmap;
7380 }
David S. Millerf86e82f2008-01-21 17:15:40 -08007381 bp->flags |= BNX2_FLAG_PCIE;
Michael Chan2dd201d2008-01-21 17:06:09 -08007382 if (CHIP_REV(bp) == CHIP_REV_Ax)
David S. Millerf86e82f2008-01-21 17:15:40 -08007383 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
Michael Chan883e5152007-05-03 13:25:11 -07007384 } else {
Michael Chan59b47d82006-11-19 14:10:45 -08007385 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7386 if (bp->pcix_cap == 0) {
7387 dev_err(&pdev->dev,
7388 "Cannot find PCIX capability, aborting.\n");
7389 rc = -EIO;
7390 goto err_out_unmap;
7391 }
7392 }
7393
Michael Chanb4b36042007-12-20 19:59:30 -08007394 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7395 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
David S. Millerf86e82f2008-01-21 17:15:40 -08007396 bp->flags |= BNX2_FLAG_MSIX_CAP;
Michael Chanb4b36042007-12-20 19:59:30 -08007397 }
7398
Michael Chan8e6a72c2007-05-03 13:24:48 -07007399 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7400 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
David S. Millerf86e82f2008-01-21 17:15:40 -08007401 bp->flags |= BNX2_FLAG_MSI_CAP;
Michael Chan8e6a72c2007-05-03 13:24:48 -07007402 }
7403
Michael Chan40453c82007-05-03 13:19:18 -07007404 /* 5708 cannot support DMA addresses > 40-bit. */
7405 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7406 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7407 else
7408 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7409
7410 /* Configure DMA attributes. */
7411 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7412 dev->features |= NETIF_F_HIGHDMA;
7413 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7414 if (rc) {
7415 dev_err(&pdev->dev,
7416 "pci_set_consistent_dma_mask failed, aborting.\n");
7417 goto err_out_unmap;
7418 }
7419 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7420 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7421 goto err_out_unmap;
7422 }
7423
David S. Millerf86e82f2008-01-21 17:15:40 -08007424 if (!(bp->flags & BNX2_FLAG_PCIE))
Michael Chan883e5152007-05-03 13:25:11 -07007425 bnx2_get_pci_speed(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007426
7427 /* 5706A0 may falsely detect SERR and PERR. */
7428 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7429 reg = REG_RD(bp, PCI_COMMAND);
7430 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7431 REG_WR(bp, PCI_COMMAND, reg);
7432 }
7433 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
David S. Millerf86e82f2008-01-21 17:15:40 -08007434 !(bp->flags & BNX2_FLAG_PCIX)) {
Michael Chanb6016b72005-05-26 13:03:09 -07007435
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007436 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007437 "5706 A1 can only be used in a PCIX bus, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007438 goto err_out_unmap;
7439 }
7440
7441 bnx2_init_nvram(bp);
7442
Michael Chan2726d6e2008-01-29 21:35:05 -08007443 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
Michael Chane3648b32005-11-04 08:51:21 -08007444
7445 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
Michael Chan24cb2302007-01-25 15:49:56 -08007446 BNX2_SHM_HDR_SIGNATURE_SIG) {
7447 u32 off = PCI_FUNC(pdev->devfn) << 2;
7448
Michael Chan2726d6e2008-01-29 21:35:05 -08007449 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
Michael Chan24cb2302007-01-25 15:49:56 -08007450 } else
Michael Chane3648b32005-11-04 08:51:21 -08007451 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7452
Michael Chanb6016b72005-05-26 13:03:09 -07007453 /* Get the permanent MAC address. First we need to make sure the
7454 * firmware is actually running.
7455 */
Michael Chan2726d6e2008-01-29 21:35:05 -08007456 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
Michael Chanb6016b72005-05-26 13:03:09 -07007457
7458 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7459 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007460 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007461 rc = -ENODEV;
7462 goto err_out_unmap;
7463 }
7464
Michael Chan2726d6e2008-01-29 21:35:05 -08007465 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007466 for (i = 0, j = 0; i < 3; i++) {
7467 u8 num, k, skip0;
7468
7469 num = (u8) (reg >> (24 - (i * 8)));
7470 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7471 if (num >= k || !skip0 || k == 1) {
7472 bp->fw_version[j++] = (num / k) + '0';
7473 skip0 = 0;
7474 }
7475 }
7476 if (i != 2)
7477 bp->fw_version[j++] = '.';
7478 }
Michael Chan2726d6e2008-01-29 21:35:05 -08007479 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
Michael Chan846f5c62007-10-10 16:16:51 -07007480 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7481 bp->wol = 1;
7482
7483 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007484 bp->flags |= BNX2_FLAG_ASF_ENABLE;
Michael Chanc2d3db82007-07-16 18:26:43 -07007485
7486 for (i = 0; i < 30; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007487 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chanc2d3db82007-07-16 18:26:43 -07007488 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7489 break;
7490 msleep(10);
7491 }
7492 }
Michael Chan2726d6e2008-01-29 21:35:05 -08007493 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007494 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7495 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7496 reg != BNX2_CONDITION_MFW_RUN_NONE) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007497 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007498
7499 bp->fw_version[j++] = ' ';
7500 for (i = 0; i < 3; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007501 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007502 reg = swab32(reg);
7503 memcpy(&bp->fw_version[j], &reg, 4);
7504 j += 4;
7505 }
7506 }
Michael Chanb6016b72005-05-26 13:03:09 -07007507
Michael Chan2726d6e2008-01-29 21:35:05 -08007508 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
Michael Chanb6016b72005-05-26 13:03:09 -07007509 bp->mac_addr[0] = (u8) (reg >> 8);
7510 bp->mac_addr[1] = (u8) reg;
7511
Michael Chan2726d6e2008-01-29 21:35:05 -08007512 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
Michael Chanb6016b72005-05-26 13:03:09 -07007513 bp->mac_addr[2] = (u8) (reg >> 24);
7514 bp->mac_addr[3] = (u8) (reg >> 16);
7515 bp->mac_addr[4] = (u8) (reg >> 8);
7516 bp->mac_addr[5] = (u8) reg;
7517
7518 bp->tx_ring_size = MAX_TX_DESC_CNT;
Michael Chan932f3772006-08-15 01:39:36 -07007519 bnx2_set_rx_ring_size(bp, 255);
Michael Chanb6016b72005-05-26 13:03:09 -07007520
7521 bp->rx_csum = 1;
7522
Michael Chanb6016b72005-05-26 13:03:09 -07007523 bp->tx_quick_cons_trip_int = 20;
7524 bp->tx_quick_cons_trip = 20;
7525 bp->tx_ticks_int = 80;
7526 bp->tx_ticks = 80;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007527
Michael Chanb6016b72005-05-26 13:03:09 -07007528 bp->rx_quick_cons_trip_int = 6;
7529 bp->rx_quick_cons_trip = 6;
7530 bp->rx_ticks_int = 18;
7531 bp->rx_ticks = 18;
7532
Michael Chan7ea69202007-07-16 18:27:10 -07007533 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07007534
Benjamin Liac392ab2008-09-18 16:40:49 -07007535 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanb6016b72005-05-26 13:03:09 -07007536
Michael Chan5b0c76a2005-11-04 08:45:49 -08007537 bp->phy_addr = 1;
7538
Michael Chanb6016b72005-05-26 13:03:09 -07007539 /* Disable WOL support if we are running on a SERDES chip. */
Michael Chan253c8b72007-01-08 19:56:01 -08007540 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7541 bnx2_get_5709_media(bp);
7542 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
Michael Chan583c28e2008-01-21 19:51:35 -08007543 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chanbac0dff2006-11-19 14:15:05 -08007544
Michael Chan0d8a6572007-07-07 22:49:43 -07007545 bp->phy_port = PORT_TP;
Michael Chan583c28e2008-01-21 19:51:35 -08007546 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan0d8a6572007-07-07 22:49:43 -07007547 bp->phy_port = PORT_FIBRE;
Michael Chan2726d6e2008-01-29 21:35:05 -08007548 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan846f5c62007-10-10 16:16:51 -07007549 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007550 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07007551 bp->wol = 0;
7552 }
Michael Chan38ea3682008-02-23 19:48:57 -08007553 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7554 /* Don't do parallel detect on this board because of
7555 * some board problems. The link will not go down
7556 * if we do parallel detect.
7557 */
7558 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7559 pdev->subsystem_device == 0x310c)
7560 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7561 } else {
Michael Chan5b0c76a2005-11-04 08:45:49 -08007562 bp->phy_addr = 2;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007563 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
Michael Chan583c28e2008-01-21 19:51:35 -08007564 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007565 }
Michael Chan261dd5c2007-01-08 19:55:46 -08007566 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7567 CHIP_NUM(bp) == CHIP_NUM_5708)
Michael Chan583c28e2008-01-21 19:51:35 -08007568 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
Michael Chanfb0c18b2007-12-10 17:18:23 -08007569 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7570 (CHIP_REV(bp) == CHIP_REV_Ax ||
7571 CHIP_REV(bp) == CHIP_REV_Bx))
Michael Chan583c28e2008-01-21 19:51:35 -08007572 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
Michael Chanb6016b72005-05-26 13:03:09 -07007573
Michael Chan7c62e832008-07-14 22:39:03 -07007574 bnx2_init_fw_cap(bp);
7575
Michael Chan16088272006-06-12 22:16:43 -07007576 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7577 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
Michael Chan846f5c62007-10-10 16:16:51 -07007578 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007579 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07007580 bp->wol = 0;
7581 }
Michael Chandda1e392006-01-23 16:08:14 -08007582
Michael Chanb6016b72005-05-26 13:03:09 -07007583 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7584 bp->tx_quick_cons_trip_int =
7585 bp->tx_quick_cons_trip;
7586 bp->tx_ticks_int = bp->tx_ticks;
7587 bp->rx_quick_cons_trip_int =
7588 bp->rx_quick_cons_trip;
7589 bp->rx_ticks_int = bp->rx_ticks;
7590 bp->comp_prod_trip_int = bp->comp_prod_trip;
7591 bp->com_ticks_int = bp->com_ticks;
7592 bp->cmd_ticks_int = bp->cmd_ticks;
7593 }
7594
Michael Chanf9317a42006-09-29 17:06:23 -07007595 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7596 *
7597 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7598 * with byte enables disabled on the unused 32-bit word. This is legal
7599 * but causes problems on the AMD 8132 which will eventually stop
7600 * responding after a while.
7601 *
7602 * AMD believes this incompatibility is unique to the 5706, and
Michael Ellerman88187df2007-01-25 19:34:07 +11007603 * prefers to locally disable MSI rather than globally disabling it.
Michael Chanf9317a42006-09-29 17:06:23 -07007604 */
7605 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7606 struct pci_dev *amd_8132 = NULL;
7607
7608 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7609 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7610 amd_8132))) {
Michael Chanf9317a42006-09-29 17:06:23 -07007611
Auke Kok44c10132007-06-08 15:46:36 -07007612 if (amd_8132->revision >= 0x10 &&
7613 amd_8132->revision <= 0x13) {
Michael Chanf9317a42006-09-29 17:06:23 -07007614 disable_msi = 1;
7615 pci_dev_put(amd_8132);
7616 break;
7617 }
7618 }
7619 }
7620
Michael Chandeaf3912007-07-07 22:48:00 -07007621 bnx2_set_default_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007622 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7623
Michael Chancd339a02005-08-25 15:35:24 -07007624 init_timer(&bp->timer);
Benjamin Liac392ab2008-09-18 16:40:49 -07007625 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
Michael Chancd339a02005-08-25 15:35:24 -07007626 bp->timer.data = (unsigned long) bp;
7627 bp->timer.function = bnx2_timer;
7628
Michael Chanb6016b72005-05-26 13:03:09 -07007629 return 0;
7630
7631err_out_unmap:
7632 if (bp->regview) {
7633 iounmap(bp->regview);
Michael Chan73eef4c2005-08-25 15:39:15 -07007634 bp->regview = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07007635 }
7636
7637err_out_release:
7638 pci_release_regions(pdev);
7639
7640err_out_disable:
7641 pci_disable_device(pdev);
7642 pci_set_drvdata(pdev, NULL);
7643
7644err_out:
7645 return rc;
7646}
7647
Michael Chan883e5152007-05-03 13:25:11 -07007648static char * __devinit
7649bnx2_bus_string(struct bnx2 *bp, char *str)
7650{
7651 char *s = str;
7652
David S. Millerf86e82f2008-01-21 17:15:40 -08007653 if (bp->flags & BNX2_FLAG_PCIE) {
Michael Chan883e5152007-05-03 13:25:11 -07007654 s += sprintf(s, "PCI Express");
7655 } else {
7656 s += sprintf(s, "PCI");
David S. Millerf86e82f2008-01-21 17:15:40 -08007657 if (bp->flags & BNX2_FLAG_PCIX)
Michael Chan883e5152007-05-03 13:25:11 -07007658 s += sprintf(s, "-X");
David S. Millerf86e82f2008-01-21 17:15:40 -08007659 if (bp->flags & BNX2_FLAG_PCI_32BIT)
Michael Chan883e5152007-05-03 13:25:11 -07007660 s += sprintf(s, " 32-bit");
7661 else
7662 s += sprintf(s, " 64-bit");
7663 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7664 }
7665 return str;
7666}
7667
Michael Chan2ba582b2007-12-21 15:04:49 -08007668static void __devinit
Michael Chan35efa7c2007-12-20 19:56:37 -08007669bnx2_init_napi(struct bnx2 *bp)
7670{
Michael Chanb4b36042007-12-20 19:59:30 -08007671 int i;
Michael Chan35efa7c2007-12-20 19:56:37 -08007672
Michael Chanb4b36042007-12-20 19:59:30 -08007673 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
Michael Chan35e90102008-06-19 16:37:42 -07007674 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7675 int (*poll)(struct napi_struct *, int);
7676
7677 if (i == 0)
7678 poll = bnx2_poll;
7679 else
Michael Chanf0ea2e62008-06-19 16:41:57 -07007680 poll = bnx2_poll_msix;
Michael Chan35e90102008-06-19 16:37:42 -07007681
7682 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
Michael Chanb4b36042007-12-20 19:59:30 -08007683 bnapi->bp = bp;
7684 }
Michael Chan35efa7c2007-12-20 19:56:37 -08007685}
7686
7687static int __devinit
Michael Chanb6016b72005-05-26 13:03:09 -07007688bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7689{
7690 static int version_printed = 0;
7691 struct net_device *dev = NULL;
7692 struct bnx2 *bp;
Joe Perches0795af52007-10-03 17:59:30 -07007693 int rc;
Michael Chan883e5152007-05-03 13:25:11 -07007694 char str[40];
Joe Perches0795af52007-10-03 17:59:30 -07007695 DECLARE_MAC_BUF(mac);
Michael Chanb6016b72005-05-26 13:03:09 -07007696
7697 if (version_printed++ == 0)
7698 printk(KERN_INFO "%s", version);
7699
7700 /* dev zeroed in init_etherdev */
Benjamin Li706bf242008-07-18 17:55:11 -07007701 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
Michael Chanb6016b72005-05-26 13:03:09 -07007702
7703 if (!dev)
7704 return -ENOMEM;
7705
7706 rc = bnx2_init_board(pdev, dev);
7707 if (rc < 0) {
7708 free_netdev(dev);
7709 return rc;
7710 }
7711
7712 dev->open = bnx2_open;
7713 dev->hard_start_xmit = bnx2_start_xmit;
7714 dev->stop = bnx2_close;
7715 dev->get_stats = bnx2_get_stats;
Benjamin Li5fcaed02008-07-14 22:39:52 -07007716 dev->set_rx_mode = bnx2_set_rx_mode;
Michael Chanb6016b72005-05-26 13:03:09 -07007717 dev->do_ioctl = bnx2_ioctl;
7718 dev->set_mac_address = bnx2_change_mac_addr;
7719 dev->change_mtu = bnx2_change_mtu;
7720 dev->tx_timeout = bnx2_tx_timeout;
7721 dev->watchdog_timeo = TX_TIMEOUT;
7722#ifdef BCM_VLAN
7723 dev->vlan_rx_register = bnx2_vlan_rx_register;
Michael Chanb6016b72005-05-26 13:03:09 -07007724#endif
Michael Chanb6016b72005-05-26 13:03:09 -07007725 dev->ethtool_ops = &bnx2_ethtool_ops;
Michael Chanb6016b72005-05-26 13:03:09 -07007726
Michael Chan972ec0d2006-01-23 16:12:43 -08007727 bp = netdev_priv(dev);
Michael Chan35efa7c2007-12-20 19:56:37 -08007728 bnx2_init_napi(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007729
7730#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7731 dev->poll_controller = poll_bnx2;
7732#endif
7733
Michael Chan1b2f9222007-05-03 13:20:19 -07007734 pci_set_drvdata(pdev, dev);
7735
7736 memcpy(dev->dev_addr, bp->mac_addr, 6);
7737 memcpy(dev->perm_addr, bp->mac_addr, 6);
Michael Chan1b2f9222007-05-03 13:20:19 -07007738
Stephen Hemmingerd212f872007-06-27 00:47:37 -07007739 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Michael Chan4666f872007-05-03 13:22:28 -07007740 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Stephen Hemmingerd212f872007-06-27 00:47:37 -07007741 dev->features |= NETIF_F_IPV6_CSUM;
7742
Michael Chan1b2f9222007-05-03 13:20:19 -07007743#ifdef BCM_VLAN
7744 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7745#endif
7746 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
Michael Chan4666f872007-05-03 13:22:28 -07007747 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7748 dev->features |= NETIF_F_TSO6;
Michael Chan1b2f9222007-05-03 13:20:19 -07007749
Michael Chanb6016b72005-05-26 13:03:09 -07007750 if ((rc = register_netdev(dev))) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007751 dev_err(&pdev->dev, "Cannot register net device\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007752 if (bp->regview)
7753 iounmap(bp->regview);
7754 pci_release_regions(pdev);
7755 pci_disable_device(pdev);
7756 pci_set_drvdata(pdev, NULL);
7757 free_netdev(dev);
7758 return rc;
7759 }
7760
Michael Chan883e5152007-05-03 13:25:11 -07007761 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
Joe Perches0795af52007-10-03 17:59:30 -07007762 "IRQ %d, node addr %s\n",
Michael Chanb6016b72005-05-26 13:03:09 -07007763 dev->name,
Benjamin Lifbbf68b2008-09-18 16:40:03 -07007764 board_info[ent->driver_data].name,
Michael Chanb6016b72005-05-26 13:03:09 -07007765 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7766 ((CHIP_ID(bp) & 0x0ff0) >> 4),
Michael Chan883e5152007-05-03 13:25:11 -07007767 bnx2_bus_string(bp, str),
Michael Chanb6016b72005-05-26 13:03:09 -07007768 dev->base_addr,
Joe Perches0795af52007-10-03 17:59:30 -07007769 bp->pdev->irq, print_mac(mac, dev->dev_addr));
Michael Chanb6016b72005-05-26 13:03:09 -07007770
Michael Chanb6016b72005-05-26 13:03:09 -07007771 return 0;
7772}
7773
7774static void __devexit
7775bnx2_remove_one(struct pci_dev *pdev)
7776{
7777 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007778 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007779
Michael Chanafdc08b2005-08-25 15:34:29 -07007780 flush_scheduled_work();
7781
Michael Chanb6016b72005-05-26 13:03:09 -07007782 unregister_netdev(dev);
7783
7784 if (bp->regview)
7785 iounmap(bp->regview);
7786
7787 free_netdev(dev);
7788 pci_release_regions(pdev);
7789 pci_disable_device(pdev);
7790 pci_set_drvdata(pdev, NULL);
7791}
7792
7793static int
Pavel Machek829ca9a2005-09-03 15:56:56 -07007794bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
Michael Chanb6016b72005-05-26 13:03:09 -07007795{
7796 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007797 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007798
Michael Chan6caebb02007-08-03 20:57:25 -07007799 /* PCI register 4 needs to be saved whether netif_running() or not.
7800 * MSI address and data need to be saved if using MSI and
7801 * netif_running().
7802 */
7803 pci_save_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07007804 if (!netif_running(dev))
7805 return 0;
7806
Michael Chan1d602902006-03-20 17:50:08 -08007807 flush_scheduled_work();
Michael Chanb6016b72005-05-26 13:03:09 -07007808 bnx2_netif_stop(bp);
7809 netif_device_detach(dev);
7810 del_timer_sync(&bp->timer);
Michael Chan74bf4ba2008-10-09 12:21:08 -07007811 bnx2_shutdown_chip(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007812 bnx2_free_skbs(bp);
Pavel Machek829ca9a2005-09-03 15:56:56 -07007813 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
Michael Chanb6016b72005-05-26 13:03:09 -07007814 return 0;
7815}
7816
7817static int
7818bnx2_resume(struct pci_dev *pdev)
7819{
7820 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007821 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007822
Michael Chan6caebb02007-08-03 20:57:25 -07007823 pci_restore_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07007824 if (!netif_running(dev))
7825 return 0;
7826
Pavel Machek829ca9a2005-09-03 15:56:56 -07007827 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07007828 netif_device_attach(dev);
Michael Chan9a120bc2008-05-16 22:17:45 -07007829 bnx2_init_nic(bp, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07007830 bnx2_netif_start(bp);
7831 return 0;
7832}
7833
Wendy Xiong6ff2da42008-05-16 22:18:21 -07007834/**
7835 * bnx2_io_error_detected - called when PCI error is detected
7836 * @pdev: Pointer to PCI device
7837 * @state: The current pci connection state
7838 *
7839 * This function is called after a PCI bus error affecting
7840 * this device has been detected.
7841 */
7842static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7843 pci_channel_state_t state)
7844{
7845 struct net_device *dev = pci_get_drvdata(pdev);
7846 struct bnx2 *bp = netdev_priv(dev);
7847
7848 rtnl_lock();
7849 netif_device_detach(dev);
7850
7851 if (netif_running(dev)) {
7852 bnx2_netif_stop(bp);
7853 del_timer_sync(&bp->timer);
7854 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7855 }
7856
7857 pci_disable_device(pdev);
7858 rtnl_unlock();
7859
7860 /* Request a slot slot reset. */
7861 return PCI_ERS_RESULT_NEED_RESET;
7862}
7863
7864/**
7865 * bnx2_io_slot_reset - called after the pci bus has been reset.
7866 * @pdev: Pointer to PCI device
7867 *
7868 * Restart the card from scratch, as if from a cold-boot.
7869 */
7870static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7871{
7872 struct net_device *dev = pci_get_drvdata(pdev);
7873 struct bnx2 *bp = netdev_priv(dev);
7874
7875 rtnl_lock();
7876 if (pci_enable_device(pdev)) {
7877 dev_err(&pdev->dev,
7878 "Cannot re-enable PCI device after reset.\n");
7879 rtnl_unlock();
7880 return PCI_ERS_RESULT_DISCONNECT;
7881 }
7882 pci_set_master(pdev);
7883 pci_restore_state(pdev);
7884
7885 if (netif_running(dev)) {
7886 bnx2_set_power_state(bp, PCI_D0);
7887 bnx2_init_nic(bp, 1);
7888 }
7889
7890 rtnl_unlock();
7891 return PCI_ERS_RESULT_RECOVERED;
7892}
7893
7894/**
7895 * bnx2_io_resume - called when traffic can start flowing again.
7896 * @pdev: Pointer to PCI device
7897 *
7898 * This callback is called when the error recovery driver tells us that
7899 * its OK to resume normal operation.
7900 */
7901static void bnx2_io_resume(struct pci_dev *pdev)
7902{
7903 struct net_device *dev = pci_get_drvdata(pdev);
7904 struct bnx2 *bp = netdev_priv(dev);
7905
7906 rtnl_lock();
7907 if (netif_running(dev))
7908 bnx2_netif_start(bp);
7909
7910 netif_device_attach(dev);
7911 rtnl_unlock();
7912}
7913
7914static struct pci_error_handlers bnx2_err_handler = {
7915 .error_detected = bnx2_io_error_detected,
7916 .slot_reset = bnx2_io_slot_reset,
7917 .resume = bnx2_io_resume,
7918};
7919
Michael Chanb6016b72005-05-26 13:03:09 -07007920static struct pci_driver bnx2_pci_driver = {
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007921 .name = DRV_MODULE_NAME,
7922 .id_table = bnx2_pci_tbl,
7923 .probe = bnx2_init_one,
7924 .remove = __devexit_p(bnx2_remove_one),
7925 .suspend = bnx2_suspend,
7926 .resume = bnx2_resume,
Wendy Xiong6ff2da42008-05-16 22:18:21 -07007927 .err_handler = &bnx2_err_handler,
Michael Chanb6016b72005-05-26 13:03:09 -07007928};
7929
7930static int __init bnx2_init(void)
7931{
Jeff Garzik29917622006-08-19 17:48:59 -04007932 return pci_register_driver(&bnx2_pci_driver);
Michael Chanb6016b72005-05-26 13:03:09 -07007933}
7934
7935static void __exit bnx2_cleanup(void)
7936{
7937 pci_unregister_driver(&bnx2_pci_driver);
7938}
7939
7940module_init(bnx2_init);
7941module_exit(bnx2_cleanup);
7942
7943
7944