blob: 415c5406b17cae2f1fd8602031e13e5e7075db21 [file] [log] [blame]
Ben Dooks4b31d8b2008-10-21 14:07:00 +01001/* linux/arch/arm/plat-s3c64xx/clock.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX Base clock support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
Ben Dooks62acb2f2010-01-26 14:53:19 +090019#include <linux/clk.h>
20#include <linux/err.h>
Ben Dooks4b31d8b2008-10-21 14:07:00 +010021#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25
Ben Dooks3501c9a2010-01-26 10:45:40 +090026#include <mach/regs-sys.h>
27#include <mach/regs-clock.h>
Ben Dooksf7be9ab2010-01-26 13:41:30 +090028
Ben Dooks4b31d8b2008-10-21 14:07:00 +010029#include <plat/cpu.h>
30#include <plat/devs.h>
Ben Dooks62acb2f2010-01-26 14:53:19 +090031#include <plat/cpu-freq.h>
Ben Dooks4b31d8b2008-10-21 14:07:00 +010032#include <plat/clock.h>
Ben Dooks62acb2f2010-01-26 14:53:19 +090033#include <plat/clock-clksrc.h>
Kukjin Kim52e329e2011-10-04 19:41:43 +090034#include <plat/pll.h>
Ben Dooks62acb2f2010-01-26 14:53:19 +090035
36/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37 * ext_xtal_mux for want of an actual name from the manual.
38*/
39
40static struct clk clk_ext_xtal_mux = {
41 .name = "ext_xtal",
Ben Dooks62acb2f2010-01-26 14:53:19 +090042};
43
44#define clk_fin_apll clk_ext_xtal_mux
45#define clk_fin_mpll clk_ext_xtal_mux
46#define clk_fin_epll clk_ext_xtal_mux
47
48#define clk_fout_mpll clk_mpll
49#define clk_fout_epll clk_epll
Ben Dooks4b31d8b2008-10-21 14:07:00 +010050
Werner Almesbergera03f7da2009-03-05 11:43:13 +080051struct clk clk_h2 = {
52 .name = "hclk2",
Werner Almesbergera03f7da2009-03-05 11:43:13 +080053 .rate = 0,
54};
55
Ben Dooks4b31d8b2008-10-21 14:07:00 +010056struct clk clk_27m = {
57 .name = "clk_27m",
Ben Dooks4b31d8b2008-10-21 14:07:00 +010058 .rate = 27000000,
59};
60
Ben Dooks3627379f2008-10-31 16:14:36 +000061static int clk_48m_ctrl(struct clk *clk, int enable)
62{
63 unsigned long flags;
64 u32 val;
65
66 /* can't rely on clock lock, this register has other usages */
67 local_irq_save(flags);
68
69 val = __raw_readl(S3C64XX_OTHERS);
70 if (enable)
71 val |= S3C64XX_OTHERS_USBMASK;
72 else
73 val &= ~S3C64XX_OTHERS_USBMASK;
74
75 __raw_writel(val, S3C64XX_OTHERS);
76 local_irq_restore(flags);
77
78 return 0;
79}
80
Ben Dooks4b31d8b2008-10-21 14:07:00 +010081struct clk clk_48m = {
82 .name = "clk_48m",
Ben Dooks4b31d8b2008-10-21 14:07:00 +010083 .rate = 48000000,
Ben Dooks3627379f2008-10-31 16:14:36 +000084 .enable = clk_48m_ctrl,
Ben Dooks4b31d8b2008-10-21 14:07:00 +010085};
86
Maurus Cuelenaere05e021f2010-05-17 20:17:42 +020087struct clk clk_xusbxti = {
88 .name = "xusbxti",
Maurus Cuelenaere05e021f2010-05-17 20:17:42 +020089 .rate = 48000000,
90};
91
Ben Dooks4b31d8b2008-10-21 14:07:00 +010092static int inline s3c64xx_gate(void __iomem *reg,
93 struct clk *clk,
94 int enable)
95{
96 unsigned int ctrlbit = clk->ctrlbit;
97 u32 con;
98
99 con = __raw_readl(reg);
100
101 if (enable)
102 con |= ctrlbit;
103 else
104 con &= ~ctrlbit;
105
106 __raw_writel(con, reg);
107 return 0;
108}
109
110static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
111{
112 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
113}
114
115static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
116{
117 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
118}
119
Ben Dookscf18acf2008-10-21 14:07:02 +0100120int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100121{
122 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
123}
124
Kukjin Kimcdb216d2011-01-04 18:27:18 +0900125static struct clk init_clocks_off[] = {
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100126 {
127 .name = "nand",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100128 .parent = &clk_h,
129 }, {
Atul Dahiya32fc7fb2010-07-15 11:56:15 +0530130 .name = "rtc",
Atul Dahiya32fc7fb2010-07-15 11:56:15 +0530131 .parent = &clk_p,
132 .enable = s3c64xx_pclk_ctrl,
133 .ctrlbit = S3C_CLKCON_PCLK_RTC,
134 }, {
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100135 .name = "adc",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100136 .parent = &clk_p,
137 .enable = s3c64xx_pclk_ctrl,
138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
139 }, {
140 .name = "i2c",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100141 .parent = &clk_p,
142 .enable = s3c64xx_pclk_ctrl,
143 .ctrlbit = S3C_CLKCON_PCLK_IIC,
144 }, {
Ben Dooks400b11a2011-03-04 07:55:44 +0900145 .name = "i2c",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900146 .devname = "s3c2440-i2c.1",
Ben Dooks400b11a2011-03-04 07:55:44 +0900147 .parent = &clk_p,
148 .enable = s3c64xx_pclk_ctrl,
149 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
150 }, {
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100151 .name = "iis",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900152 .devname = "samsung-i2s.0",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100153 .parent = &clk_p,
154 .enable = s3c64xx_pclk_ctrl,
155 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
156 }, {
157 .name = "iis",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900158 .devname = "samsung-i2s.1",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100159 .parent = &clk_p,
160 .enable = s3c64xx_pclk_ctrl,
161 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
162 }, {
Jassi Brar2e5070b2010-02-17 19:03:19 +0000163#ifdef CONFIG_CPU_S3C6410
164 .name = "iis",
Jassi Brar2e5070b2010-02-17 19:03:19 +0000165 .parent = &clk_p,
166 .enable = s3c64xx_pclk_ctrl,
167 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
168 }, {
169#endif
Naveen Krishna Ch290d0982010-06-22 07:39:18 +0900170 .name = "keypad",
Naveen Krishna Ch290d0982010-06-22 07:39:18 +0900171 .parent = &clk_p,
172 .enable = s3c64xx_pclk_ctrl,
173 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
174 }, {
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100175 .name = "spi",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900176 .devname = "s3c64xx-spi.0",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100177 .parent = &clk_p,
178 .enable = s3c64xx_pclk_ctrl,
179 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
180 }, {
181 .name = "spi",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900182 .devname = "s3c64xx-spi.1",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100183 .parent = &clk_p,
184 .enable = s3c64xx_pclk_ctrl,
185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
186 }, {
Jassi Brar87315a82010-01-18 16:15:08 +0900187 .name = "spi_48m",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900188 .devname = "s3c64xx-spi.0",
Jassi Brar87315a82010-01-18 16:15:08 +0900189 .parent = &clk_48m,
190 .enable = s3c64xx_sclk_ctrl,
191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
192 }, {
193 .name = "spi_48m",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900194 .devname = "s3c64xx-spi.1",
Jassi Brar87315a82010-01-18 16:15:08 +0900195 .parent = &clk_48m,
196 .enable = s3c64xx_sclk_ctrl,
197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
198 }, {
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100199 .name = "48m",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900200 .devname = "s3c-sdhci.0",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100201 .parent = &clk_48m,
202 .enable = s3c64xx_sclk_ctrl,
203 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
204 }, {
205 .name = "48m",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900206 .devname = "s3c-sdhci.1",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100207 .parent = &clk_48m,
208 .enable = s3c64xx_sclk_ctrl,
209 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
210 }, {
211 .name = "48m",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900212 .devname = "s3c-sdhci.2",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100213 .parent = &clk_48m,
214 .enable = s3c64xx_sclk_ctrl,
215 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
Mark Brown8f1ecf12009-04-28 16:06:24 +0100216 }, {
217 .name = "dma0",
Mark Brown8f1ecf12009-04-28 16:06:24 +0100218 .parent = &clk_h,
219 .enable = s3c64xx_hclk_ctrl,
220 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
221 }, {
222 .name = "dma1",
Mark Brown8f1ecf12009-04-28 16:06:24 +0100223 .parent = &clk_h,
224 .enable = s3c64xx_hclk_ctrl,
225 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100226 },
227};
228
229static struct clk init_clocks[] = {
230 {
231 .name = "lcd",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100232 .parent = &clk_h,
233 .enable = s3c64xx_hclk_ctrl,
234 .ctrlbit = S3C_CLKCON_HCLK_LCD,
235 }, {
236 .name = "gpio",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100237 .parent = &clk_p,
238 .enable = s3c64xx_pclk_ctrl,
239 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
240 }, {
241 .name = "usb-host",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100242 .parent = &clk_h,
243 .enable = s3c64xx_hclk_ctrl,
Peter Korsgaard386f4352009-06-18 23:54:44 +0200244 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100245 }, {
Thomas Abraham5f4c5b22010-05-28 11:41:14 +0900246 .name = "otg",
Thomas Abraham5f4c5b22010-05-28 11:41:14 +0900247 .parent = &clk_h,
248 .enable = s3c64xx_hclk_ctrl,
249 .ctrlbit = S3C_CLKCON_HCLK_USB,
250 }, {
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100251 .name = "timers",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100252 .parent = &clk_p,
253 .enable = s3c64xx_pclk_ctrl,
254 .ctrlbit = S3C_CLKCON_PCLK_PWM,
255 }, {
256 .name = "uart",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900257 .devname = "s3c6400-uart.0",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100258 .parent = &clk_p,
259 .enable = s3c64xx_pclk_ctrl,
260 .ctrlbit = S3C_CLKCON_PCLK_UART0,
261 }, {
262 .name = "uart",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900263 .devname = "s3c6400-uart.1",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100264 .parent = &clk_p,
265 .enable = s3c64xx_pclk_ctrl,
266 .ctrlbit = S3C_CLKCON_PCLK_UART1,
267 }, {
268 .name = "uart",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900269 .devname = "s3c6400-uart.2",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100270 .parent = &clk_p,
271 .enable = s3c64xx_pclk_ctrl,
272 .ctrlbit = S3C_CLKCON_PCLK_UART2,
273 }, {
274 .name = "uart",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900275 .devname = "s3c6400-uart.3",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100276 .parent = &clk_p,
277 .enable = s3c64xx_pclk_ctrl,
278 .ctrlbit = S3C_CLKCON_PCLK_UART3,
279 }, {
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100280 .name = "watchdog",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100281 .parent = &clk_p,
282 .ctrlbit = S3C_CLKCON_PCLK_WDT,
283 }, {
284 .name = "ac97",
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100285 .parent = &clk_p,
286 .ctrlbit = S3C_CLKCON_PCLK_AC97,
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +0900287 }, {
288 .name = "cfcon",
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +0900289 .parent = &clk_h,
290 .enable = s3c64xx_hclk_ctrl,
291 .ctrlbit = S3C_CLKCON_HCLK_IHOST,
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100292 }
293};
294
Rajeshwari Shindea361d102011-10-24 17:05:58 +0200295static struct clk clk_hsmmc0 = {
296 .name = "hsmmc",
297 .devname = "s3c-sdhci.0",
298 .parent = &clk_h,
299 .enable = s3c64xx_hclk_ctrl,
300 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
301};
302
303static struct clk clk_hsmmc1 = {
304 .name = "hsmmc",
305 .devname = "s3c-sdhci.1",
306 .parent = &clk_h,
307 .enable = s3c64xx_hclk_ctrl,
308 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
309};
310
311static struct clk clk_hsmmc2 = {
312 .name = "hsmmc",
313 .devname = "s3c-sdhci.2",
314 .parent = &clk_h,
315 .enable = s3c64xx_hclk_ctrl,
316 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
317};
Ben Dooks62acb2f2010-01-26 14:53:19 +0900318
319static struct clk clk_fout_apll = {
320 .name = "fout_apll",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900321};
322
323static struct clk *clk_src_apll_list[] = {
324 [0] = &clk_fin_apll,
325 [1] = &clk_fout_apll,
326};
327
328static struct clksrc_sources clk_src_apll = {
329 .sources = clk_src_apll_list,
330 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
331};
332
333static struct clksrc_clk clk_mout_apll = {
334 .clk = {
335 .name = "mout_apll",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900336 },
337 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
338 .sources = &clk_src_apll,
339};
340
341static struct clk *clk_src_epll_list[] = {
342 [0] = &clk_fin_epll,
343 [1] = &clk_fout_epll,
344};
345
346static struct clksrc_sources clk_src_epll = {
347 .sources = clk_src_epll_list,
348 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
349};
350
351static struct clksrc_clk clk_mout_epll = {
352 .clk = {
353 .name = "mout_epll",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900354 },
355 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
356 .sources = &clk_src_epll,
357};
358
359static struct clk *clk_src_mpll_list[] = {
360 [0] = &clk_fin_mpll,
361 [1] = &clk_fout_mpll,
362};
363
364static struct clksrc_sources clk_src_mpll = {
365 .sources = clk_src_mpll_list,
366 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
367};
368
369static struct clksrc_clk clk_mout_mpll = {
370 .clk = {
371 .name = "mout_mpll",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900372 },
373 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
374 .sources = &clk_src_mpll,
375};
376
377static unsigned int armclk_mask;
378
379static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
380{
381 unsigned long rate = clk_get_rate(clk->parent);
382 u32 clkdiv;
383
384 /* divisor mask starts at bit0, so no need to shift */
385 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
386
387 return rate / (clkdiv + 1);
388}
389
390static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
391 unsigned long rate)
392{
393 unsigned long parent = clk_get_rate(clk->parent);
394 u32 div;
395
396 if (parent < rate)
397 return parent;
398
399 div = (parent / rate) - 1;
400 if (div > armclk_mask)
401 div = armclk_mask;
402
403 return parent / (div + 1);
404}
405
406static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
407{
408 unsigned long parent = clk_get_rate(clk->parent);
409 u32 div;
410 u32 val;
411
412 if (rate < parent / (armclk_mask + 1))
413 return -EINVAL;
414
415 rate = clk_round_rate(clk, rate);
416 div = clk_get_rate(clk->parent) / rate;
417
418 val = __raw_readl(S3C_CLK_DIV0);
419 val &= ~armclk_mask;
420 val |= (div - 1);
421 __raw_writel(val, S3C_CLK_DIV0);
422
423 return 0;
424
425}
426
427static struct clk clk_arm = {
428 .name = "armclk",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900429 .parent = &clk_mout_apll.clk,
430 .ops = &(struct clk_ops) {
431 .get_rate = s3c64xx_clk_arm_get_rate,
432 .set_rate = s3c64xx_clk_arm_set_rate,
433 .round_rate = s3c64xx_clk_arm_round_rate,
434 },
435};
436
437static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
438{
439 unsigned long rate = clk_get_rate(clk->parent);
440
441 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
442
443 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
444 rate /= 2;
445
446 return rate;
447}
448
449static struct clk_ops clk_dout_ops = {
450 .get_rate = s3c64xx_clk_doutmpll_get_rate,
451};
452
453static struct clk clk_dout_mpll = {
454 .name = "dout_mpll",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900455 .parent = &clk_mout_mpll.clk,
456 .ops = &clk_dout_ops,
457};
458
459static struct clk *clkset_spi_mmc_list[] = {
460 &clk_mout_epll.clk,
461 &clk_dout_mpll,
462 &clk_fin_epll,
463 &clk_27m,
464};
465
466static struct clksrc_sources clkset_spi_mmc = {
467 .sources = clkset_spi_mmc_list,
468 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
469};
470
471static struct clk *clkset_irda_list[] = {
472 &clk_mout_epll.clk,
473 &clk_dout_mpll,
474 NULL,
475 &clk_27m,
476};
477
478static struct clksrc_sources clkset_irda = {
479 .sources = clkset_irda_list,
480 .nr_sources = ARRAY_SIZE(clkset_irda_list),
481};
482
483static struct clk *clkset_uart_list[] = {
484 &clk_mout_epll.clk,
485 &clk_dout_mpll,
486 NULL,
487 NULL
488};
489
490static struct clksrc_sources clkset_uart = {
491 .sources = clkset_uart_list,
492 .nr_sources = ARRAY_SIZE(clkset_uart_list),
493};
494
495static struct clk *clkset_uhost_list[] = {
496 &clk_48m,
497 &clk_mout_epll.clk,
498 &clk_dout_mpll,
499 &clk_fin_epll,
500};
501
502static struct clksrc_sources clkset_uhost = {
503 .sources = clkset_uhost_list,
504 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
505};
506
507/* The peripheral clocks are all controlled via clocksource followed
508 * by an optional divider and gate stage. We currently roll this into
509 * one clock which hides the intermediate clock from the mux.
510 *
511 * Note, the JPEG clock can only be an even divider...
512 *
513 * The scaler and LCD clocks depend on the S3C64XX version, and also
514 * have a common parent divisor so are not included here.
515 */
516
517/* clocks that feed other parts of the clock source tree */
518
519static struct clk clk_iis_cd0 = {
520 .name = "iis_cdclk0",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900521};
522
523static struct clk clk_iis_cd1 = {
524 .name = "iis_cdclk1",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900525};
526
Jassi Brarbc8eb1e2010-03-09 15:10:32 +0900527static struct clk clk_iisv4_cd = {
528 .name = "iis_cdclk_v4",
Jassi Brarbc8eb1e2010-03-09 15:10:32 +0900529};
530
Ben Dooks62acb2f2010-01-26 14:53:19 +0900531static struct clk clk_pcm_cd = {
532 .name = "pcm_cdclk",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900533};
534
535static struct clk *clkset_audio0_list[] = {
536 [0] = &clk_mout_epll.clk,
537 [1] = &clk_dout_mpll,
538 [2] = &clk_fin_epll,
539 [3] = &clk_iis_cd0,
540 [4] = &clk_pcm_cd,
541};
542
543static struct clksrc_sources clkset_audio0 = {
544 .sources = clkset_audio0_list,
545 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
546};
547
548static struct clk *clkset_audio1_list[] = {
549 [0] = &clk_mout_epll.clk,
550 [1] = &clk_dout_mpll,
551 [2] = &clk_fin_epll,
552 [3] = &clk_iis_cd1,
553 [4] = &clk_pcm_cd,
554};
555
556static struct clksrc_sources clkset_audio1 = {
557 .sources = clkset_audio1_list,
558 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
559};
560
Jassi Brar1aede2e2010-03-09 15:10:33 +0900561static struct clk *clkset_audio2_list[] = {
562 [0] = &clk_mout_epll.clk,
563 [1] = &clk_dout_mpll,
564 [2] = &clk_fin_epll,
565 [3] = &clk_iisv4_cd,
566 [4] = &clk_pcm_cd,
567};
568
569static struct clksrc_sources clkset_audio2 = {
570 .sources = clkset_audio2_list,
571 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
572};
573
Ben Dooks62acb2f2010-01-26 14:53:19 +0900574static struct clk *clkset_camif_list[] = {
575 &clk_h2,
576};
577
578static struct clksrc_sources clkset_camif = {
579 .sources = clkset_camif_list,
580 .nr_sources = ARRAY_SIZE(clkset_camif_list),
581};
582
583static struct clksrc_clk clksrcs[] = {
584 {
585 .clk = {
Ben Dooks62acb2f2010-01-26 14:53:19 +0900586 .name = "usb-bus-host",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900587 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
588 .enable = s3c64xx_sclk_ctrl,
589 },
590 .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
591 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
592 .sources = &clkset_uhost,
593 }, {
594 .clk = {
Ben Dooks62acb2f2010-01-26 14:53:19 +0900595 .name = "spi-bus",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900596 .devname = "s3c64xx-spi.0",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900597 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
598 .enable = s3c64xx_sclk_ctrl,
599 },
600 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
601 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
602 .sources = &clkset_spi_mmc,
603 }, {
604 .clk = {
605 .name = "spi-bus",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900606 .devname = "s3c64xx-spi.1",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900607 .enable = s3c64xx_sclk_ctrl,
608 },
609 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
610 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
611 .sources = &clkset_spi_mmc,
612 }, {
613 .clk = {
614 .name = "audio-bus",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900615 .devname = "samsung-i2s.0",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900616 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
617 .enable = s3c64xx_sclk_ctrl,
618 },
619 .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
620 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
621 .sources = &clkset_audio0,
622 }, {
623 .clk = {
624 .name = "audio-bus",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900625 .devname = "samsung-i2s.1",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900626 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
627 .enable = s3c64xx_sclk_ctrl,
628 },
629 .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
630 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
631 .sources = &clkset_audio1,
632 }, {
633 .clk = {
Jassi Brar835879a2010-03-09 15:10:34 +0900634 .name = "audio-bus",
Thomas Abraham226e85f2011-06-14 19:12:26 +0900635 .devname = "samsung-i2s.2",
Jassi Brar835879a2010-03-09 15:10:34 +0900636 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
637 .enable = s3c64xx_sclk_ctrl,
638 },
639 .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
640 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
641 .sources = &clkset_audio2,
642 }, {
643 .clk = {
Ben Dooks62acb2f2010-01-26 14:53:19 +0900644 .name = "irda-bus",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900645 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
646 .enable = s3c64xx_sclk_ctrl,
647 },
648 .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
649 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
650 .sources = &clkset_irda,
651 }, {
652 .clk = {
653 .name = "camera",
Ben Dooks62acb2f2010-01-26 14:53:19 +0900654 .ctrlbit = S3C_CLKCON_SCLK_CAM,
655 .enable = s3c64xx_sclk_ctrl,
656 },
657 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
658 .reg_src = { .reg = NULL, .shift = 0, .size = 0 },
659 .sources = &clkset_camif,
660 },
661};
662
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200663/* Where does UCLK0 come from? */
664static struct clksrc_clk clk_sclk_uclk = {
665 .clk = {
666 .name = "uclk1",
667 .ctrlbit = S3C_CLKCON_SCLK_UART,
668 .enable = s3c64xx_sclk_ctrl,
669 },
670 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
671 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
672 .sources = &clkset_uart,
673};
674
Rajeshwari Shindea361d102011-10-24 17:05:58 +0200675static struct clksrc_clk clk_sclk_mmc0 = {
676 .clk = {
677 .name = "mmc_bus",
678 .devname = "s3c-sdhci.0",
679 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
680 .enable = s3c64xx_sclk_ctrl,
681 },
682 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
683 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
684 .sources = &clkset_spi_mmc,
685};
686
687static struct clksrc_clk clk_sclk_mmc1 = {
688 .clk = {
689 .name = "mmc_bus",
690 .devname = "s3c-sdhci.1",
691 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
692 .enable = s3c64xx_sclk_ctrl,
693 },
694 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
695 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
696 .sources = &clkset_spi_mmc,
697};
698
699static struct clksrc_clk clk_sclk_mmc2 = {
700 .clk = {
701 .name = "mmc_bus",
702 .devname = "s3c-sdhci.2",
703 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
704 .enable = s3c64xx_sclk_ctrl,
705 },
706 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
707 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
708 .sources = &clkset_spi_mmc,
709};
710
Ben Dooks62acb2f2010-01-26 14:53:19 +0900711/* Clock initialisation code */
712
713static struct clksrc_clk *init_parents[] = {
714 &clk_mout_apll,
715 &clk_mout_epll,
716 &clk_mout_mpll,
717};
718
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200719static struct clksrc_clk *clksrc_cdev[] = {
720 &clk_sclk_uclk,
Rajeshwari Shindea361d102011-10-24 17:05:58 +0200721 &clk_sclk_mmc0,
722 &clk_sclk_mmc1,
723 &clk_sclk_mmc2,
724};
725
726static struct clk *clk_cdev[] = {
727 &clk_hsmmc0,
728 &clk_hsmmc1,
729 &clk_hsmmc2,
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200730};
731
732static struct clk_lookup s3c64xx_clk_lookup[] = {
733 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
734 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
Rajeshwari Shindea361d102011-10-24 17:05:58 +0200735 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
736 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
737 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
738 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
739 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
740 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200741};
742
Ben Dooks62acb2f2010-01-26 14:53:19 +0900743#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
744
745void __init_or_cpufreq s3c6400_setup_clocks(void)
746{
747 struct clk *xtal_clk;
748 unsigned long xtal;
749 unsigned long fclk;
750 unsigned long hclk;
751 unsigned long hclk2;
752 unsigned long pclk;
753 unsigned long epll;
754 unsigned long apll;
755 unsigned long mpll;
756 unsigned int ptr;
757 u32 clkdiv0;
758
759 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
760
761 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
762 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
763
764 xtal_clk = clk_get(NULL, "xtal");
765 BUG_ON(IS_ERR(xtal_clk));
766
767 xtal = clk_get_rate(xtal_clk);
768 clk_put(xtal_clk);
769
770 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
771
772 /* For now assume the mux always selects the crystal */
773 clk_ext_xtal_mux.parent = xtal_clk;
774
Kukjin Kim52e329e2011-10-04 19:41:43 +0900775 epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
776 __raw_readl(S3C_EPLL_CON1));
Ben Dooks62acb2f2010-01-26 14:53:19 +0900777 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
778 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
779
780 fclk = mpll;
781
782 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
783 apll, mpll, epll);
784
Tomasz Figafb5d3752011-08-19 11:54:31 +0200785 if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
786 /* Synchronous mode */
787 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
788 else
789 /* Asynchronous mode */
790 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
791
Ben Dooks62acb2f2010-01-26 14:53:19 +0900792 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
793 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
794
795 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
796 hclk2, hclk, pclk);
797
798 clk_fout_mpll.rate = mpll;
799 clk_fout_epll.rate = epll;
800 clk_fout_apll.rate = apll;
801
802 clk_h2.rate = hclk2;
803 clk_h.rate = hclk;
804 clk_p.rate = pclk;
805 clk_f.rate = fclk;
806
807 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
808 s3c_set_clksrc(init_parents[ptr], true);
809
810 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
811 s3c_set_clksrc(&clksrcs[ptr], true);
812}
813
814static struct clk *clks1[] __initdata = {
815 &clk_ext_xtal_mux,
816 &clk_iis_cd0,
817 &clk_iis_cd1,
Jassi Brarbc8eb1e2010-03-09 15:10:32 +0900818 &clk_iisv4_cd,
Ben Dooks62acb2f2010-01-26 14:53:19 +0900819 &clk_pcm_cd,
820 &clk_mout_epll.clk,
821 &clk_mout_mpll.clk,
822 &clk_dout_mpll,
823 &clk_arm,
824};
825
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100826static struct clk *clks[] __initdata = {
827 &clk_ext,
828 &clk_epll,
829 &clk_27m,
830 &clk_48m,
Werner Almesbergera03f7da2009-03-05 11:43:13 +0800831 &clk_h2,
Maurus Cuelenaere05e021f2010-05-17 20:17:42 +0200832 &clk_xusbxti,
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100833};
834
Ben Dooks55bf9262010-01-26 15:10:38 +0900835/**
836 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
837 * @xtal: The rate for the clock crystal feeding the PLLs.
838 * @armclk_divlimit: Divisor mask for ARMCLK.
839 *
840 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
841 * as ARMCLK as well as the necessary parent clocks.
842 *
843 * This call does not setup the clocks, which is left to the
844 * s3c6400_setup_clocks() call which may be needed by the cpufreq
845 * or resume code to re-set the clocks if the bootloader has changed
846 * them.
847 */
848void __init s3c64xx_register_clocks(unsigned long xtal,
849 unsigned armclk_divlimit)
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100850{
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200851 unsigned int cnt;
852
Ben Dooks55bf9262010-01-26 15:10:38 +0900853 armclk_mask = armclk_divlimit;
854
855 s3c24xx_register_baseclocks(xtal);
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100856 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
Ben Dooks55bf9262010-01-26 15:10:38 +0900857
Ben Dooks1d9f13c2010-01-06 01:21:38 +0900858 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100859
Kukjin Kimcdb216d2011-01-04 18:27:18 +0900860 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
861 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
Ben Dooks9d325f22008-11-21 10:36:05 +0000862
Rajeshwari Shindea361d102011-10-24 17:05:58 +0200863 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
864 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
865 s3c_disable_clocks(clk_cdev[cnt], 1);
866
Ben Dooks55bf9262010-01-26 15:10:38 +0900867 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
868 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
Thomas Abraham0cfb26e2011-10-24 12:08:42 +0200869 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
870 s3c_register_clksrc(clksrc_cdev[cnt], 1);
871 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
872
Ben Dooks9d325f22008-11-21 10:36:05 +0000873 s3c_pwmclk_init();
Ben Dooks4b31d8b2008-10-21 14:07:00 +0100874}