| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 1 | # Put here option for CPU selection and depending optimization | 
 | 2 | if !X86_ELAN | 
 | 3 |  | 
 | 4 | choice | 
 | 5 | 	prompt "Processor family" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 6 | 	default M686 if X86_32 | 
 | 7 | 	default GENERIC_CPU if X86_64 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 8 |  | 
 | 9 | config M386 | 
 | 10 | 	bool "386" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 11 | 	depends on X86_32 && !UML | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 12 | 	---help--- | 
 | 13 | 	  This is the processor type of your CPU. This information is used for | 
 | 14 | 	  optimizing purposes. In order to compile a kernel that can run on | 
 | 15 | 	  all x86 CPU types (albeit not optimally fast), you can specify | 
 | 16 | 	  "386" here. | 
 | 17 |  | 
 | 18 | 	  The kernel will not necessarily run on earlier architectures than | 
 | 19 | 	  the one you have chosen, e.g. a Pentium optimized kernel will run on | 
 | 20 | 	  a PPro, but not necessarily on a i486. | 
 | 21 |  | 
 | 22 | 	  Here are the settings recommended for greatest speed: | 
 | 23 | 	  - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI | 
| Dmitri Vorobiev | f7f17a6 | 2008-04-21 00:47:55 +0400 | [diff] [blame] | 24 | 	  486DLC/DLC2, and UMC 486SX-S.  Only "386" kernels will run on a 386 | 
 | 25 | 	  class machine. | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 26 | 	  - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or | 
 | 27 | 	  SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. | 
 | 28 | 	  - "586" for generic Pentium CPUs lacking the TSC | 
 | 29 | 	  (time stamp counter) register. | 
 | 30 | 	  - "Pentium-Classic" for the Intel Pentium. | 
 | 31 | 	  - "Pentium-MMX" for the Intel Pentium MMX. | 
 | 32 | 	  - "Pentium-Pro" for the Intel Pentium Pro. | 
 | 33 | 	  - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron. | 
 | 34 | 	  - "Pentium-III" for the Intel Pentium III or Coppermine Celeron. | 
 | 35 | 	  - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. | 
 | 36 | 	  - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). | 
 | 37 | 	  - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). | 
 | 38 | 	  - "Crusoe" for the Transmeta Crusoe series. | 
 | 39 | 	  - "Efficeon" for the Transmeta Efficeon series. | 
 | 40 | 	  - "Winchip-C6" for original IDT Winchip. | 
| Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 41 | 	  - "Winchip-2" for IDT Winchips with 3dNow! capabilities. | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 42 | 	  - "GeodeGX1" for Geode GX1 (Cyrix MediaGX). | 
| Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 43 | 	  - "Geode GX/LX" For AMD Geode GX and LX processors. | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 44 | 	  - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. | 
| Egry Gabor | 48a1204 | 2006-06-26 18:47:15 +0200 | [diff] [blame] | 45 | 	  - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). | 
| Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 46 | 	  - "VIA C7" for VIA C7. | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 47 |  | 
 | 48 | 	  If you don't know what to do, choose "386". | 
 | 49 |  | 
 | 50 | config M486 | 
 | 51 | 	bool "486" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 52 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 53 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 54 | 	  Select this for a 486 series processor, either Intel or one of the | 
 | 55 | 	  compatible processors from AMD, Cyrix, IBM, or Intel.  Includes DX, | 
 | 56 | 	  DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or | 
 | 57 | 	  U5S. | 
 | 58 |  | 
 | 59 | config M586 | 
 | 60 | 	bool "586/K5/5x86/6x86/6x86MX" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 61 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 62 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 63 | 	  Select this for an 586 or 686 series processor such as the AMD K5, | 
 | 64 | 	  the Cyrix 5x86, 6x86 and 6x86MX.  This choice does not | 
 | 65 | 	  assume the RDTSC (Read Time Stamp Counter) instruction. | 
 | 66 |  | 
 | 67 | config M586TSC | 
 | 68 | 	bool "Pentium-Classic" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 69 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 70 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 71 | 	  Select this for a Pentium Classic processor with the RDTSC (Read | 
 | 72 | 	  Time Stamp Counter) instruction for benchmarking. | 
 | 73 |  | 
 | 74 | config M586MMX | 
 | 75 | 	bool "Pentium-MMX" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 76 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 77 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 78 | 	  Select this for a Pentium with the MMX graphics/multimedia | 
 | 79 | 	  extended instructions. | 
 | 80 |  | 
 | 81 | config M686 | 
 | 82 | 	bool "Pentium-Pro" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 83 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 84 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 85 | 	  Select this for Intel Pentium Pro chips.  This enables the use of | 
 | 86 | 	  Pentium Pro extended instructions, and disables the init-time guard | 
 | 87 | 	  against the f00f bug found in earlier Pentiums. | 
 | 88 |  | 
 | 89 | config MPENTIUMII | 
 | 90 | 	bool "Pentium-II/Celeron(pre-Coppermine)" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 91 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 92 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 93 | 	  Select this for Intel chips based on the Pentium-II and | 
 | 94 | 	  pre-Coppermine Celeron core.  This option enables an unaligned | 
 | 95 | 	  copy optimization, compiles the kernel with optimization flags | 
 | 96 | 	  tailored for the chip, and applies any applicable Pentium Pro | 
 | 97 | 	  optimizations. | 
 | 98 |  | 
 | 99 | config MPENTIUMIII | 
 | 100 | 	bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 101 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 102 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 103 | 	  Select this for Intel chips based on the Pentium-III and | 
 | 104 | 	  Celeron-Coppermine core.  This option enables use of some | 
 | 105 | 	  extended prefetch instructions in addition to the Pentium II | 
 | 106 | 	  extensions. | 
 | 107 |  | 
 | 108 | config MPENTIUMM | 
 | 109 | 	bool "Pentium M" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 110 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 111 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 112 | 	  Select this for Intel Pentium M (not Pentium-4 M) | 
 | 113 | 	  notebook chips. | 
 | 114 |  | 
 | 115 | config MPENTIUM4 | 
| Andi Kleen | c55d92d | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 116 | 	bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 117 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 118 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 119 | 	  Select this for Intel Pentium 4 chips.  This includes the | 
| Oliver Pinter | 75e3808 | 2007-10-17 18:04:36 +0200 | [diff] [blame] | 120 | 	  Pentium 4, Pentium D, P4-based Celeron and Xeon, and | 
 | 121 | 	  Pentium-4 M (not Pentium M) chips.  This option enables compile | 
 | 122 | 	  flags optimized for the chip, uses the correct cache line size, and | 
 | 123 | 	  applies any applicable optimizations. | 
 | 124 |  | 
 | 125 | 	  CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 ) | 
 | 126 |  | 
 | 127 | 	  Select this for: | 
 | 128 | 	    Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename: | 
 | 129 | 		-Willamette | 
 | 130 | 		-Northwood | 
 | 131 | 		-Mobile Pentium 4 | 
 | 132 | 		-Mobile Pentium 4 M | 
 | 133 | 		-Extreme Edition (Gallatin) | 
 | 134 | 		-Prescott | 
 | 135 | 		-Prescott 2M | 
 | 136 | 		-Cedar Mill | 
 | 137 | 		-Presler | 
 | 138 | 		-Smithfiled | 
 | 139 | 	    Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: | 
 | 140 | 		-Foster | 
 | 141 | 		-Prestonia | 
 | 142 | 		-Gallatin | 
 | 143 | 		-Nocona | 
 | 144 | 		-Irwindale | 
 | 145 | 		-Cranford | 
 | 146 | 		-Potomac | 
 | 147 | 		-Paxville | 
 | 148 | 		-Dempsey | 
 | 149 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 150 |  | 
 | 151 | config MK6 | 
 | 152 | 	bool "K6/K6-II/K6-III" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 153 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 154 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 155 | 	  Select this for an AMD K6-family processor.  Enables use of | 
 | 156 | 	  some extended instructions, and passes appropriate optimization | 
 | 157 | 	  flags to GCC. | 
 | 158 |  | 
 | 159 | config MK7 | 
 | 160 | 	bool "Athlon/Duron/K7" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 161 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 162 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 163 | 	  Select this for an AMD Athlon K7-family processor.  Enables use of | 
 | 164 | 	  some extended instructions, and passes appropriate optimization | 
 | 165 | 	  flags to GCC. | 
 | 166 |  | 
 | 167 | config MK8 | 
 | 168 | 	bool "Opteron/Athlon64/Hammer/K8" | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 169 | 	---help--- | 
| Borislav Petkov | 36723bf | 2009-02-04 21:44:04 +0100 | [diff] [blame] | 170 | 	  Select this for an AMD Opteron or Athlon64 Hammer-family processor. | 
 | 171 | 	  Enables use of some extended instructions, and passes appropriate | 
 | 172 | 	  optimization flags to GCC. | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 173 |  | 
 | 174 | config MCRUSOE | 
 | 175 | 	bool "Crusoe" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 176 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 177 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 178 | 	  Select this for a Transmeta Crusoe processor.  Treats the processor | 
 | 179 | 	  like a 586 with TSC, and sets some GCC optimization flags (like a | 
 | 180 | 	  Pentium Pro with no alignment requirements). | 
 | 181 |  | 
 | 182 | config MEFFICEON | 
 | 183 | 	bool "Efficeon" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 184 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 185 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 186 | 	  Select this for a Transmeta Efficeon processor. | 
 | 187 |  | 
 | 188 | config MWINCHIPC6 | 
 | 189 | 	bool "Winchip-C6" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 190 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 191 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 192 | 	  Select this for an IDT Winchip C6 chip.  Linux and GCC | 
 | 193 | 	  treat this chip as a 586TSC with some extended instructions | 
 | 194 | 	  and alignment requirements. | 
 | 195 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 196 | config MWINCHIP3D | 
| Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 197 | 	bool "Winchip-2/Winchip-2A/Winchip-3" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 198 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 199 | 	---help--- | 
| Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 200 | 	  Select this for an IDT Winchip-2, 2A or 3.  Linux and GCC | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 201 | 	  treat this chip as a 586TSC with some extended instructions | 
| David Sterba | 3dde6ad | 2007-05-09 07:12:20 +0200 | [diff] [blame] | 202 | 	  and alignment requirements.  Also enable out of order memory | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 203 | 	  stores for this CPU, which can increase performance of some | 
 | 204 | 	  operations. | 
 | 205 |  | 
 | 206 | config MGEODEGX1 | 
 | 207 | 	bool "GeodeGX1" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 208 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 209 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 210 | 	  Select this for a Geode GX1 (Cyrix MediaGX) chip. | 
 | 211 |  | 
| Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 212 | config MGEODE_LX | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 213 | 	bool "Geode GX/LX" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 214 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 215 | 	---help--- | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 216 | 	  Select this for AMD Geode GX and LX processors. | 
| Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 217 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 218 | config MCYRIXIII | 
 | 219 | 	bool "CyrixIII/VIA-C3" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 220 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 221 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 222 | 	  Select this for a Cyrix III or C3 chip.  Presently Linux and GCC | 
 | 223 | 	  treat this chip as a generic 586. Whilst the CPU is 686 class, | 
 | 224 | 	  it lacks the cmov extension which gcc assumes is present when | 
 | 225 | 	  generating 686 code. | 
 | 226 | 	  Note that Nehemiah (Model 9) and above will not boot with this | 
 | 227 | 	  kernel due to them lacking the 3DNow! instructions used in earlier | 
 | 228 | 	  incarnations of the CPU. | 
 | 229 |  | 
 | 230 | config MVIAC3_2 | 
 | 231 | 	bool "VIA C3-2 (Nehemiah)" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 232 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 233 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 234 | 	  Select this for a VIA C3 "Nehemiah". Selecting this enables usage | 
 | 235 | 	  of SSE and tells gcc to treat the CPU as a 686. | 
 | 236 | 	  Note, this kernel will not boot on older (pre model 9) C3s. | 
 | 237 |  | 
| Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 238 | config MVIAC7 | 
 | 239 | 	bool "VIA C7" | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 240 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 241 | 	---help--- | 
| Simon Arlott | 0949be3 | 2007-05-02 19:27:05 +0200 | [diff] [blame] | 242 | 	  Select this for a VIA C7.  Selecting this uses the correct cache | 
 | 243 | 	  shift and tells gcc to treat the CPU as a 686. | 
 | 244 |  | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 245 | config MPSC | 
 | 246 | 	bool "Intel P4 / older Netburst based Xeon" | 
 | 247 | 	depends on X86_64 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 248 | 	---help--- | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 249 | 	  Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey | 
 | 250 | 	  Xeon CPUs with Intel 64bit which is compatible with x86-64. | 
 | 251 | 	  Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 252 | 	  Netburst core and shouldn't use this option. You can distinguish them | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 253 | 	  using the cpu family field | 
 | 254 | 	  in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. | 
 | 255 |  | 
 | 256 | config MCORE2 | 
 | 257 | 	bool "Core 2/newer Xeon" | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 258 | 	---help--- | 
| Borislav Petkov | 36723bf | 2009-02-04 21:44:04 +0100 | [diff] [blame] | 259 |  | 
 | 260 | 	  Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and | 
 | 261 | 	  53xx) CPUs. You can distinguish newer from older Xeons by the CPU | 
 | 262 | 	  family in /proc/cpuinfo. Newer ones have 6 and older ones 15 | 
 | 263 | 	  (not a typo) | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 264 |  | 
 | 265 | config GENERIC_CPU | 
 | 266 | 	bool "Generic-x86-64" | 
 | 267 | 	depends on X86_64 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 268 | 	---help--- | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 269 | 	  Generic x86-64 CPU. | 
 | 270 | 	  Run equally well on all x86-64 CPUs. | 
 | 271 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 272 | endchoice | 
 | 273 |  | 
 | 274 | config X86_GENERIC | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 275 | 	bool "Generic x86 support" | 
 | 276 | 	depends on X86_32 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 277 | 	---help--- | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 278 | 	  Instead of just including optimizations for the selected | 
 | 279 | 	  x86 variant (e.g. PII, Crusoe or Athlon), include some more | 
 | 280 | 	  generic optimizations as well. This will make the kernel | 
 | 281 | 	  perform better on x86 CPUs other than that selected. | 
 | 282 |  | 
 | 283 | 	  This is really intended for distributors who need more | 
 | 284 | 	  generic optimizations. | 
 | 285 |  | 
 | 286 | endif | 
 | 287 |  | 
| Ingo Molnar | acbaa93 | 2008-04-30 08:58:27 +0200 | [diff] [blame] | 288 | config X86_CPU | 
 | 289 | 	def_bool y | 
 | 290 | 	select GENERIC_FIND_FIRST_BIT | 
 | 291 | 	select GENERIC_FIND_NEXT_BIT | 
 | 292 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 293 | # | 
 | 294 | # Define implied options from the CPU selection here | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 295 | config X86_L1_CACHE_BYTES | 
 | 296 | 	int | 
| Ingo Molnar | ace6c6c | 2009-01-21 10:32:44 +0100 | [diff] [blame] | 297 | 	default "128" if MPSC | 
 | 298 | 	default "64" if GENERIC_CPU || MK8 || MCORE2 || X86_32 | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 299 |  | 
 | 300 | config X86_INTERNODE_CACHE_BYTES | 
 | 301 | 	int | 
 | 302 | 	default "4096" if X86_VSMP | 
 | 303 | 	default X86_L1_CACHE_BYTES if !X86_VSMP | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 304 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 305 | config X86_CMPXCHG | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 306 | 	def_bool X86_64 || (X86_32 && !M386) | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 307 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 308 | config X86_L1_CACHE_SHIFT | 
 | 309 | 	int | 
| Ingo Molnar | 0a2a18b7 | 2009-01-12 23:37:16 +0100 | [diff] [blame] | 310 | 	default "7" if MPENTIUM4 || MPSC | 
| Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 311 | 	default "4" if X86_ELAN || M486 || M386 || MGEODEGX1 | 
| Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 312 | 	default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX | 
| Ingo Molnar | 0a2a18b7 | 2009-01-12 23:37:16 +0100 | [diff] [blame] | 313 | 	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7 || X86_GENERIC || GENERIC_CPU | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 314 |  | 
| Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 315 | config X86_XADD | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 316 | 	def_bool y | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 317 | 	depends on X86_32 && !M386 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 318 |  | 
 | 319 | config X86_PPRO_FENCE | 
| Nick Piggin | fb0328e | 2008-01-30 13:32:31 +0100 | [diff] [blame] | 320 | 	bool "PentiumPro memory ordering errata workaround" | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 321 | 	depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1 | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 322 | 	---help--- | 
| Borislav Petkov | 36723bf | 2009-02-04 21:44:04 +0100 | [diff] [blame] | 323 | 	  Old PentiumPro multiprocessor systems had errata that could cause | 
 | 324 | 	  memory operations to violate the x86 ordering standard in rare cases. | 
 | 325 | 	  Enabling this option will attempt to work around some (but not all) | 
 | 326 | 	  occurances of this problem, at the cost of much heavier spinlock and | 
 | 327 | 	  memory barrier operations. | 
| Nick Piggin | fb0328e | 2008-01-30 13:32:31 +0100 | [diff] [blame] | 328 |  | 
| Borislav Petkov | 36723bf | 2009-02-04 21:44:04 +0100 | [diff] [blame] | 329 | 	  If unsure, say n here. Even distro kernels should think twice before | 
 | 330 | 	  enabling this: there are few systems, and an unlikely bug. | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 331 |  | 
 | 332 | config X86_F00F_BUG | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 333 | 	def_bool y | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 334 | 	depends on M586MMX || M586TSC || M586 || M486 || M386 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 335 |  | 
 | 336 | config X86_WP_WORKS_OK | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 337 | 	def_bool y | 
| Glauber Costa | 293e6a2 | 2008-06-25 11:40:42 -0300 | [diff] [blame] | 338 | 	depends on !M386 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 339 |  | 
 | 340 | config X86_INVLPG | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 341 | 	def_bool y | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 342 | 	depends on X86_32 && !M386 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 343 |  | 
 | 344 | config X86_BSWAP | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 345 | 	def_bool y | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 346 | 	depends on X86_32 && !M386 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 347 |  | 
 | 348 | config X86_POPAD_OK | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 349 | 	def_bool y | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 350 | 	depends on X86_32 && !M386 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 351 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 352 | config X86_ALIGNMENT_16 | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 353 | 	def_bool y | 
| Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 354 | 	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 355 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 356 | config X86_INTEL_USERCOPY | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 357 | 	def_bool y | 
| Andi Kleen | c55d92d | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 358 | 	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 359 |  | 
 | 360 | config X86_USE_PPRO_CHECKSUM | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 361 | 	def_bool y | 
| Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 362 | 	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2 | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 363 |  | 
 | 364 | config X86_USE_3DNOW | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 365 | 	def_bool y | 
| Paolo 'Blaisorblade' Giarrusso | 1b4ad24 | 2006-10-11 01:21:35 -0700 | [diff] [blame] | 366 | 	depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 367 |  | 
 | 368 | config X86_OOSTORE | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 369 | 	def_bool y | 
| Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 370 | 	depends on (MWINCHIP3D || MWINCHIPC6) && MTRR | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 371 |  | 
| H. Peter Anvin | 959b3be | 2008-02-14 14:56:45 -0800 | [diff] [blame] | 372 | # | 
 | 373 | # P6_NOPs are a relatively minor optimization that require a family >= | 
 | 374 | # 6 processor, except that it is broken on certain VIA chips. | 
 | 375 | # Furthermore, AMD chips prefer a totally different sequence of NOPs | 
| Linus Torvalds | 14469a8 | 2008-09-05 09:30:14 -0700 | [diff] [blame] | 376 | # (which work on all CPUs).  In addition, it looks like Virtual PC | 
 | 377 | # does not understand them. | 
 | 378 | # | 
 | 379 | # As a result, disallow these if we're not compiling for X86_64 (these | 
 | 380 | # NOPs do work on all x86-64 capable chips); the list of processors in | 
 | 381 | # the right-hand clause are the cores that benefit from this optimization. | 
| H. Peter Anvin | 959b3be | 2008-02-14 14:56:45 -0800 | [diff] [blame] | 382 | # | 
| H. Peter Anvin | 7343b3b | 2008-02-14 14:52:05 -0800 | [diff] [blame] | 383 | config X86_P6_NOP | 
 | 384 | 	def_bool y | 
| Linus Torvalds | 14469a8 | 2008-09-05 09:30:14 -0700 | [diff] [blame] | 385 | 	depends on X86_64 | 
 | 386 | 	depends on (MCORE2 || MPENTIUM4 || MPSC) | 
| H. Peter Anvin | 7343b3b | 2008-02-14 14:52:05 -0800 | [diff] [blame] | 387 |  | 
| Paolo 'Blaisorblade' Giarrusso | 96d55b8 | 2005-10-30 15:00:07 -0800 | [diff] [blame] | 388 | config X86_TSC | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 389 | 	def_bool y | 
| Krzysztof Helt | 69d45dd | 2008-09-28 21:28:15 +0200 | [diff] [blame] | 390 | 	depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64 | 
| Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 391 |  | 
| Jan Beulich | f8096f9 | 2008-04-22 16:27:29 +0100 | [diff] [blame] | 392 | config X86_CMPXCHG64 | 
 | 393 | 	def_bool y | 
 | 394 | 	depends on X86_PAE || X86_64 | 
 | 395 |  | 
| Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 396 | # this should be set for all -march=.. options where the compiler | 
 | 397 | # generates cmov. | 
 | 398 | config X86_CMOV | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 399 | 	def_bool y | 
| Jan Beulich | 79aa10d | 2008-08-29 12:50:38 +0100 | [diff] [blame] | 400 | 	depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64) | 
| Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 401 |  | 
| H. Peter Anvin | de32e04 | 2007-07-11 12:18:30 -0700 | [diff] [blame] | 402 | config X86_MINIMUM_CPU_FAMILY | 
| Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 403 | 	int | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 404 | 	default "64" if X86_64 | 
| H. Peter Anvin | 7343b3b | 2008-02-14 14:52:05 -0800 | [diff] [blame] | 405 | 	default "6" if X86_32 && X86_P6_NOP | 
| Sam Ravnborg | 1032c0b | 2007-11-06 21:35:08 +0100 | [diff] [blame] | 406 | 	default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK) | 
| H. Peter Anvin | de32e04 | 2007-07-11 12:18:30 -0700 | [diff] [blame] | 407 | 	default "3" | 
| Andi Kleen | c7f81c9 | 2007-05-02 19:27:20 +0200 | [diff] [blame] | 408 |  | 
| Roland McGrath | 0a049bb | 2008-01-30 13:30:54 +0100 | [diff] [blame] | 409 | config X86_DEBUGCTLMSR | 
| Harvey Harrison | 96daa8c | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 410 | 	def_bool y | 
| Al Viro | 5641f1f | 2009-01-05 17:19:02 +0000 | [diff] [blame] | 411 | 	depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386) && !UML | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 412 |  | 
 | 413 | menuconfig PROCESSOR_SELECT | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 414 | 	bool "Supported processor vendors" if EMBEDDED | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 415 | 	---help--- | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 416 | 	  This lets you choose what x86 vendor support code your kernel | 
 | 417 | 	  will include. | 
 | 418 |  | 
| Yinghai Lu | 879d792 | 2008-09-09 16:40:37 -0700 | [diff] [blame] | 419 | config CPU_SUP_INTEL | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 420 | 	default y | 
 | 421 | 	bool "Support Intel processors" if PROCESSOR_SELECT | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 422 | 	---help--- | 
| Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 423 | 	  This enables detection, tunings and quirks for Intel processors | 
 | 424 |  | 
 | 425 | 	  You need this enabled if you want your kernel to run on an | 
 | 426 | 	  Intel CPU. Disabling this option on other types of CPUs | 
 | 427 | 	  makes the kernel a tiny bit smaller. Disabling it on an Intel | 
 | 428 | 	  CPU might render the kernel unbootable. | 
 | 429 |  | 
 | 430 | 	  If unsure, say N. | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 431 |  | 
 | 432 | config CPU_SUP_CYRIX_32 | 
 | 433 | 	default y | 
 | 434 | 	bool "Support Cyrix processors" if PROCESSOR_SELECT | 
 | 435 | 	depends on !64BIT | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 436 | 	---help--- | 
| Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 437 | 	  This enables detection, tunings and quirks for Cyrix processors | 
 | 438 |  | 
 | 439 | 	  You need this enabled if you want your kernel to run on a | 
 | 440 | 	  Cyrix CPU. Disabling this option on other types of CPUs | 
 | 441 | 	  makes the kernel a tiny bit smaller. Disabling it on a Cyrix | 
 | 442 | 	  CPU might render the kernel unbootable. | 
 | 443 |  | 
 | 444 | 	  If unsure, say N. | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 445 |  | 
| Yinghai Lu | ff73152 | 2008-09-07 17:58:56 -0700 | [diff] [blame] | 446 | config CPU_SUP_AMD | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 447 | 	default y | 
 | 448 | 	bool "Support AMD processors" if PROCESSOR_SELECT | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 449 | 	---help--- | 
| Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 450 | 	  This enables detection, tunings and quirks for AMD processors | 
 | 451 |  | 
 | 452 | 	  You need this enabled if you want your kernel to run on an | 
 | 453 | 	  AMD CPU. Disabling this option on other types of CPUs | 
 | 454 | 	  makes the kernel a tiny bit smaller. Disabling it on an AMD | 
 | 455 | 	  CPU might render the kernel unbootable. | 
 | 456 |  | 
 | 457 | 	  If unsure, say N. | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 458 |  | 
| Sebastian Andrzej Siewior | 48f4c48 | 2009-03-14 12:24:02 +0100 | [diff] [blame] | 459 | config CPU_SUP_CENTAUR | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 460 | 	default y | 
 | 461 | 	bool "Support Centaur processors" if PROCESSOR_SELECT | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 462 | 	---help--- | 
| Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 463 | 	  This enables detection, tunings and quirks for Centaur processors | 
 | 464 |  | 
 | 465 | 	  You need this enabled if you want your kernel to run on a | 
 | 466 | 	  Centaur CPU. Disabling this option on other types of CPUs | 
 | 467 | 	  makes the kernel a tiny bit smaller. Disabling it on a Centaur | 
 | 468 | 	  CPU might render the kernel unbootable. | 
 | 469 |  | 
 | 470 | 	  If unsure, say N. | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 471 |  | 
 | 472 | config CPU_SUP_TRANSMETA_32 | 
 | 473 | 	default y | 
 | 474 | 	bool "Support Transmeta processors" if PROCESSOR_SELECT | 
 | 475 | 	depends on !64BIT | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 476 | 	---help--- | 
| Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 477 | 	  This enables detection, tunings and quirks for Transmeta processors | 
 | 478 |  | 
 | 479 | 	  You need this enabled if you want your kernel to run on a | 
 | 480 | 	  Transmeta CPU. Disabling this option on other types of CPUs | 
 | 481 | 	  makes the kernel a tiny bit smaller. Disabling it on a Transmeta | 
 | 482 | 	  CPU might render the kernel unbootable. | 
 | 483 |  | 
 | 484 | 	  If unsure, say N. | 
| Thomas Petazzoni | 8d02c21 | 2008-08-05 11:45:19 +0200 | [diff] [blame] | 485 |  | 
 | 486 | config CPU_SUP_UMC_32 | 
 | 487 | 	default y | 
 | 488 | 	bool "Support UMC processors" if PROCESSOR_SELECT | 
 | 489 | 	depends on !64BIT | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 490 | 	---help--- | 
| Ingo Molnar | b7b3a42 | 2008-10-12 15:36:24 +0200 | [diff] [blame] | 491 | 	  This enables detection, tunings and quirks for UMC processors | 
 | 492 |  | 
 | 493 | 	  You need this enabled if you want your kernel to run on a | 
 | 494 | 	  UMC CPU. Disabling this option on other types of CPUs | 
 | 495 | 	  makes the kernel a tiny bit smaller. Disabling it on a UMC | 
 | 496 | 	  CPU might render the kernel unbootable. | 
 | 497 |  | 
 | 498 | 	  If unsure, say N. | 
| Ingo Molnar | 81faaae | 2008-09-10 08:20:51 +0200 | [diff] [blame] | 499 |  | 
| Markus Metzger | 93fa763 | 2008-04-08 11:01:58 +0200 | [diff] [blame] | 500 | config X86_DS | 
| Markus Metzger | 531f6ed | 2008-10-17 09:09:27 +0200 | [diff] [blame] | 501 | 	def_bool X86_PTRACE_BTS | 
 | 502 | 	depends on X86_DEBUGCTLMSR | 
| Markus Metzger | 1e9b51c | 2008-11-25 09:24:15 +0100 | [diff] [blame] | 503 | 	select HAVE_HW_BRANCH_TRACER | 
| Markus Metzger | 93fa763 | 2008-04-08 11:01:58 +0200 | [diff] [blame] | 504 |  | 
 | 505 | config X86_PTRACE_BTS | 
| Markus Metzger | 531f6ed | 2008-10-17 09:09:27 +0200 | [diff] [blame] | 506 | 	bool "Branch Trace Store" | 
| Markus Metzger | 93fa763 | 2008-04-08 11:01:58 +0200 | [diff] [blame] | 507 | 	default y | 
| Markus Metzger | 531f6ed | 2008-10-17 09:09:27 +0200 | [diff] [blame] | 508 | 	depends on X86_DEBUGCTLMSR | 
| Ingo Molnar | d45b41a | 2009-04-15 23:15:14 +0200 | [diff] [blame] | 509 | 	depends on BROKEN | 
| Ingo Molnar | 8f9ca47 | 2009-02-05 16:21:53 +0100 | [diff] [blame] | 510 | 	---help--- | 
| Markus Metzger | 531f6ed | 2008-10-17 09:09:27 +0200 | [diff] [blame] | 511 | 	  This adds a ptrace interface to the hardware's branch trace store. | 
 | 512 |  | 
 | 513 | 	  Debuggers may use it to collect an execution trace of the debugged | 
 | 514 | 	  application in order to answer the question 'how did I get here?'. | 
 | 515 | 	  Debuggers may trace user mode as well as kernel mode. | 
 | 516 |  | 
 | 517 | 	  Say Y unless there is no application development on this machine | 
 | 518 | 	  and you want to save a small amount of code size. |