Blame - drivers/scsi/qla2xxx/qla_dbg.c - android_kernel_oneplus_msm8996

blob: 74a2121783c9cfcc7f4afbd5d34438969a5707e0 [file] [log] [blame]

Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	2	* QLogic Fibre Channel HBA Driver
Saurav Kashyap	1e63395	2013-02-08 01:57:54 -0500	[diff] [blame]	3	* Copyright (c) 2003-2013 QLogic Corporation
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	5	* See LICENSE.qla2xxx for copyright and licensing details.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	7
				8	/*
				9	* Table for showing the current message id in use for particular level
				10	* Change this table for addition of log/debug messages.
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	11	* ----------------------------------------------------------------------
				12	* \| Level \| Last Value Used \| Holes \|
				13	* ----------------------------------------------------------------------
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	14	* \| Module Init and Probe \| 0x014f \| 0x4b,0xba,0xfa \|
Giridhar Malavali	754d124	2013-06-25 11:27:16 -0400	[diff] [blame]	15	* \| Mailbox commands \| 0x117a \| 0x111a-0x111b \|
Joe Carnuccio	e9f4f41	2013-03-25 02:21:36 -0400	[diff] [blame]	16	* \| \| \| 0x1155-0x1158 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	17	* \| Device Discovery \| 0x2095 \| 0x2020-0x2022, \|
Saurav Kashyap	2a8593f	2012-08-22 14:21:27 -0400	[diff] [blame]	18	* \| \| \| 0x2016 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	19	* \| Queue Command and IO tracing \| 0x3058 \| 0x3006-0x300b \|
Arun Easi	9e522cd	2012-08-22 14:21:31 -0400	[diff] [blame]	20	* \| \| \| 0x3027-0x3028 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	21	* \| \| \| 0x303d-0x3041 \|
				22	* \| \| \| 0x302d,0x3033 \|
				23	* \| \| \| 0x3036,0x3038 \|
				24	* \| \| \| 0x303a \|
				25	* \| DPC Thread \| 0x4022 \| 0x4002,0x4013 \|
				26	* \| Async Events \| 0x5081 \| 0x502b-0x502f \|
Giridhar Malavali	9ba56b9	2012-02-09 11:15:36 -0800	[diff] [blame]	27	* \| \| \| 0x5047,0x5052 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	28	* \| \| \| 0x5040,0x5075 \|
Giridhar Malavali	5988aeb	2012-05-15 14:34:12 -0400	[diff] [blame]	29	* \| Timer Routines \| 0x6011 \| \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	30	* \| User Space Interactions \| 0x70dd \| 0x7018,0x702e, \|
Saurav Kashyap	78d56df	2013-01-30 03:34:42 -0500	[diff] [blame]	31	* \| \| \| 0x7020,0x7024, \|
Joe Carnuccio	733a95b	2012-02-09 11:15:55 -0800	[diff] [blame]	32	* \| \| \| 0x7039,0x7045, \|
				33	* \| \| \| 0x7073-0x7075, \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	34	* \| \| \| 0x707b,0x708c, \|
Saurav Kashyap	a9b6f72	2012-08-22 14:21:01 -0400	[diff] [blame]	35	* \| \| \| 0x70a5,0x70a6, \|
				36	* \| \| \| 0x70a8,0x70ab, \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	37	* \| \| \| 0x70ad-0x70ae, \|
Bart Van Assche	090fc2e	2013-06-25 11:27:22 -0400	[diff] [blame]	38	* \| \| \| 0x70d1-0x70da, \|
Bart Van Assche	a44c72f	2013-06-25 11:27:23 -0400	[diff] [blame^]	39	* \| \| \| 0x7047,0x703b \|
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	40	* \| Task Management \| 0x803c \| 0x8025-0x8026 \|
				41	* \| \| \| 0x800b,0x8039 \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	42	* \| AER/EEH \| 0x9011 \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	43	* \| Virtual Port \| 0xa007 \| \|
Saurav Kashyap	6c31555	2013-02-08 01:57:53 -0500	[diff] [blame]	44	* \| ISP82XX Specific \| 0xb086 \| 0xb002,0xb024 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	45	* \| MultiQ \| 0xc00c \| \|
				46	* \| Misc \| 0xd010 \| \|
Arun Easi	33c36c0	2013-01-30 03:34:41 -0500	[diff] [blame]	47	* \| Target Mode \| 0xe070 \| \|
Arun Easi	aa230bc	2013-01-30 03:34:39 -0500	[diff] [blame]	48	* \| Target Mode Management \| 0xf072 \| \|
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	49	* \| Target Mode Task Management \| 0x1000b \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	50	* ----------------------------------------------------------------------
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	51	*/
				52
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	53	#include "qla_def.h"
				54
				55	#include <linux/delay.h>
				56
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	57	static uint32_t ql_dbg_offset = 0x800;
				58
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	59	static inline void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	60	qla2xxx_prep_dump(struct qla_hw_data ha, struct qla2xxx_fw_dump fw_dump)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	61	{
				62	fw_dump->fw_major_version = htonl(ha->fw_major_version);
				63	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
				64	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
				65	fw_dump->fw_attributes = htonl(ha->fw_attributes);
				66
				67	fw_dump->vendor = htonl(ha->pdev->vendor);
				68	fw_dump->device = htonl(ha->pdev->device);
				69	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
				70	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
				71	}
				72
				73	static inline void *
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	74	qla2xxx_copy_queues(struct qla_hw_data ha, void ptr)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	75	{
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	76	struct req_que *req = ha->req_q_map[0];
				77	struct rsp_que *rsp = ha->rsp_q_map[0];
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	78	/* Request queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	79	memcpy(ptr, req->ring, req->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	80	sizeof(request_t));
				81
				82	/* Response queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	83	ptr += req->length * sizeof(request_t);
				84	memcpy(ptr, rsp->ring, rsp->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	85	sizeof(response_t));
				86
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	87	return ptr + (rsp->length * sizeof(response_t));
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	88	}
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	89
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	90	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	91	qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	92	uint32_t ram_dwords, void **nxt)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	93	{
				94	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	95	uint32_t cnt, stat, timer, dwords, idx;
				96	uint16_t mb0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	97	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	98	dma_addr_t dump_dma = ha->gid_list_dma;
				99	uint32_t dump = (uint32_t )ha->gid_list;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	100
				101	rval = QLA_SUCCESS;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	102	mb0 = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	103
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	104	WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	105	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				106
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	107	dwords = qla2x00_gid_list_size(ha) / 4;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	108	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				109	cnt += dwords, addr += dwords) {
				110	if (cnt + dwords > ram_dwords)
				111	dwords = ram_dwords - cnt;
				112
				113	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				114	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				115
				116	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				117	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				118	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				119	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				120
				121	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				122	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	123	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				124
				125	for (timer = 6000000; timer; timer--) {
				126	/* Check for pending interrupts. */
				127	stat = RD_REG_DWORD(&reg->host_status);
				128	if (stat & HSRX_RISC_INT) {
				129	stat &= 0xff;
				130
				131	if (stat == 0x1 \|\| stat == 0x2 \|\|
				132	stat == 0x10 \|\| stat == 0x11) {
				133	set_bit(MBX_INTERRUPT,
				134	&ha->mbx_cmd_flags);
				135
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	136	mb0 = RD_REG_WORD(&reg->mailbox0);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	137
				138	WRT_REG_DWORD(&reg->hccr,
				139	HCCRX_CLR_RISC_INT);
				140	RD_REG_DWORD(&reg->hccr);
				141	break;
				142	}
				143
				144	/* Clear this intr; it wasn't a mailbox intr */
				145	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				146	RD_REG_DWORD(&reg->hccr);
				147	}
				148	udelay(5);
				149	}
				150
				151	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	152	rval = mb0 & MBS_MASK;
				153	for (idx = 0; idx < dwords; idx++)
				154	ram[cnt + idx] = swab32(dump[idx]);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	155	} else {
				156	rval = QLA_FUNCTION_FAILED;
				157	}
				158	}
				159
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	160	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	161	return rval;
				162	}
				163
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	164	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	165	qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	166	uint32_t cram_size, void **nxt)
				167	{
				168	int rval;
				169
				170	/* Code RAM. */
				171	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
				172	if (rval != QLA_SUCCESS)
				173	return rval;
				174
				175	/* External Memory. */
				176	return qla24xx_dump_ram(ha, 0x100000, *nxt,
				177	ha->fw_memory_size - 0x100000 + 1, nxt);
				178	}
				179
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	180	static uint32_t *
				181	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
				182	uint32_t count, uint32_t *buf)
				183	{
				184	uint32_t __iomem *dmp_reg;
				185
				186	WRT_REG_DWORD(&reg->iobase_addr, iobase);
				187	dmp_reg = &reg->iobase_window;
				188	while (count--)
				189	*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
				190
				191	return buf;
				192	}
				193
				194	static inline int
				195	qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
				196	{
				197	int rval = QLA_SUCCESS;
				198	uint32_t cnt;
				199
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	200	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
Andrew Vasquez	aed1088	2009-06-03 09:55:26 -0700	[diff] [blame]	201	for (cnt = 30000;
				202	((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	203	rval == QLA_SUCCESS; cnt--) {
				204	if (cnt)
				205	udelay(100);
				206	else
				207	rval = QLA_FUNCTION_TIMEOUT;
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	208	}
				209
				210	return rval;
				211	}
				212
				213	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	214	qla24xx_soft_reset(struct qla_hw_data *ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	215	{
				216	int rval = QLA_SUCCESS;
				217	uint32_t cnt;
				218	uint16_t mb0, wd;
				219	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				220
				221	/* Reset RISC. */
				222	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				223	for (cnt = 0; cnt < 30000; cnt++) {
				224	if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
				225	break;
				226
				227	udelay(10);
				228	}
				229
				230	WRT_REG_DWORD(&reg->ctrl_status,
				231	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				232	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
				233
				234	udelay(100);
				235	/* Wait for firmware to complete NVRAM accesses. */
				236	mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
				237	for (cnt = 10000 ; cnt && mb0; cnt--) {
				238	udelay(5);
				239	mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
				240	barrier();
				241	}
				242
				243	/* Wait for soft-reset to complete. */
				244	for (cnt = 0; cnt < 30000; cnt++) {
				245	if ((RD_REG_DWORD(&reg->ctrl_status) &
				246	CSRX_ISP_SOFT_RESET) == 0)
				247	break;
				248
				249	udelay(10);
				250	}
				251	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				252	RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
				253
				254	for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
				255	rval == QLA_SUCCESS; cnt--) {
				256	if (cnt)
				257	udelay(100);
				258	else
				259	rval = QLA_FUNCTION_TIMEOUT;
				260	}
				261
				262	return rval;
				263	}
				264
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	265	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	266	qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
Andrew Vasquez	e18e963	2009-06-17 10:30:31 -0700	[diff] [blame]	267	uint32_t ram_words, void **nxt)
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	268	{
				269	int rval;
				270	uint32_t cnt, stat, timer, words, idx;
				271	uint16_t mb0;
				272	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				273	dma_addr_t dump_dma = ha->gid_list_dma;
				274	uint16_t dump = (uint16_t )ha->gid_list;
				275
				276	rval = QLA_SUCCESS;
				277	mb0 = 0;
				278
				279	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
				280	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				281
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	282	words = qla2x00_gid_list_size(ha) / 2;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	283	for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
				284	cnt += words, addr += words) {
				285	if (cnt + words > ram_words)
				286	words = ram_words - cnt;
				287
				288	WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
				289	WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
				290
				291	WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
				292	WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
				293	WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
				294	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
				295
				296	WRT_MAILBOX_REG(ha, reg, 4, words);
				297	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				298
				299	for (timer = 6000000; timer; timer--) {
				300	/* Check for pending interrupts. */
				301	stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
				302	if (stat & HSR_RISC_INT) {
				303	stat &= 0xff;
				304
				305	if (stat == 0x1 \|\| stat == 0x2) {
				306	set_bit(MBX_INTERRUPT,
				307	&ha->mbx_cmd_flags);
				308
				309	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				310
				311	/* Release mailbox registers. */
				312	WRT_REG_WORD(&reg->semaphore, 0);
				313	WRT_REG_WORD(&reg->hccr,
				314	HCCR_CLR_RISC_INT);
				315	RD_REG_WORD(&reg->hccr);
				316	break;
				317	} else if (stat == 0x10 \|\| stat == 0x11) {
				318	set_bit(MBX_INTERRUPT,
				319	&ha->mbx_cmd_flags);
				320
				321	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				322
				323	WRT_REG_WORD(&reg->hccr,
				324	HCCR_CLR_RISC_INT);
				325	RD_REG_WORD(&reg->hccr);
				326	break;
				327	}
				328
				329	/* clear this intr; it wasn't a mailbox intr */
				330	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				331	RD_REG_WORD(&reg->hccr);
				332	}
				333	udelay(5);
				334	}
				335
				336	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				337	rval = mb0 & MBS_MASK;
				338	for (idx = 0; idx < words; idx++)
				339	ram[cnt + idx] = swab16(dump[idx]);
				340	} else {
				341	rval = QLA_FUNCTION_FAILED;
				342	}
				343	}
				344
				345	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
				346	return rval;
				347	}
				348
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	349	static inline void
				350	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
				351	uint16_t *buf)
				352	{
				353	uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
				354
				355	while (count--)
				356	*buf++ = htons(RD_REG_WORD(dmp_reg++));
				357	}
				358
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	359	static inline void *
				360	qla24xx_copy_eft(struct qla_hw_data ha, void ptr)
				361	{
				362	if (!ha->eft)
				363	return ptr;
				364
				365	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
				366	return ptr + ntohl(ha->fw_dump->eft_size);
				367	}
				368
				369	static inline void *
				370	qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				371	{
				372	uint32_t cnt;
				373	uint32_t *iter_reg;
				374	struct qla2xxx_fce_chain *fcec = ptr;
				375
				376	if (!ha->fce)
				377	return ptr;
				378
				379	*last_chain = &fcec->type;
				380	fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
				381	fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
				382	fce_calc_size(ha->fce_bufs));
				383	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
				384	fcec->addr_l = htonl(LSD(ha->fce_dma));
				385	fcec->addr_h = htonl(MSD(ha->fce_dma));
				386
				387	iter_reg = fcec->eregs;
				388	for (cnt = 0; cnt < 8; cnt++)
				389	*iter_reg++ = htonl(ha->fce_mb[cnt]);
				390
				391	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
				392
Giridhar Malavali	3cb0a67	2011-11-18 09:03:11 -0800	[diff] [blame]	393	return (char *)iter_reg + ntohl(fcec->size);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	394	}
				395
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	396	static inline void *
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	397	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
				398	uint32_t **last_chain)
				399	{
				400	struct qla2xxx_mqueue_chain *q;
				401	struct qla2xxx_mqueue_header *qh;
				402	uint32_t num_queues;
				403	int que;
				404	struct {
				405	int length;
				406	void *ring;
				407	} aq, *aqp;
				408
Arun Easi	00876ae8	2013-03-25 02:21:37 -0400	[diff] [blame]	409	if (!ha->tgt.atio_ring)
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	410	return ptr;
				411
				412	num_queues = 1;
				413	aqp = &aq;
				414	aqp->length = ha->tgt.atio_q_length;
				415	aqp->ring = ha->tgt.atio_ring;
				416
				417	for (que = 0; que < num_queues; que++) {
				418	/* aqp = ha->atio_q_map[que]; */
				419	q = ptr;
				420	*last_chain = &q->type;
				421	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				422	q->chain_size = htonl(
				423	sizeof(struct qla2xxx_mqueue_chain) +
				424	sizeof(struct qla2xxx_mqueue_header) +
				425	(aqp->length * sizeof(request_t)));
				426	ptr += sizeof(struct qla2xxx_mqueue_chain);
				427
				428	/* Add header. */
				429	qh = ptr;
				430	qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
				431	qh->number = htonl(que);
				432	qh->size = htonl(aqp->length * sizeof(request_t));
				433	ptr += sizeof(struct qla2xxx_mqueue_header);
				434
				435	/* Add data. */
				436	memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
				437
				438	ptr += aqp->length * sizeof(request_t);
				439	}
				440
				441	return ptr;
				442	}
				443
				444	static inline void *
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	445	qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				446	{
				447	struct qla2xxx_mqueue_chain *q;
				448	struct qla2xxx_mqueue_header *qh;
				449	struct req_que *req;
				450	struct rsp_que *rsp;
				451	int que;
				452
				453	if (!ha->mqenable)
				454	return ptr;
				455
				456	/* Request queues */
				457	for (que = 1; que < ha->max_req_queues; que++) {
				458	req = ha->req_q_map[que];
				459	if (!req)
				460	break;
				461
				462	/* Add chain. */
				463	q = ptr;
				464	*last_chain = &q->type;
				465	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				466	q->chain_size = htonl(
				467	sizeof(struct qla2xxx_mqueue_chain) +
				468	sizeof(struct qla2xxx_mqueue_header) +
				469	(req->length * sizeof(request_t)));
				470	ptr += sizeof(struct qla2xxx_mqueue_chain);
				471
				472	/* Add header. */
				473	qh = ptr;
				474	qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
				475	qh->number = htonl(que);
				476	qh->size = htonl(req->length * sizeof(request_t));
				477	ptr += sizeof(struct qla2xxx_mqueue_header);
				478
				479	/* Add data. */
				480	memcpy(ptr, req->ring, req->length * sizeof(request_t));
				481	ptr += req->length * sizeof(request_t);
				482	}
				483
				484	/* Response queues */
				485	for (que = 1; que < ha->max_rsp_queues; que++) {
				486	rsp = ha->rsp_q_map[que];
				487	if (!rsp)
				488	break;
				489
				490	/* Add chain. */
				491	q = ptr;
				492	*last_chain = &q->type;
				493	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				494	q->chain_size = htonl(
				495	sizeof(struct qla2xxx_mqueue_chain) +
				496	sizeof(struct qla2xxx_mqueue_header) +
				497	(rsp->length * sizeof(response_t)));
				498	ptr += sizeof(struct qla2xxx_mqueue_chain);
				499
				500	/* Add header. */
				501	qh = ptr;
				502	qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
				503	qh->number = htonl(que);
				504	qh->size = htonl(rsp->length * sizeof(response_t));
				505	ptr += sizeof(struct qla2xxx_mqueue_header);
				506
				507	/* Add data. */
				508	memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
				509	ptr += rsp->length * sizeof(response_t);
				510	}
				511
				512	return ptr;
				513	}
				514
				515	static inline void *
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	516	qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				517	{
				518	uint32_t cnt, que_idx;
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	519	uint8_t que_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	520	struct qla2xxx_mq_chain *mq = ptr;
				521	struct device_reg_25xxmq __iomem *reg;
				522
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	523	if (!ha->mqenable \|\| IS_QLA83XX(ha))
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	524	return ptr;
				525
				526	mq = ptr;
				527	*last_chain = &mq->type;
				528	mq->type = __constant_htonl(DUMP_CHAIN_MQ);
				529	mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
				530
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	531	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
				532	ha->max_req_queues : ha->max_rsp_queues;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	533	mq->count = htonl(que_cnt);
				534	for (cnt = 0; cnt < que_cnt; cnt++) {
Saurav Kashyap	fa49263	2012-11-21 02:40:29 -0500	[diff] [blame]	535	reg = (struct device_reg_25xxmq __iomem *)
				536	(ha->mqiobase + cnt * QLA_QUE_PAGE);
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	537	que_idx = cnt * 4;
				538	mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
				539	mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
				540	mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
				541	mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
				542	}
				543
				544	return ptr + sizeof(struct qla2xxx_mq_chain);
				545	}
				546
Giridhar Malavali	08de284	2011-08-16 11:31:44 -0700	[diff] [blame]	547	void
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	548	qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
				549	{
				550	struct qla_hw_data *ha = vha->hw;
				551
				552	if (rval != QLA_SUCCESS) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	553	ql_log(ql_log_warn, vha, 0xd000,
				554	"Failed to dump firmware (%x).\n", rval);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	555	ha->fw_dumped = 0;
				556	} else {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	557	ql_log(ql_log_info, vha, 0xd001,
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	558	"Firmware dump saved to temp buffer (%ld/%p).\n",
				559	vha->host_no, ha->fw_dump);
				560	ha->fw_dumped = 1;
				561	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
				562	}
				563	}
				564
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	565	/**
				566	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
				567	* @ha: HA context
				568	* @hardware_locked: Called with the hardware_lock
				569	*/
				570	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	571	qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	572	{
				573	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	574	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	575	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	576	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	577	uint16_t __iomem *dmp_reg;
				578	unsigned long flags;
				579	struct qla2300_fw_dump *fw;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	580	void *nxt;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	581	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	582
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	583	flags = 0;
				584
				585	if (!hardware_locked)
				586	spin_lock_irqsave(&ha->hardware_lock, flags);
				587
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	588	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	589	ql_log(ql_log_warn, vha, 0xd002,
				590	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	591	goto qla2300_fw_dump_failed;
				592	}
				593
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	594	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	595	ql_log(ql_log_warn, vha, 0xd003,
				596	"Firmware has been previously dumped (%p) "
				597	"-- ignoring request.\n",
				598	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	599	goto qla2300_fw_dump_failed;
				600	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	601	fw = &ha->fw_dump->isp.isp23;
				602	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	603
				604	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	605	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	606
				607	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	608	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	609	if (IS_QLA2300(ha)) {
				610	for (cnt = 30000;
				611	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				612	rval == QLA_SUCCESS; cnt--) {
				613	if (cnt)
				614	udelay(100);
				615	else
				616	rval = QLA_FUNCTION_TIMEOUT;
				617	}
				618	} else {
				619	RD_REG_WORD(&reg->hccr); /* PCI Posting. */
				620	udelay(10);
				621	}
				622
				623	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	624	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	625	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	626	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	627
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	628	dmp_reg = &reg->u.isp2300.req_q_in;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	629	for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	630	fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	631
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	632	dmp_reg = &reg->u.isp2300.mailbox0;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	633	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	634	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	635
				636	WRT_REG_WORD(&reg->ctrl_status, 0x40);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	637	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	638
				639	WRT_REG_WORD(&reg->ctrl_status, 0x50);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	640	qla2xxx_read_window(reg, 48, fw->dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	641
				642	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	643	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	644	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	645	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	646
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	647	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	648	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	649
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	650	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	651	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	652
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	653	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	654	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	655
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	656	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	657	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	658
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	659	WRT_REG_WORD(&reg->pcr, 0x2800);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	660	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	661
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	662	WRT_REG_WORD(&reg->pcr, 0x2A00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	663	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	664
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	665	WRT_REG_WORD(&reg->pcr, 0x2C00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	666	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	667
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	668	WRT_REG_WORD(&reg->pcr, 0x2E00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	669	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	670
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	671	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	672	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	673
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	674	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	675	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	676
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	677	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	678	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	679
				680	/* Reset RISC. */
				681	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				682	for (cnt = 0; cnt < 30000; cnt++) {
				683	if ((RD_REG_WORD(&reg->ctrl_status) &
				684	CSR_ISP_SOFT_RESET) == 0)
				685	break;
				686
				687	udelay(10);
				688	}
				689	}
				690
				691	if (!IS_QLA2300(ha)) {
				692	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				693	rval == QLA_SUCCESS; cnt--) {
				694	if (cnt)
				695	udelay(100);
				696	else
				697	rval = QLA_FUNCTION_TIMEOUT;
				698	}
				699	}
				700
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	701	/* Get RISC SRAM. */
				702	if (rval == QLA_SUCCESS)
				703	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
				704	sizeof(fw->risc_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	705
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	706	/* Get stack SRAM. */
				707	if (rval == QLA_SUCCESS)
				708	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
				709	sizeof(fw->stack_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	710
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	711	/* Get data SRAM. */
				712	if (rval == QLA_SUCCESS)
				713	rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
				714	ha->fw_memory_size - 0x11000 + 1, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	715
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	716	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	717	qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	718
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	719	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	720
				721	qla2300_fw_dump_failed:
				722	if (!hardware_locked)
				723	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				724	}
				725
				726	/**
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	727	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
				728	* @ha: HA context
				729	* @hardware_locked: Called with the hardware_lock
				730	*/
				731	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	732	qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	733	{
				734	int rval;
				735	uint32_t cnt, timer;
				736	uint16_t risc_address;
				737	uint16_t mb0, mb2;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	738	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	739	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	740	uint16_t __iomem *dmp_reg;
				741	unsigned long flags;
				742	struct qla2100_fw_dump *fw;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	743	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	744
				745	risc_address = 0;
				746	mb0 = mb2 = 0;
				747	flags = 0;
				748
				749	if (!hardware_locked)
				750	spin_lock_irqsave(&ha->hardware_lock, flags);
				751
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	752	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	753	ql_log(ql_log_warn, vha, 0xd004,
				754	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	755	goto qla2100_fw_dump_failed;
				756	}
				757
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	758	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	759	ql_log(ql_log_warn, vha, 0xd005,
				760	"Firmware has been previously dumped (%p) "
				761	"-- ignoring request.\n",
				762	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	763	goto qla2100_fw_dump_failed;
				764	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	765	fw = &ha->fw_dump->isp.isp21;
				766	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	767
				768	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	769	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	770
				771	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	772	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	773	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				774	rval == QLA_SUCCESS; cnt--) {
				775	if (cnt)
				776	udelay(100);
				777	else
				778	rval = QLA_FUNCTION_TIMEOUT;
				779	}
				780	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	781	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	782	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	783	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	784
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	785	dmp_reg = &reg->u.isp2100.mailbox0;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	786	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	787	if (cnt == 8)
				788	dmp_reg = &reg->u_end.isp2200.mailbox8;
				789
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	790	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	791	}
				792
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	793	dmp_reg = &reg->u.isp2100.unused_2[0];
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	794	for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	795	fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	796
				797	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	798	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	799	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	800	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	801
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	802	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	803	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	804
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	805	WRT_REG_WORD(&reg->pcr, 0x2100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	806	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	807
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	808	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	809	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	810
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	811	WRT_REG_WORD(&reg->pcr, 0x2300);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	812	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	813
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	814	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	815	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	816
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	817	WRT_REG_WORD(&reg->pcr, 0x2500);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	818	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	819
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	820	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	821	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	822
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	823	WRT_REG_WORD(&reg->pcr, 0x2700);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	824	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	825
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	826	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	827	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	828
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	829	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	830	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	831
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	832	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	833	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	834
				835	/* Reset the ISP. */
				836	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				837	}
				838
				839	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				840	rval == QLA_SUCCESS; cnt--) {
				841	if (cnt)
				842	udelay(100);
				843	else
				844	rval = QLA_FUNCTION_TIMEOUT;
				845	}
				846
				847	/* Pause RISC. */
				848	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
				849	(RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
				850
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	851	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	852	for (cnt = 30000;
				853	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				854	rval == QLA_SUCCESS; cnt--) {
				855	if (cnt)
				856	udelay(100);
				857	else
				858	rval = QLA_FUNCTION_TIMEOUT;
				859	}
				860	if (rval == QLA_SUCCESS) {
				861	/* Set memory configuration and timing. */
				862	if (IS_QLA2100(ha))
				863	WRT_REG_WORD(&reg->mctr, 0xf1);
				864	else
				865	WRT_REG_WORD(&reg->mctr, 0xf2);
				866	RD_REG_WORD(&reg->mctr); /* PCI Posting. */
				867
				868	/* Release RISC. */
				869	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
				870	}
				871	}
				872
				873	if (rval == QLA_SUCCESS) {
				874	/* Get RISC SRAM. */
				875	risc_address = 0x1000;
				876	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
				877	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				878	}
				879	for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
				880	cnt++, risc_address++) {
				881	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
				882	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				883
				884	for (timer = 6000000; timer != 0; timer--) {
				885	/* Check for pending interrupts. */
				886	if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
				887	if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
				888	set_bit(MBX_INTERRUPT,
				889	&ha->mbx_cmd_flags);
				890
				891	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				892	mb2 = RD_MAILBOX_REG(ha, reg, 2);
				893
				894	WRT_REG_WORD(&reg->semaphore, 0);
				895	WRT_REG_WORD(&reg->hccr,
				896	HCCR_CLR_RISC_INT);
				897	RD_REG_WORD(&reg->hccr);
				898	break;
				899	}
				900	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				901	RD_REG_WORD(&reg->hccr);
				902	}
				903	udelay(5);
				904	}
				905
				906	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				907	rval = mb0 & MBS_MASK;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	908	fw->risc_ram[cnt] = htons(mb2);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	909	} else {
				910	rval = QLA_FUNCTION_FAILED;
				911	}
				912	}
				913
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	914	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	915	qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	916
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	917	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	918
				919	qla2100_fw_dump_failed:
				920	if (!hardware_locked)
				921	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				922	}
				923
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	924	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	925	qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	926	{
				927	int rval;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	928	uint32_t cnt;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	929	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	930	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	931	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				932	uint32_t __iomem *dmp_reg;
				933	uint32_t *iter_reg;
				934	uint16_t __iomem *mbx_reg;
				935	unsigned long flags;
				936	struct qla24xx_fw_dump *fw;
				937	uint32_t ext_mem_cnt;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	938	void *nxt;
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	939	void *nxt_chain;
				940	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	941	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	942
Giridhar Malavali	a908301	2010-04-12 17:59:55 -0700	[diff] [blame]	943	if (IS_QLA82XX(ha))
				944	return;
				945
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	946	risc_address = ext_mem_cnt = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	947	flags = 0;
				948
				949	if (!hardware_locked)
				950	spin_lock_irqsave(&ha->hardware_lock, flags);
				951
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	952	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	953	ql_log(ql_log_warn, vha, 0xd006,
				954	"No buffer available for dump.\n");
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	955	goto qla24xx_fw_dump_failed;
				956	}
				957
				958	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	959	ql_log(ql_log_warn, vha, 0xd007,
				960	"Firmware has been previously dumped (%p) "
				961	"-- ignoring request.\n",
				962	ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	963	goto qla24xx_fw_dump_failed;
				964	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	965	fw = &ha->fw_dump->isp.isp24;
				966	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	967
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	968	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	969
				970	/* Pause RISC. */
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	971	rval = qla24xx_pause_risc(reg);
				972	if (rval != QLA_SUCCESS)
				973	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	974
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	975	/* Host interface registers. */
				976	dmp_reg = &reg->flash_addr;
				977	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				978	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	979
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	980	/* Disable interrupts. */
				981	WRT_REG_DWORD(&reg->ictrl, 0);
				982	RD_REG_DWORD(&reg->ictrl);
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	983
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	984	/* Shadow registers. */
				985	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				986	RD_REG_DWORD(&reg->iobase_addr);
				987	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				988	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	989
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	990	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				991	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	992
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	993	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				994	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	995
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	996	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				997	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	998
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	999	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1000	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1001
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1002	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1003	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1004
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1005	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1006	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1007
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1008	/* Mailbox registers. */
				1009	mbx_reg = &reg->mailbox0;
				1010	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1011	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1012
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1013	/* Transfer sequence registers. */
				1014	iter_reg = fw->xseq_gp_reg;
				1015	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1016	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1017	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1018	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1019	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1020	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1021	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1022	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1023
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1024	qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
				1025	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1026
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1027	/* Receive sequence registers. */
				1028	iter_reg = fw->rseq_gp_reg;
				1029	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1030	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1031	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1032	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1033	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1034	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1035	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1036	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1037
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1038	qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
				1039	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1040	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1041
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1042	/* Command DMA registers. */
				1043	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1044
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1045	/* Queues. */
				1046	iter_reg = fw->req0_dma_reg;
				1047	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1048	dmp_reg = &reg->iobase_q;
				1049	for (cnt = 0; cnt < 7; cnt++)
				1050	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1051
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1052	iter_reg = fw->resp0_dma_reg;
				1053	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1054	dmp_reg = &reg->iobase_q;
				1055	for (cnt = 0; cnt < 7; cnt++)
				1056	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1057
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1058	iter_reg = fw->req1_dma_reg;
				1059	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1060	dmp_reg = &reg->iobase_q;
				1061	for (cnt = 0; cnt < 7; cnt++)
				1062	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1063
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1064	/* Transmit DMA registers. */
				1065	iter_reg = fw->xmt0_dma_reg;
				1066	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1067	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1068
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1069	iter_reg = fw->xmt1_dma_reg;
				1070	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1071	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1072
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1073	iter_reg = fw->xmt2_dma_reg;
				1074	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1075	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1076
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1077	iter_reg = fw->xmt3_dma_reg;
				1078	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1079	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1080
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1081	iter_reg = fw->xmt4_dma_reg;
				1082	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1083	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1084
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1085	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1086
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1087	/* Receive DMA registers. */
				1088	iter_reg = fw->rcvt0_data_dma_reg;
				1089	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1090	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1091
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1092	iter_reg = fw->rcvt1_data_dma_reg;
				1093	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1094	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1095
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1096	/* RISC registers. */
				1097	iter_reg = fw->risc_gp_reg;
				1098	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1099	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1100	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1101	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1102	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1103	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1104	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1105	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1106
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1107	/* Local memory controller registers. */
				1108	iter_reg = fw->lmc_reg;
				1109	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1110	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1111	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1112	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1113	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1114	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1115	qla24xx_read_window(reg, 0x3060, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1116
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1117	/* Fibre Protocol Module registers. */
				1118	iter_reg = fw->fpm_hdw_reg;
				1119	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1120	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1121	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1122	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1123	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1124	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1125	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1126	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1127	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1128	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1129	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1130	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1131
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1132	/* Frame Buffer registers. */
				1133	iter_reg = fw->fb_hdw_reg;
				1134	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1135	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1136	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1137	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1138	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1139	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1140	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1141	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1142	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1143	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1144	qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1145
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1146	rval = qla24xx_soft_reset(ha);
				1147	if (rval != QLA_SUCCESS)
				1148	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1149
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1150	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1151	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1152	if (rval != QLA_SUCCESS)
				1153	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1154
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1155	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1156
				1157	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1158
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1159	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
				1160	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
				1161	if (last_chain) {
				1162	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1163	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1164	}
				1165
				1166	/* Adjust valid length. */
				1167	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1168
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1169	qla24xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1170	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1171
				1172	qla24xx_fw_dump_failed:
				1173	if (!hardware_locked)
				1174	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1175	}
				1176
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1177	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1178	qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1179	{
				1180	int rval;
				1181	uint32_t cnt;
				1182	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1183	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1184	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1185	uint32_t __iomem *dmp_reg;
				1186	uint32_t *iter_reg;
				1187	uint16_t __iomem *mbx_reg;
				1188	unsigned long flags;
				1189	struct qla25xx_fw_dump *fw;
				1190	uint32_t ext_mem_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1191	void nxt, nxt_chain;
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1192	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1193	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1194
				1195	risc_address = ext_mem_cnt = 0;
				1196	flags = 0;
				1197
				1198	if (!hardware_locked)
				1199	spin_lock_irqsave(&ha->hardware_lock, flags);
				1200
				1201	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1202	ql_log(ql_log_warn, vha, 0xd008,
				1203	"No buffer available for dump.\n");
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1204	goto qla25xx_fw_dump_failed;
				1205	}
				1206
				1207	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1208	ql_log(ql_log_warn, vha, 0xd009,
				1209	"Firmware has been previously dumped (%p) "
				1210	"-- ignoring request.\n",
				1211	ha->fw_dump);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1212	goto qla25xx_fw_dump_failed;
				1213	}
				1214	fw = &ha->fw_dump->isp.isp25;
				1215	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1216	ha->fw_dump->version = __constant_htonl(2);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1217
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1218	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1219
				1220	/* Pause RISC. */
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1221	rval = qla24xx_pause_risc(reg);
				1222	if (rval != QLA_SUCCESS)
				1223	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1224
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1225	/* Host/Risc registers. */
				1226	iter_reg = fw->host_risc_reg;
				1227	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1228	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1229
				1230	/* PCIe registers. */
				1231	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1232	RD_REG_DWORD(&reg->iobase_addr);
				1233	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1234	dmp_reg = &reg->iobase_c4;
				1235	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1236	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1237	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1238	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1239
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1240	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1241	RD_REG_DWORD(&reg->iobase_window);
				1242
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1243	/* Host interface registers. */
				1244	dmp_reg = &reg->flash_addr;
				1245	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1246	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1247
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1248	/* Disable interrupts. */
				1249	WRT_REG_DWORD(&reg->ictrl, 0);
				1250	RD_REG_DWORD(&reg->ictrl);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1251
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1252	/* Shadow registers. */
				1253	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1254	RD_REG_DWORD(&reg->iobase_addr);
				1255	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1256	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1257
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1258	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1259	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1260
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1261	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1262	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1263
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1264	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1265	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1266
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1267	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1268	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1269
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1270	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1271	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1272
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1273	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1274	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1275
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1276	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1277	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1278
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1279	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1280	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1281
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1282	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1283	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1284
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1285	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1286	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1287
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1288	/* RISC I/O register. */
				1289	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1290	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1291
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1292	/* Mailbox registers. */
				1293	mbx_reg = &reg->mailbox0;
				1294	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1295	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1296
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1297	/* Transfer sequence registers. */
				1298	iter_reg = fw->xseq_gp_reg;
				1299	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1300	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1301	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1302	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1303	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1304	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1305	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1306	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1307
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1308	iter_reg = fw->xseq_0_reg;
				1309	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1310	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1311	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1312
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1313	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1314
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1315	/* Receive sequence registers. */
				1316	iter_reg = fw->rseq_gp_reg;
				1317	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1318	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1319	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1320	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1321	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1322	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1323	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1324	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1325
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1326	iter_reg = fw->rseq_0_reg;
				1327	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1328	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1329
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1330	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1331	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1332
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1333	/* Auxiliary sequence registers. */
				1334	iter_reg = fw->aseq_gp_reg;
				1335	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1336	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1337	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1338	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1339	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1340	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1341	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1342	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1343
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1344	iter_reg = fw->aseq_0_reg;
				1345	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1346	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1347
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1348	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1349	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1350
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1351	/* Command DMA registers. */
				1352	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1353
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1354	/* Queues. */
				1355	iter_reg = fw->req0_dma_reg;
				1356	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1357	dmp_reg = &reg->iobase_q;
				1358	for (cnt = 0; cnt < 7; cnt++)
				1359	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1360
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1361	iter_reg = fw->resp0_dma_reg;
				1362	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1363	dmp_reg = &reg->iobase_q;
				1364	for (cnt = 0; cnt < 7; cnt++)
				1365	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1366
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1367	iter_reg = fw->req1_dma_reg;
				1368	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1369	dmp_reg = &reg->iobase_q;
				1370	for (cnt = 0; cnt < 7; cnt++)
				1371	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1372
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1373	/* Transmit DMA registers. */
				1374	iter_reg = fw->xmt0_dma_reg;
				1375	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1376	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1377
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1378	iter_reg = fw->xmt1_dma_reg;
				1379	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1380	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1381
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1382	iter_reg = fw->xmt2_dma_reg;
				1383	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1384	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1385
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1386	iter_reg = fw->xmt3_dma_reg;
				1387	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1388	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1389
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1390	iter_reg = fw->xmt4_dma_reg;
				1391	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1392	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1393
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1394	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1395
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1396	/* Receive DMA registers. */
				1397	iter_reg = fw->rcvt0_data_dma_reg;
				1398	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1399	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1400
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1401	iter_reg = fw->rcvt1_data_dma_reg;
				1402	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1403	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1404
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1405	/* RISC registers. */
				1406	iter_reg = fw->risc_gp_reg;
				1407	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1408	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1409	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1410	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1411	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1412	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1413	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1414	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1415
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1416	/* Local memory controller registers. */
				1417	iter_reg = fw->lmc_reg;
				1418	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1419	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1420	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1421	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1422	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1423	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1424	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1425	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1426
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1427	/* Fibre Protocol Module registers. */
				1428	iter_reg = fw->fpm_hdw_reg;
				1429	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1430	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1431	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1432	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1433	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1434	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1435	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1436	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1437	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1438	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1439	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1440	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1441
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1442	/* Frame Buffer registers. */
				1443	iter_reg = fw->fb_hdw_reg;
				1444	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1445	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1446	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1447	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1448	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1449	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1450	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1451	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1452	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1453	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1454	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1455	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1456
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1457	/* Multi queue registers */
				1458	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1459	&last_chain);
				1460
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1461	rval = qla24xx_soft_reset(ha);
				1462	if (rval != QLA_SUCCESS)
				1463	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1464
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1465	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1466	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1467	if (rval != QLA_SUCCESS)
				1468	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1469
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1470	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1471
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1472	nxt = qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1473
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1474	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1475	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1476	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1477	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1478	if (last_chain) {
				1479	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1480	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1481	}
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1482
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1483	/* Adjust valid length. */
				1484	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1485
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1486	qla25xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1487	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1488
				1489	qla25xx_fw_dump_failed:
				1490	if (!hardware_locked)
				1491	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1492	}
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1493
				1494	void
				1495	qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1496	{
				1497	int rval;
				1498	uint32_t cnt;
				1499	uint32_t risc_address;
				1500	struct qla_hw_data *ha = vha->hw;
				1501	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1502	uint32_t __iomem *dmp_reg;
				1503	uint32_t *iter_reg;
				1504	uint16_t __iomem *mbx_reg;
				1505	unsigned long flags;
				1506	struct qla81xx_fw_dump *fw;
				1507	uint32_t ext_mem_cnt;
				1508	void nxt, nxt_chain;
				1509	uint32_t *last_chain = NULL;
				1510	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1511
				1512	risc_address = ext_mem_cnt = 0;
				1513	flags = 0;
				1514
				1515	if (!hardware_locked)
				1516	spin_lock_irqsave(&ha->hardware_lock, flags);
				1517
				1518	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1519	ql_log(ql_log_warn, vha, 0xd00a,
				1520	"No buffer available for dump.\n");
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1521	goto qla81xx_fw_dump_failed;
				1522	}
				1523
				1524	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1525	ql_log(ql_log_warn, vha, 0xd00b,
				1526	"Firmware has been previously dumped (%p) "
				1527	"-- ignoring request.\n",
				1528	ha->fw_dump);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1529	goto qla81xx_fw_dump_failed;
				1530	}
				1531	fw = &ha->fw_dump->isp.isp81;
				1532	qla2xxx_prep_dump(ha, ha->fw_dump);
				1533
				1534	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1535
				1536	/* Pause RISC. */
				1537	rval = qla24xx_pause_risc(reg);
				1538	if (rval != QLA_SUCCESS)
				1539	goto qla81xx_fw_dump_failed_0;
				1540
				1541	/* Host/Risc registers. */
				1542	iter_reg = fw->host_risc_reg;
				1543	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1544	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1545
				1546	/* PCIe registers. */
				1547	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1548	RD_REG_DWORD(&reg->iobase_addr);
				1549	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1550	dmp_reg = &reg->iobase_c4;
				1551	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1552	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1553	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1554	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1555
				1556	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1557	RD_REG_DWORD(&reg->iobase_window);
				1558
				1559	/* Host interface registers. */
				1560	dmp_reg = &reg->flash_addr;
				1561	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1562	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1563
				1564	/* Disable interrupts. */
				1565	WRT_REG_DWORD(&reg->ictrl, 0);
				1566	RD_REG_DWORD(&reg->ictrl);
				1567
				1568	/* Shadow registers. */
				1569	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1570	RD_REG_DWORD(&reg->iobase_addr);
				1571	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1572	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1573
				1574	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1575	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1576
				1577	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1578	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1579
				1580	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1581	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1582
				1583	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1584	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1585
				1586	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1587	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1588
				1589	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1590	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1591
				1592	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1593	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1594
				1595	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1596	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1597
				1598	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1599	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1600
				1601	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1602	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1603
				1604	/* RISC I/O register. */
				1605	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1606	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1607
				1608	/* Mailbox registers. */
				1609	mbx_reg = &reg->mailbox0;
				1610	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1611	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1612
				1613	/* Transfer sequence registers. */
				1614	iter_reg = fw->xseq_gp_reg;
				1615	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1616	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1617	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1618	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1619	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1620	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1621	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1622	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1623
				1624	iter_reg = fw->xseq_0_reg;
				1625	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1626	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1627	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1628
				1629	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1630
				1631	/* Receive sequence registers. */
				1632	iter_reg = fw->rseq_gp_reg;
				1633	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1634	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1635	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1636	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1637	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1638	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1639	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1640	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1641
				1642	iter_reg = fw->rseq_0_reg;
				1643	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1644	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1645
				1646	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1647	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				1648
				1649	/* Auxiliary sequence registers. */
				1650	iter_reg = fw->aseq_gp_reg;
				1651	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1652	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1653	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1654	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1655	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1656	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1657	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1658	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				1659
				1660	iter_reg = fw->aseq_0_reg;
				1661	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1662	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				1663
				1664	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1665	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				1666
				1667	/* Command DMA registers. */
				1668	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
				1669
				1670	/* Queues. */
				1671	iter_reg = fw->req0_dma_reg;
				1672	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1673	dmp_reg = &reg->iobase_q;
				1674	for (cnt = 0; cnt < 7; cnt++)
				1675	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1676
				1677	iter_reg = fw->resp0_dma_reg;
				1678	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1679	dmp_reg = &reg->iobase_q;
				1680	for (cnt = 0; cnt < 7; cnt++)
				1681	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1682
				1683	iter_reg = fw->req1_dma_reg;
				1684	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1685	dmp_reg = &reg->iobase_q;
				1686	for (cnt = 0; cnt < 7; cnt++)
				1687	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1688
				1689	/* Transmit DMA registers. */
				1690	iter_reg = fw->xmt0_dma_reg;
				1691	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1692	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				1693
				1694	iter_reg = fw->xmt1_dma_reg;
				1695	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1696	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				1697
				1698	iter_reg = fw->xmt2_dma_reg;
				1699	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1700	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				1701
				1702	iter_reg = fw->xmt3_dma_reg;
				1703	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1704	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				1705
				1706	iter_reg = fw->xmt4_dma_reg;
				1707	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1708	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				1709
				1710	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				1711
				1712	/* Receive DMA registers. */
				1713	iter_reg = fw->rcvt0_data_dma_reg;
				1714	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1715	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				1716
				1717	iter_reg = fw->rcvt1_data_dma_reg;
				1718	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1719	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				1720
				1721	/* RISC registers. */
				1722	iter_reg = fw->risc_gp_reg;
				1723	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1724	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1725	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1726	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1727	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1728	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1729	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1730	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				1731
				1732	/* Local memory controller registers. */
				1733	iter_reg = fw->lmc_reg;
				1734	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1735	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1736	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1737	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1738	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1739	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1740	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1741	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				1742
				1743	/* Fibre Protocol Module registers. */
				1744	iter_reg = fw->fpm_hdw_reg;
				1745	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1746	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1747	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1748	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1749	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1750	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1751	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1752	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1753	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1754	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1755	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1756	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				1757	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				1758	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				1759
				1760	/* Frame Buffer registers. */
				1761	iter_reg = fw->fb_hdw_reg;
				1762	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1763	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1764	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1765	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1766	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1767	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1768	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1769	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1770	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1771	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1772	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1773	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				1774	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				1775
				1776	/* Multi queue registers */
				1777	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1778	&last_chain);
				1779
				1780	rval = qla24xx_soft_reset(ha);
				1781	if (rval != QLA_SUCCESS)
				1782	goto qla81xx_fw_dump_failed_0;
				1783
				1784	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				1785	&nxt);
				1786	if (rval != QLA_SUCCESS)
				1787	goto qla81xx_fw_dump_failed_0;
				1788
				1789	nxt = qla2xxx_copy_queues(ha, nxt);
				1790
				1791	nxt = qla24xx_copy_eft(ha, nxt);
				1792
				1793	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1794	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1795	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1796	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1797	if (last_chain) {
				1798	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1799	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1800	}
				1801
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1802	/* Adjust valid length. */
				1803	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1804
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1805	qla81xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1806	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1807
				1808	qla81xx_fw_dump_failed:
				1809	if (!hardware_locked)
				1810	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1811	}
				1812
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1813	void
				1814	qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1815	{
				1816	int rval;
				1817	uint32_t cnt, reg_data;
				1818	uint32_t risc_address;
				1819	struct qla_hw_data *ha = vha->hw;
				1820	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1821	uint32_t __iomem *dmp_reg;
				1822	uint32_t *iter_reg;
				1823	uint16_t __iomem *mbx_reg;
				1824	unsigned long flags;
				1825	struct qla83xx_fw_dump *fw;
				1826	uint32_t ext_mem_cnt;
				1827	void nxt, nxt_chain;
				1828	uint32_t *last_chain = NULL;
				1829	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1830
				1831	risc_address = ext_mem_cnt = 0;
				1832	flags = 0;
				1833
				1834	if (!hardware_locked)
				1835	spin_lock_irqsave(&ha->hardware_lock, flags);
				1836
				1837	if (!ha->fw_dump) {
				1838	ql_log(ql_log_warn, vha, 0xd00c,
				1839	"No buffer available for dump!!!\n");
				1840	goto qla83xx_fw_dump_failed;
				1841	}
				1842
				1843	if (ha->fw_dumped) {
				1844	ql_log(ql_log_warn, vha, 0xd00d,
				1845	"Firmware has been previously dumped (%p) -- ignoring "
				1846	"request...\n", ha->fw_dump);
				1847	goto qla83xx_fw_dump_failed;
				1848	}
				1849	fw = &ha->fw_dump->isp.isp83;
				1850	qla2xxx_prep_dump(ha, ha->fw_dump);
				1851
				1852	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1853
				1854	/* Pause RISC. */
				1855	rval = qla24xx_pause_risc(reg);
				1856	if (rval != QLA_SUCCESS)
				1857	goto qla83xx_fw_dump_failed_0;
				1858
				1859	WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
				1860	dmp_reg = &reg->iobase_window;
				1861	reg_data = RD_REG_DWORD(dmp_reg);
				1862	WRT_REG_DWORD(dmp_reg, 0);
				1863
				1864	dmp_reg = &reg->unused_4_1[0];
				1865	reg_data = RD_REG_DWORD(dmp_reg);
				1866	WRT_REG_DWORD(dmp_reg, 0);
				1867
				1868	WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
				1869	dmp_reg = &reg->unused_4_1[2];
				1870	reg_data = RD_REG_DWORD(dmp_reg);
				1871	WRT_REG_DWORD(dmp_reg, 0);
				1872
				1873	/* select PCR and disable ecc checking and correction */
				1874	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1875	RD_REG_DWORD(&reg->iobase_addr);
				1876	WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
				1877
				1878	/* Host/Risc registers. */
				1879	iter_reg = fw->host_risc_reg;
				1880	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1881	iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1882	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
				1883
				1884	/* PCIe registers. */
				1885	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1886	RD_REG_DWORD(&reg->iobase_addr);
				1887	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1888	dmp_reg = &reg->iobase_c4;
				1889	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1890	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1891	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1892	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1893
				1894	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1895	RD_REG_DWORD(&reg->iobase_window);
				1896
				1897	/* Host interface registers. */
				1898	dmp_reg = &reg->flash_addr;
				1899	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1900	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1901
				1902	/* Disable interrupts. */
				1903	WRT_REG_DWORD(&reg->ictrl, 0);
				1904	RD_REG_DWORD(&reg->ictrl);
				1905
				1906	/* Shadow registers. */
				1907	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1908	RD_REG_DWORD(&reg->iobase_addr);
				1909	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1910	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1911
				1912	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1913	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1914
				1915	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1916	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1917
				1918	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1919	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1920
				1921	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1922	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1923
				1924	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1925	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1926
				1927	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1928	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1929
				1930	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1931	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1932
				1933	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1934	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1935
				1936	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1937	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1938
				1939	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1940	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1941
				1942	/* RISC I/O register. */
				1943	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1944	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1945
				1946	/* Mailbox registers. */
				1947	mbx_reg = &reg->mailbox0;
				1948	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1949	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1950
				1951	/* Transfer sequence registers. */
				1952	iter_reg = fw->xseq_gp_reg;
				1953	iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
				1954	iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
				1955	iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
				1956	iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
				1957	iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
				1958	iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
				1959	iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
				1960	iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
				1961	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1962	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1963	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1964	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1965	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1966	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1967	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1968	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1969
				1970	iter_reg = fw->xseq_0_reg;
				1971	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1972	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1973	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1974
				1975	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1976
				1977	qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
				1978
				1979	/* Receive sequence registers. */
				1980	iter_reg = fw->rseq_gp_reg;
				1981	iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
				1982	iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
				1983	iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
				1984	iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
				1985	iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
				1986	iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
				1987	iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
				1988	iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
				1989	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1990	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1991	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1992	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1993	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1994	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1995	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1996	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1997
				1998	iter_reg = fw->rseq_0_reg;
				1999	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				2000	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				2001
				2002	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				2003	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				2004	qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
				2005
				2006	/* Auxiliary sequence registers. */
				2007	iter_reg = fw->aseq_gp_reg;
				2008	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				2009	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				2010	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				2011	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				2012	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				2013	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				2014	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				2015	iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				2016	iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
				2017	iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
				2018	iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
				2019	iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
				2020	iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
				2021	iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
				2022	iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
				2023	qla24xx_read_window(reg, 0xB170, 16, iter_reg);
				2024
				2025	iter_reg = fw->aseq_0_reg;
				2026	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				2027	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				2028
				2029	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				2030	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				2031	qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
				2032
				2033	/* Command DMA registers. */
				2034	iter_reg = fw->cmd_dma_reg;
				2035	iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
				2036	iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
				2037	iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
				2038	qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
				2039
				2040	/* Queues. */
				2041	iter_reg = fw->req0_dma_reg;
				2042	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				2043	dmp_reg = &reg->iobase_q;
				2044	for (cnt = 0; cnt < 7; cnt++)
				2045	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2046
				2047	iter_reg = fw->resp0_dma_reg;
				2048	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				2049	dmp_reg = &reg->iobase_q;
				2050	for (cnt = 0; cnt < 7; cnt++)
				2051	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2052
				2053	iter_reg = fw->req1_dma_reg;
				2054	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				2055	dmp_reg = &reg->iobase_q;
				2056	for (cnt = 0; cnt < 7; cnt++)
				2057	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2058
				2059	/* Transmit DMA registers. */
				2060	iter_reg = fw->xmt0_dma_reg;
				2061	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				2062	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				2063
				2064	iter_reg = fw->xmt1_dma_reg;
				2065	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				2066	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				2067
				2068	iter_reg = fw->xmt2_dma_reg;
				2069	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				2070	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				2071
				2072	iter_reg = fw->xmt3_dma_reg;
				2073	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				2074	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				2075
				2076	iter_reg = fw->xmt4_dma_reg;
				2077	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				2078	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				2079
				2080	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				2081
				2082	/* Receive DMA registers. */
				2083	iter_reg = fw->rcvt0_data_dma_reg;
				2084	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				2085	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				2086
				2087	iter_reg = fw->rcvt1_data_dma_reg;
				2088	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				2089	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				2090
				2091	/* RISC registers. */
				2092	iter_reg = fw->risc_gp_reg;
				2093	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				2094	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				2095	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				2096	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				2097	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				2098	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				2099	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				2100	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				2101
				2102	/* Local memory controller registers. */
				2103	iter_reg = fw->lmc_reg;
				2104	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				2105	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				2106	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				2107	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				2108	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				2109	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				2110	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				2111	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				2112
				2113	/* Fibre Protocol Module registers. */
				2114	iter_reg = fw->fpm_hdw_reg;
				2115	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				2116	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				2117	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				2118	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				2119	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				2120	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				2121	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				2122	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				2123	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				2124	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				2125	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				2126	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				2127	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				2128	iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				2129	iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
				2130	qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
				2131
				2132	/* RQ0 Array registers. */
				2133	iter_reg = fw->rq0_array_reg;
				2134	iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
				2135	iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
				2136	iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
				2137	iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
				2138	iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
				2139	iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
				2140	iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
				2141	iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
				2142	iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
				2143	iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
				2144	iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
				2145	iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
				2146	iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
				2147	iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
				2148	iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
				2149	qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
				2150
				2151	/* RQ1 Array registers. */
				2152	iter_reg = fw->rq1_array_reg;
				2153	iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
				2154	iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
				2155	iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
				2156	iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
				2157	iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
				2158	iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
				2159	iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
				2160	iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
				2161	iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
				2162	iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
				2163	iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
				2164	iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
				2165	iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
				2166	iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
				2167	iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
				2168	qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
				2169
				2170	/* RP0 Array registers. */
				2171	iter_reg = fw->rp0_array_reg;
				2172	iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
				2173	iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
				2174	iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
				2175	iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
				2176	iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
				2177	iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
				2178	iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
				2179	iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
				2180	iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
				2181	iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
				2182	iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
				2183	iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
				2184	iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
				2185	iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
				2186	iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
				2187	qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
				2188
				2189	/* RP1 Array registers. */
				2190	iter_reg = fw->rp1_array_reg;
				2191	iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
				2192	iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
				2193	iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
				2194	iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
				2195	iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
				2196	iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
				2197	iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
				2198	iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
				2199	iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
				2200	iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
				2201	iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
				2202	iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
				2203	iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
				2204	iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
				2205	iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
				2206	qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
				2207
				2208	iter_reg = fw->at0_array_reg;
				2209	iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
				2210	iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
				2211	iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
				2212	iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
				2213	iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
				2214	iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
				2215	iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
				2216	qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
				2217
				2218	/* I/O Queue Control registers. */
				2219	qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
				2220
				2221	/* Frame Buffer registers. */
				2222	iter_reg = fw->fb_hdw_reg;
				2223	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				2224	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				2225	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				2226	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				2227	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				2228	iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
				2229	iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
				2230	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				2231	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				2232	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				2233	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				2234	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				2235	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				2236	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				2237	iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
				2238	iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
				2239	iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
				2240	iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
				2241	iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
				2242	iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
				2243	iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
				2244	iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
				2245	iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
				2246	iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
				2247	iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
				2248	iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
				2249	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				2250
				2251	/* Multi queue registers */
				2252	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				2253	&last_chain);
				2254
				2255	rval = qla24xx_soft_reset(ha);
				2256	if (rval != QLA_SUCCESS) {
				2257	ql_log(ql_log_warn, vha, 0xd00e,
				2258	"SOFT RESET FAILED, forcing continuation of dump!!!\n");
				2259	rval = QLA_SUCCESS;
				2260
				2261	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
				2262
				2263	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
				2264	RD_REG_DWORD(&reg->hccr);
				2265
				2266	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
				2267	RD_REG_DWORD(&reg->hccr);
				2268
				2269	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				2270	RD_REG_DWORD(&reg->hccr);
				2271
				2272	for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
				2273	udelay(5);
				2274
				2275	if (!cnt) {
				2276	nxt = fw->code_ram;
Saurav Kashyap	8c0bc70	2012-11-21 02:40:35 -0500	[diff] [blame]	2277	nxt += sizeof(fw->code_ram);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2278	nxt += (ha->fw_memory_size - 0x100000 + 1);
				2279	goto copy_queue;
				2280	} else
				2281	ql_log(ql_log_warn, vha, 0xd010,
				2282	"bigger hammer success?\n");
				2283	}
				2284
				2285	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				2286	&nxt);
				2287	if (rval != QLA_SUCCESS)
				2288	goto qla83xx_fw_dump_failed_0;
				2289
				2290	copy_queue:
				2291	nxt = qla2xxx_copy_queues(ha, nxt);
				2292
				2293	nxt = qla24xx_copy_eft(ha, nxt);
				2294
				2295	/* Chain entries -- started with MQ. */
				2296	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				2297	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	2298	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2299	if (last_chain) {
				2300	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				2301	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				2302	}
				2303
				2304	/* Adjust valid length. */
				2305	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				2306
				2307	qla83xx_fw_dump_failed_0:
				2308	qla2xxx_dump_post_process(base_vha, rval);
				2309
				2310	qla83xx_fw_dump_failed:
				2311	if (!hardware_locked)
				2312	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				2313	}
				2314
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2315	/****************************************************************************/
				2316	/* Driver Debug Functions. */
				2317	/****************************************************************************/
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2318
				2319	static inline int
				2320	ql_mask_match(uint32_t level)
				2321	{
				2322	if (ql2xextended_error_logging == 1)
				2323	ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
				2324	return (level & ql2xextended_error_logging) == level;
				2325	}
				2326
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2327	/*
				2328	* This function is for formatting and logging debug information.
				2329	* It is to be used when vha is available. It formats the message
				2330	* and logs it to the messages file.
				2331	* parameters:
				2332	* level: The level of the debug messages to be printed.
				2333	* If ql2xextended_error_logging value is correctly set,
				2334	* this message will appear in the messages file.
				2335	* vha: Pointer to the scsi_qla_host_t.
				2336	* id: This is a unique identifier for the level. It identifies the
				2337	* part of the code from where the message originated.
				2338	* msg: The message to be displayed.
				2339	*/
				2340	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2341	ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2342	{
				2343	va_list va;
				2344	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2345
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2346	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2347	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2348
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2349	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2350
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2351	vaf.fmt = fmt;
				2352	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2353
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2354	if (vha != NULL) {
				2355	const struct pci_dev *pdev = vha->hw->pdev;
				2356	/* <module-name> <pci-name> <msg-id>:<host> Message */
				2357	pr_warn("%s [%s]-%04x:%ld: %pV",
				2358	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
				2359	vha->host_no, &vaf);
				2360	} else {
				2361	pr_warn("%s [%s]-%04x: : %pV",
				2362	QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2363	}
				2364
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2365	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2366
				2367	}
				2368
				2369	/*
				2370	* This function is for formatting and logging debug information.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2371	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2372	* i.e., before host allocation. It formats the message and logs it
				2373	* to the messages file.
				2374	* parameters:
				2375	* level: The level of the debug messages to be printed.
				2376	* If ql2xextended_error_logging value is correctly set,
				2377	* this message will appear in the messages file.
				2378	* pdev: Pointer to the struct pci_dev.
				2379	* id: This is a unique id for the level. It identifies the part
				2380	* of the code from where the message originated.
				2381	* msg: The message to be displayed.
				2382	*/
				2383	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2384	ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2385	const char *fmt, ...)
				2386	{
				2387	va_list va;
				2388	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2389
				2390	if (pdev == NULL)
				2391	return;
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2392	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2393	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2394
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2395	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2396
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2397	vaf.fmt = fmt;
				2398	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2399
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2400	/* <module-name> <dev-name>:<msg-id> Message */
				2401	pr_warn("%s [%s]-%04x: : %pV",
				2402	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2403
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2404	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2405	}
				2406
				2407	/*
				2408	* This function is for formatting and logging log messages.
				2409	* It is to be used when vha is available. It formats the message
				2410	* and logs it to the messages file. All the messages will be logged
				2411	* irrespective of value of ql2xextended_error_logging.
				2412	* parameters:
				2413	* level: The level of the log messages to be printed in the
				2414	* messages file.
				2415	* vha: Pointer to the scsi_qla_host_t
				2416	* id: This is a unique id for the level. It identifies the
				2417	* part of the code from where the message originated.
				2418	* msg: The message to be displayed.
				2419	*/
				2420	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2421	ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2422	{
				2423	va_list va;
				2424	struct va_format vaf;
				2425	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2426
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2427	if (level > ql_errlev)
				2428	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2429
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2430	if (vha != NULL) {
				2431	const struct pci_dev *pdev = vha->hw->pdev;
				2432	/* <module-name> <msg-id>:<host> Message */
				2433	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
				2434	QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
				2435	} else {
				2436	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2437	QL_MSGHDR, "0000:00:00.0", id);
				2438	}
				2439	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2440
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2441	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2442
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2443	vaf.fmt = fmt;
				2444	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2445
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2446	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2447	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2448	pr_crit("%s%pV", pbuf, &vaf);
				2449	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2450	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2451	pr_err("%s%pV", pbuf, &vaf);
				2452	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2453	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2454	pr_warn("%s%pV", pbuf, &vaf);
				2455	break;
				2456	default:
				2457	pr_info("%s%pV", pbuf, &vaf);
				2458	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2459	}
				2460
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2461	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2462	}
				2463
				2464	/*
				2465	* This function is for formatting and logging log messages.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2466	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2467	* i.e., before host allocation. It formats the message and logs
				2468	* it to the messages file. All the messages are logged irrespective
				2469	* of the value of ql2xextended_error_logging.
				2470	* parameters:
				2471	* level: The level of the log messages to be printed in the
				2472	* messages file.
				2473	* pdev: Pointer to the struct pci_dev.
				2474	* id: This is a unique id for the level. It identifies the
				2475	* part of the code from where the message originated.
				2476	* msg: The message to be displayed.
				2477	*/
				2478	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2479	ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2480	const char *fmt, ...)
				2481	{
				2482	va_list va;
				2483	struct va_format vaf;
				2484	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2485
				2486	if (pdev == NULL)
				2487	return;
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2488	if (level > ql_errlev)
				2489	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2490
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2491	/* <module-name> <dev-name>:<msg-id> Message */
				2492	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2493	QL_MSGHDR, dev_name(&(pdev->dev)), id);
				2494	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2495
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2496	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2497
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2498	vaf.fmt = fmt;
				2499	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2500
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2501	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2502	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2503	pr_crit("%s%pV", pbuf, &vaf);
				2504	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2505	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2506	pr_err("%s%pV", pbuf, &vaf);
				2507	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2508	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2509	pr_warn("%s%pV", pbuf, &vaf);
				2510	break;
				2511	default:
				2512	pr_info("%s%pV", pbuf, &vaf);
				2513	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2514	}
				2515
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2516	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2517	}
				2518
				2519	void
				2520	ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
				2521	{
				2522	int i;
				2523	struct qla_hw_data *ha = vha->hw;
				2524	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				2525	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
				2526	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
				2527	uint16_t __iomem *mbx_reg;
				2528
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2529	if (!ql_mask_match(level))
				2530	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2531
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2532	if (IS_QLA82XX(ha))
				2533	mbx_reg = &reg82->mailbox_in[0];
				2534	else if (IS_FWI2_CAPABLE(ha))
				2535	mbx_reg = &reg24->mailbox0;
				2536	else
				2537	mbx_reg = MAILBOX_REG(ha, reg, 0);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2538
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2539	ql_dbg(level, vha, id, "Mailbox registers:\n");
				2540	for (i = 0; i < 6; i++)
				2541	ql_dbg(level, vha, id,
				2542	"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2543	}
				2544
				2545
				2546	void
				2547	ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
				2548	uint8_t *b, uint32_t size)
				2549	{
				2550	uint32_t cnt;
				2551	uint8_t c;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2552
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2553	if (!ql_mask_match(level))
				2554	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2555
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2556	ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
				2557	"9 Ah Bh Ch Dh Eh Fh\n");
				2558	ql_dbg(level, vha, id, "----------------------------------"
				2559	"----------------------------\n");
				2560
				2561	ql_dbg(level, vha, id, " ");
				2562	for (cnt = 0; cnt < size;) {
				2563	c = *b++;
				2564	printk("%02x", (uint32_t) c);
				2565	cnt++;
				2566	if (!(cnt % 16))
				2567	printk("\n");
				2568	else
				2569	printk(" ");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2570	}
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2571	if (cnt % 16)
				2572	ql_dbg(level, vha, id, "\n");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2573	}