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review.evervolv.com / android_kernel_oneplus_msm8996 / a57350216d5d54dec387d8dd746ec73f2ea825a8 / . / arch / arm / boot / dts / imx51.dtsi
blob: 768e6da594a2198df85a1c04efccbef3ace2cf8f [file] [log] [blame]
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx51-pinfunc.h"
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]25 };
26
27 tzic: tz-interrupt-controller@e0000000 {
28 compatible = "fsl,imx51-tzic", "fsl,tzic";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 reg = <0xe0000000 0x4000>;
32 };
33
34 clocks {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 ckil {
39 compatible = "fsl,imx-ckil", "fixed-clock";
40 clock-frequency = <32768>;
41 };
42
43 ckih1 {
44 compatible = "fsl,imx-ckih1", "fixed-clock";
45 clock-frequency = <22579200>;
46 };
47
48 ckih2 {
49 compatible = "fsl,imx-ckih2", "fixed-clock";
50 clock-frequency = <0>;
51 };
52
53 osc {
54 compatible = "fsl,imx-osc", "fixed-clock";
55 clock-frequency = <24000000>;
56 };
57 };
58
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 cpu@0 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a8";
65 reg = <0>;
66 clock-latency = <61036>; /* two CLK32 periods */
67 clocks = <&clks 24>;
68 clock-names = "cpu";
69 operating-points = <
70 /* kHz uV (No regulator support) */
71 160000 0
72 800000 0
73 >;
74 };
75 };
76
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]77 soc {
78 #address-cells = <1>;
79 #size-cells = <1>;
80 compatible = "simple-bus";
81 interrupt-parent = <&tzic>;
82 ranges;
83
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]84 ipu: ipu@40000000 {
85 #crtc-cells = <1>;
86 compatible = "fsl,imx51-ipu";
87 reg = <0x40000000 0x20000000>;
88 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]89 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
90 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]91 resets = <&src 2>;
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]92 };
93
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]94 aips@70000000 { /* AIPS1 */
95 compatible = "fsl,aips-bus", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 reg = <0x70000000 0x10000000>;
99 ranges;
100
101 spba@70000000 {
102 compatible = "fsl,spba-bus", "simple-bus";
103 #address-cells = <1>;
104 #size-cells = <1>;
105 reg = <0x70000000 0x40000>;
106 ranges;
107
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]108 esdhc1: esdhc@70004000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]109 compatible = "fsl,imx51-esdhc";
110 reg = <0x70004000 0x4000>;
111 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]112 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
113 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]114 status = "disabled";
115 };
116
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]117 esdhc2: esdhc@70008000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]118 compatible = "fsl,imx51-esdhc";
119 reg = <0x70008000 0x4000>;
120 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]121 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
122 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]123 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]124 status = "disabled";
125 };
126
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]127 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]128 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
129 reg = <0x7000c000 0x4000>;
130 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]131 clocks = <&clks 32>, <&clks 33>;
132 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]133 status = "disabled";
134 };
135
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]136 ecspi1: ecspi@70010000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]137 #address-cells = <1>;
138 #size-cells = <0>;
139 compatible = "fsl,imx51-ecspi";
140 reg = <0x70010000 0x4000>;
141 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]142 clocks = <&clks 51>, <&clks 52>;
143 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]144 status = "disabled";
145 };
146
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]147 ssi2: ssi@70014000 {
148 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
149 reg = <0x70014000 0x4000>;
150 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]151 clocks = <&clks 49>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]152 fsl,fifo-depth = <15>;
153 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
154 status = "disabled";
155 };
156
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]157 esdhc3: esdhc@70020000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]158 compatible = "fsl,imx51-esdhc";
159 reg = <0x70020000 0x4000>;
160 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]161 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
162 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]163 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]164 status = "disabled";
165 };
166
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]167 esdhc4: esdhc@70024000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]168 compatible = "fsl,imx51-esdhc";
169 reg = <0x70024000 0x4000>;
170 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]171 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
172 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]173 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]174 status = "disabled";
175 };
176 };
177
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]178 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]179 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
180 reg = <0x73f80000 0x0200>;
181 interrupts = <18>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]182 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]183 status = "disabled";
184 };
185
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]186 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]187 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
188 reg = <0x73f80200 0x0200>;
189 interrupts = <14>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]190 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]191 status = "disabled";
192 };
193
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]194 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]195 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
196 reg = <0x73f80400 0x0200>;
197 interrupts = <16>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]198 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]199 status = "disabled";
200 };
201
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]202 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]203 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
204 reg = <0x73f80600 0x0200>;
205 interrupts = <17>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]206 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]207 status = "disabled";
208 };
209
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame^]210 usbmisc: usbmisc@73f80800 {
211 #index-cells = <1>;
212 compatible = "fsl,imx51-usbmisc";
213 reg = <0x73f80800 0x200>;
214 };
215
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]216 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]217 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]218 reg = <0x73f84000 0x4000>;
219 interrupts = <50 51>;
220 gpio-controller;
221 #gpio-cells = <2>;
222 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]223 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]224 };
225
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]226 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]227 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]228 reg = <0x73f88000 0x4000>;
229 interrupts = <52 53>;
230 gpio-controller;
231 #gpio-cells = <2>;
232 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]233 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]234 };
235
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]236 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]237 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]238 reg = <0x73f8c000 0x4000>;
239 interrupts = <54 55>;
240 gpio-controller;
241 #gpio-cells = <2>;
242 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]243 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]244 };
245
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]246 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]247 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]248 reg = <0x73f90000 0x4000>;
249 interrupts = <56 57>;
250 gpio-controller;
251 #gpio-cells = <2>;
252 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]253 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]254 };
255
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]256 kpp: kpp@73f94000 {
257 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
258 reg = <0x73f94000 0x4000>;
259 interrupts = <60>;
260 clocks = <&clks 0>;
261 status = "disabled";
262 };
263
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]264 wdog1: wdog@73f98000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]265 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
266 reg = <0x73f98000 0x4000>;
267 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]268 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]269 };
270
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]271 wdog2: wdog@73f9c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]272 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
273 reg = <0x73f9c000 0x4000>;
274 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]275 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]276 status = "disabled";
277 };
278
Sascha Hauered73c632013-03-14 13:08:59 +0100[diff] [blame]279 gpt: timer@73fa0000 {
280 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
281 reg = <0x73fa0000 0x4000>;
282 interrupts = <39>;
283 clocks = <&clks 36>, <&clks 41>;
284 clock-names = "ipg", "per";
285 };
286
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]287 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]288 compatible = "fsl,imx51-iomuxc";
289 reg = <0x73fa8000 0x4000>;
290
291 audmux {
292 pinctrl_audmux_1: audmuxgrp-1 {
293 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]294 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
295 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
296 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
297 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]298 >;
299 };
300 };
301
302 fec {
303 pinctrl_fec_1: fecgrp-1 {
304 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]305 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
306 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
307 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
308 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
309 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
310 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
311 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
312 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
313 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
314 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
315 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
316 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
317 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
318 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
319 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
320 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
321 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]322 >;
323 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]324
325 pinctrl_fec_2: fecgrp-2 {
326 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]327 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
328 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
329 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
330 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
331 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
332 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
333 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
334 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
335 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
336 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
337 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
338 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
339 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
340 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
341 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
342 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
343 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
344 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]345 >;
346 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]347 };
348
349 ecspi1 {
350 pinctrl_ecspi1_1: ecspi1grp-1 {
351 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]352 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
353 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
354 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]355 >;
356 };
357 };
358
Gwenhael Goavec-Meroua15ac4a2013-03-09 14:59:08 +0100[diff] [blame]359 ecspi2 {
360 pinctrl_ecspi2_1: ecspi2grp-1 {
361 fsl,pins = <
362 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
363 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
364 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
365 >;
366 };
367 };
368
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]369 esdhc1 {
370 pinctrl_esdhc1_1: esdhc1grp-1 {
371 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]372 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
373 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
374 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
375 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
376 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
377 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]378 >;
379 };
380 };
381
382 esdhc2 {
383 pinctrl_esdhc2_1: esdhc2grp-1 {
384 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]385 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
386 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
387 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
388 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
389 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
390 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]391 >;
392 };
393 };
394
395 i2c2 {
396 pinctrl_i2c2_1: i2c2grp-1 {
397 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]398 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
399 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]400 >;
401 };
Gwenhael Goavec-Merou52c9aa92013-03-09 15:04:19 +0100[diff] [blame]402
403 pinctrl_i2c2_2: i2c2grp-2 {
404 fsl,pins = <
405 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
406 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
407 >;
408 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]409 };
410
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]411 ipu_disp1 {
412 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
413 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]414 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
415 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
416 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
417 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
418 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
419 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
420 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
421 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
422 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
423 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
424 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
425 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
426 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
427 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
428 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
429 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
430 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
431 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
432 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
433 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
434 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
435 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
436 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
437 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
438 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
439 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]440 >;
441 };
442 };
443
444 ipu_disp2 {
445 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
446 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]447 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
448 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
449 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
450 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
451 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
452 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
453 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
454 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
455 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
456 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
457 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
458 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
459 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
460 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
461 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
462 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
463 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
464 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
465 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
466 MX51_PAD_DI_GP4__DI2_PIN15 0x5
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]467 >;
468 };
469 };
470
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]471 pata {
472 pinctrl_pata_1: patagrp-1 {
473 fsl,pins = <
474 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
475 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
476 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
477 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
478 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
479 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
480 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
481 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
482 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
483 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
484 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
485 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
486 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
487 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
488 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
489 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
490 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
491 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
492 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
493 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
494 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
495 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
496 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
497 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
498 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
499 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
500 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
501 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
502 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
503 >;
504 };
505 };
506
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]507 uart1 {
508 pinctrl_uart1_1: uart1grp-1 {
509 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]510 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
511 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
512 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
513 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]514 >;
515 };
516 };
517
518 uart2 {
519 pinctrl_uart2_1: uart2grp-1 {
520 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]521 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
522 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]523 >;
524 };
525 };
526
527 uart3 {
528 pinctrl_uart3_1: uart3grp-1 {
529 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]530 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
531 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
532 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
533 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]534 >;
535 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]536
537 pinctrl_uart3_2: uart3grp-2 {
538 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]539 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
540 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]541 >;
542 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]543 };
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]544
545 kpp {
546 pinctrl_kpp_1: kppgrp-1 {
547 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]548 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
549 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
550 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
551 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
552 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
553 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
554 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
555 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]556 >;
557 };
558 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]559 };
560
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]561 pwm1: pwm@73fb4000 {
562 #pwm-cells = <2>;
563 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
564 reg = <0x73fb4000 0x4000>;
565 clocks = <&clks 37>, <&clks 38>;
566 clock-names = "ipg", "per";
567 interrupts = <61>;
568 };
569
570 pwm2: pwm@73fb8000 {
571 #pwm-cells = <2>;
572 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
573 reg = <0x73fb8000 0x4000>;
574 clocks = <&clks 39>, <&clks 40>;
575 clock-names = "ipg", "per";
576 interrupts = <94>;
577 };
578
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]579 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]580 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
581 reg = <0x73fbc000 0x4000>;
582 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]583 clocks = <&clks 28>, <&clks 29>;
584 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]585 status = "disabled";
586 };
587
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]588 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]589 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
590 reg = <0x73fc0000 0x4000>;
591 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]592 clocks = <&clks 30>, <&clks 31>;
593 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]594 status = "disabled";
595 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]596
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]597 src: src@73fd0000 {
598 compatible = "fsl,imx51-src";
599 reg = <0x73fd0000 0x4000>;
600 #reset-cells = <1>;
601 };
602
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]603 clks: ccm@73fd4000{
604 compatible = "fsl,imx51-ccm";
605 reg = <0x73fd4000 0x4000>;
606 interrupts = <0 71 0x04 0 72 0x04>;
607 #clock-cells = <1>;
608 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]609 };
610
611 aips@80000000 { /* AIPS2 */
612 compatible = "fsl,aips-bus", "simple-bus";
613 #address-cells = <1>;
614 #size-cells = <1>;
615 reg = <0x80000000 0x10000000>;
616 ranges;
617
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]618 ecspi2: ecspi@83fac000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]619 #address-cells = <1>;
620 #size-cells = <0>;
621 compatible = "fsl,imx51-ecspi";
622 reg = <0x83fac000 0x4000>;
623 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]624 clocks = <&clks 53>, <&clks 54>;
625 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]626 status = "disabled";
627 };
628
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]629 sdma: sdma@83fb0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]630 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
631 reg = <0x83fb0000 0x4000>;
632 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]633 clocks = <&clks 56>, <&clks 56>;
634 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]635 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]636 };
637
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]638 cspi: cspi@83fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]639 #address-cells = <1>;
640 #size-cells = <0>;
641 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
642 reg = <0x83fc0000 0x4000>;
643 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200[diff] [blame]644 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]645 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]646 status = "disabled";
647 };
648
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]649 i2c2: i2c@83fc4000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]650 #address-cells = <1>;
651 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]652 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]653 reg = <0x83fc4000 0x4000>;
654 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]655 clocks = <&clks 35>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]656 status = "disabled";
657 };
658
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]659 i2c1: i2c@83fc8000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]660 #address-cells = <1>;
661 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]662 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]663 reg = <0x83fc8000 0x4000>;
664 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]665 clocks = <&clks 34>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]666 status = "disabled";
667 };
668
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]669 ssi1: ssi@83fcc000 {
670 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
671 reg = <0x83fcc000 0x4000>;
672 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]673 clocks = <&clks 48>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]674 fsl,fifo-depth = <15>;
675 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
676 status = "disabled";
677 };
678
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]679 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]680 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
681 reg = <0x83fd0000 0x4000>;
682 status = "disabled";
683 };
684
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]685 nfc: nand@83fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]686 compatible = "fsl,imx51-nand";
687 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
688 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]689 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]690 status = "disabled";
691 };
692
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]693 pata: pata@83fe0000 {
694 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
695 reg = <0x83fe0000 0x4000>;
696 interrupts = <70>;
697 clocks = <&clks 161>;
698 status = "disabled";
699 };
700
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]701 ssi3: ssi@83fe8000 {
702 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
703 reg = <0x83fe8000 0x4000>;
704 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]705 clocks = <&clks 50>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]706 fsl,fifo-depth = <15>;
707 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
708 status = "disabled";
709 };
710
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]711 fec: ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]712 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
713 reg = <0x83fec000 0x4000>;
714 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]715 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
716 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]717 status = "disabled";
718 };
719 };
720 };
721};