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review.evervolv.com / android_kernel_oneplus_msm8996 / a5770904d7220a31a4a160ca793a029d6382a8da / . / arch / arm / boot / dts / imx6q.dtsi
blob: 312a22e4e9b0fc097b88789026c470584107482d [file] [log] [blame]
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]1
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]11#include "imx6qdl.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]12#include "imx6q-pinfunc.h"
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 operating-points = <
24 /* kHz uV */
25 1200000 1275000
26 996000 1250000
27 792000 1150000
28 396000 950000
29 >;
30 clock-latency = <61036>; /* two CLK32 periods */
31 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
32 <&clks 17>, <&clks 170>;
33 clock-names = "arm", "pll2_pfd2_396m", "step",
34 "pll1_sw", "pll1_sys";
35 arm-supply = <&reg_arm>;
36 pu-supply = <&reg_pu>;
37 soc-supply = <&reg_soc>;
38 };
39
40 cpu@1 {
41 compatible = "arm,cortex-a9";
42 reg = <1>;
43 next-level-cache = <&L2>;
44 };
45
46 cpu@2 {
47 compatible = "arm,cortex-a9";
48 reg = <2>;
49 next-level-cache = <&L2>;
50 };
51
52 cpu@3 {
53 compatible = "arm,cortex-a9";
54 reg = <3>;
55 next-level-cache = <&L2>;
56 };
57 };
58
59 soc {
60 aips-bus@02000000 { /* AIPS1 */
61 spba-bus@02000000 {
62 ecspi5: ecspi@02018000 {
63 #address-cells = <1>;
64 #size-cells = <0>;
65 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
66 reg = <0x02018000 0x4000>;
67 interrupts = <0 35 0x04>;
68 clocks = <&clks 116>, <&clks 116>;
69 clock-names = "ipg", "per";
70 status = "disabled";
71 };
72 };
73
74 iomuxc: iomuxc@020e0000 {
75 compatible = "fsl,imx6q-iomuxc";
76 reg = <0x020e0000 0x4000>;
77
78 /* shared pinctrl settings */
79 audmux {
80 pinctrl_audmux_1: audmux-1 {
81 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]82 MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
83 MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
84 MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
85 MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]86 >;
87 };
Sean Cross624dbac2013-03-07 06:00:10 +0000[diff] [blame]88
89 pinctrl_audmux_2: audmux-2 {
90 fsl,pins = <
91 MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
92 MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
93 MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
94 MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
95 >;
96 };
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]97 };
98
99 ecspi1 {
100 pinctrl_ecspi1_1: ecspi1grp-1 {
101 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]102 MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
103 MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
104 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]105 >;
106 };
107 };
108
Sean Cross4820a9a2013-03-07 06:00:08 +0000[diff] [blame]109 ecspi3 {
110 pinctrl_ecspi3_1: ecspi3grp-1 {
111 fsl,pins = <
112 MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
113 MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
114 MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
115 >;
116 };
117 };
118
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]119 enet {
120 pinctrl_enet_1: enetgrp-1 {
121 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]122 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
123 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
124 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
125 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
126 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
127 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
128 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
129 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
130 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
131 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
132 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
133 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
134 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
135 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
136 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
137 MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]138 >;
139 };
140
141 pinctrl_enet_2: enetgrp-2 {
142 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]143 MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
144 MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
145 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
146 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
147 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
148 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
149 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
150 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
151 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
152 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
153 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
154 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
155 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
156 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
157 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]158 >;
159 };
Christian Hempa5770902013-06-11 19:48:21 +0200[diff] [blame^]160
161 pinctrl_enet_3: enetgrp-3 {
162 fsl,pins = <
163 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
164 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
165 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
166 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
167 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
168 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
169 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
170 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
171 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
172 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
173 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
174 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
175 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
176 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
177 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
178 MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
179 >;
180 };
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]181 };
182
183 gpmi-nand {
184 pinctrl_gpmi_nand_1: gpmi-nand-1 {
185 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]186 MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
187 MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
188 MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
189 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
190 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
191 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]192 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
193 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
194 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
195 MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
196 MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
197 MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
198 MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
199 MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
200 MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
201 MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
202 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]203 >;
204 };
205 };
206
207 i2c1 {
208 pinctrl_i2c1_1: i2c1grp-1 {
209 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]210 MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
211 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]212 >;
213 };
214 };
215
Sean Crossd27f5122013-03-07 06:00:09 +0000[diff] [blame]216 i2c2 {
217 pinctrl_i2c2_1: i2c2grp-1 {
218 fsl,pins = <
219 MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
220 MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
221 >;
222 };
223 };
224
225 i2c3 {
226 pinctrl_i2c3_1: i2c3grp-1 {
227 fsl,pins = <
228 MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
229 MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
230 >;
231 };
232 };
233
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]234 uart1 {
235 pinctrl_uart1_1: uart1grp-1 {
236 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]237 MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
238 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]239 >;
240 };
241 };
242
243 uart2 {
244 pinctrl_uart2_1: uart2grp-1 {
245 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]246 MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
247 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]248 >;
249 };
250 };
251
252 uart4 {
253 pinctrl_uart4_1: uart4grp-1 {
254 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]255 MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
256 MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]257 >;
258 };
259 };
260
261 usbotg {
262 pinctrl_usbotg_1: usbotggrp-1 {
263 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]264 MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]265 >;
266 };
Peter Chena10c22e2013-02-18 10:06:44 +0800[diff] [blame]267
268 pinctrl_usbotg_2: usbotggrp-2 {
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]269 fsl,pins = <
270 MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
Peter Chena10c22e2013-02-18 10:06:44 +0800[diff] [blame]271 >;
272 };
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]273 };
274
275 usdhc2 {
276 pinctrl_usdhc2_1: usdhc2grp-1 {
277 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]278 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
279 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
280 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
281 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
282 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
283 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
284 MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
285 MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
286 MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
287 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]288 >;
289 };
Christian Hempa5770902013-06-11 19:48:21 +0200[diff] [blame^]290
291 pinctrl_usdhc2_2: usdhc2grp-2 {
292 fsl,pins = <
293 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
294 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
295 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
296 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
297 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
298 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
299 >;
300 };
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]301 };
302
303 usdhc3 {
304 pinctrl_usdhc3_1: usdhc3grp-1 {
305 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]306 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
307 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
308 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
309 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
310 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
311 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
312 MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
313 MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
314 MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
315 MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]316 >;
317 };
318
319 pinctrl_usdhc3_2: usdhc3grp-2 {
320 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]321 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
322 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
323 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
324 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
325 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
326 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]327 >;
328 };
329 };
330
331 usdhc4 {
332 pinctrl_usdhc4_1: usdhc4grp-1 {
333 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]334 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
335 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
336 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
337 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
338 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
339 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
340 MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
341 MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
342 MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
343 MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]344 >;
345 };
346
347 pinctrl_usdhc4_2: usdhc4grp-2 {
348 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]349 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
350 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
351 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
352 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
353 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
354 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]355 >;
356 };
357 };
Huang Shijieee6ce3d2013-05-28 14:20:10 +0800[diff] [blame]358
359 weim {
360 pinctrl_weim_cs0_1: weim_cs0grp-1 {
361 fsl,pins = <
362 MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
363 >;
364 };
365
366 pinctrl_weim_nor_1: weimnorgrp-1 {
367 fsl,pins = <
368 MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1
369 MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1
370 MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
371 /* data */
372 MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
373 MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
374 MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
375 MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
376 MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
377 MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
378 MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
379 MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
380 MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
381 MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
382 MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
383 MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
384 MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
385 MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
386 MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
387 MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
388 /* address */
389 MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
390 MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
391 MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
392 MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
393 MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
394 MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
395 MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
396 MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
397 MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
398 MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
399 MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
400 MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1
401 MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1
402 MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1
403 MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1
404 MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1
405 MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1
406 MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1
407 MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1
408 MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1
409 MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1
410 MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1
411 MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1
412 MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1
413 >;
414 };
415
416 };
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]417 };
418 };
419
420 ipu2: ipu@02800000 {
421 #crtc-cells = <1>;
422 compatible = "fsl,imx6q-ipu";
423 reg = <0x02800000 0x400000>;
424 interrupts = <0 8 0x4 0 7 0x4>;
425 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
426 clock-names = "bus", "di0", "di1";
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]427 resets = <&src 4>;
Shawn Guo7c1da582013-02-04 23:09:16 +0800[diff] [blame]428 };
429 };
430};
Steffen Trumtrar41c043422013-03-28 16:23:35 +0100[diff] [blame]431
432&ldb {
433 clocks = <&clks 33>, <&clks 34>,
434 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
435 <&clks 135>, <&clks 136>;
436 clock-names = "di0_pll", "di1_pll",
437 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
438 "di0", "di1";
439
440 lvds-channel@0 {
441 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
442 };
443
444 lvds-channel@1 {
445 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
446 };
447};