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review.evervolv.com / android_kernel_oneplus_msm8996 / a5bb85dfffd38714d83cf7798886462d7314b90a / . / include / asm-blackfin / mach-bf548 / defBF548.h
blob: e46f56891e6a28f443e7ab518e1ce8d79834c856 [file] [log] [blame]
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1/*
2 * File: include/asm-blackfin/mach-bf548/defBF548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF548_H
32#define _DEF_BF548_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* SPORT0 Registers */
66
67#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
68#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
69#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
70#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
71#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
72#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
73#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
74#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
75#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
76#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
77#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
78#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
79#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
80#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
81#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
82#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
83#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
84#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
85#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
86#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
87#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
88#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
89
90/* EPPI0 Registers */
91
92#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
93#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
94#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
95#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
96#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
97#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
98#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
99#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
100#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
101#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
102#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
103#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
104#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
105#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
106
107/* UART2 Registers */
108
109#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
110#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
111#define UART2_GCTL 0xffc02108 /* Global Control Register */
112#define UART2_LCR 0xffc0210c /* Line Control Register */
113#define UART2_MCR 0xffc02110 /* Modem Control Register */
114#define UART2_LSR 0xffc02114 /* Line Status Register */
115#define UART2_MSR 0xffc02118 /* Modem Status Register */
116#define UART2_SCR 0xffc0211c /* Scratch Register */
117#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
118#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
119#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
120
121/* Two Wire Interface Registers (TWI1) */
122
Bryan Wu1d487f42007-10-11 00:30:56 +0800[diff] [blame]123#define TWI1_REGBASE 0xffc02200
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]124#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
125#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
126#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
127#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
128#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
129#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
130#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
131#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
132#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
133#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
134#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
135#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
136#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
137#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
138#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
139#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
140
141/* SPI2 Registers */
142
Bryan Wu1d487f42007-10-11 00:30:56 +0800[diff] [blame]143#define SPI2_REGBASE 0xffc02400
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]144#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
145#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
146#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
147#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
148#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
149#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
150#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
151
152/* CAN Controller 1 Config 1 Registers */
153
154#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
155#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
156#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
157#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
158#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
159#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
160#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
161#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
162#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
163#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
164#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
165#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
166#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
167
168/* CAN Controller 1 Config 2 Registers */
169
170#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
171#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
172#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
173#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
174#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
175#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
176#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
177#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
178#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
179#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
180#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
181#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
182#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
183
184/* CAN Controller 1 Clock/Interrupt/Counter Registers */
185
186#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
187#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
188#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
189#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
190#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
191#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
192#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
193#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
194#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
195#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
196#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
197#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
198#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
199#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
200#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
201#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
202
203/* CAN Controller 1 Mailbox Acceptance Registers */
204
205#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
206#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
207#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
208#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
209#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
210#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
211#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
212#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
213#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
214#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
215#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
216#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
217#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
218#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
219#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
220#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
221#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
222#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
223#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
224#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
225#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
226#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
227#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
228#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
229#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
230#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
231#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
232#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
233#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
234#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
235#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
236#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
237
238/* CAN Controller 1 Mailbox Acceptance Registers */
239
240#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
241#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
242#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
243#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
244#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
245#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
246#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
247#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
248#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
249#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
250#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
251#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
252#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
253#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
254#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
255#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
256#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
257#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
258#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
259#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
260#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
261#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
262#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
263#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
264#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
265#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
266#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
267#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
268#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
269#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
270#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
271#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
272
273/* CAN Controller 1 Mailbox Data Registers */
274
275#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
276#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
277#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
278#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
279#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
280#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
281#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
282#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
283#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
284#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
285#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
286#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
287#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
288#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
289#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
290#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
291#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
292#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
293#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
294#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
295#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
296#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
297#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
298#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
299#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
300#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
301#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
302#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
303#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
304#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
305#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
306#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
307#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
308#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
309#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
310#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
311#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
312#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
313#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
314#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
315#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
316#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
317#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
318#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
319#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
320#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
321#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
322#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
323#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
324#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
325#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
326#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
327#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
328#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
329#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
330#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
331#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
332#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
333#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
334#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
335#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
336#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
337#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
338#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
339#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
340#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
341#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
342#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
343#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
344#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
345#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
346#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
347#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
348#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
349#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
350#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
351#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
352#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
353#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
354#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
355#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
356#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
357#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
358#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
359#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
360#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
361#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
362#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
363#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
364#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
365#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
366#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
367#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
368#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
369#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
370#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
371#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
372#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
373#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
374#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
375#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
376#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
377#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
378#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
379#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
380#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
381#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
382#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
383#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
384#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
385#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
386#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
387#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
388#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
389#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
390#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
391#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
392#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
393#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
394#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
395#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
396#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
397#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
398#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
399#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
400#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
401#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
402#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
403
404/* CAN Controller 1 Mailbox Data Registers */
405
406#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
407#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
408#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
409#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
410#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
411#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
412#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
413#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
414#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
415#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
416#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
417#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
418#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
419#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
420#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
421#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
422#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
423#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
424#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
425#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
426#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
427#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
428#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
429#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
430#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
431#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
432#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
433#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
434#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
435#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
436#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
437#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
438#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
439#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
440#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
441#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
442#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
443#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
444#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
445#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
446#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
447#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
448#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
449#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
450#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
451#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
452#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
453#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
454#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
455#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
456#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
457#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
458#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
459#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
460#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
461#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
462#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
463#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
464#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
465#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
466#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
467#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
468#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
469#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
470#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
471#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
472#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
473#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
474#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
475#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
476#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
477#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
478#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
479#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
480#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
481#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
482#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
483#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
484#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
485#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
486#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
487#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
488#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
489#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
490#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
491#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
492#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
493#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
494#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
495#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
496#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
497#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
498#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
499#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
500#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
501#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
502#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
503#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
504#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
505#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
506#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
507#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
508#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
509#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
510#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
511#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
512#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
513#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
514#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
515#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
516#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
517#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
518#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
519#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
520#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
521#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
522#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
523#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
524#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
525#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
526#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
527#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
528#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
529#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
530#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
531#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
532#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
533#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
534
535/* ATAPI Registers */
536
537#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
538#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
539#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
540#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
541#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
542#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
543#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
544#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
545#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
546#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
547#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
548#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
549#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
550#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
551#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
552#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
553#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
554#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
555#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
556#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
557#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
558#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
559#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
560#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
561#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
562
563/* SDH Registers */
564
565#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
566#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
567#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
568#define SDH_COMMAND 0xffc0390c /* SDH Command */
569#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
570#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
571#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
572#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
573#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
574#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
575#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
576#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
577#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
578#define SDH_STATUS 0xffc03934 /* SDH Status */
579#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
580#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
581#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
582#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
583#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
584#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
585#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
586#define SDH_CFG 0xffc039c8 /* SDH Configuration */
587#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
588#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
589#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
590#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
591#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
592#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
593#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
594#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
595#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
596
597/* HOST Port Registers */
598
599#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
600#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
601#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
602
603/* USB Control Registers */
604
605#define USB_FADDR 0xffc03c00 /* Function address register */
606#define USB_POWER 0xffc03c04 /* Power management register */
607#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
608#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
609#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
610#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
611#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
612#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
613#define USB_FRAME 0xffc03c20 /* USB frame number */
614#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
615#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
616#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
617#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
618
619/* USB Packet Control Registers */
620
621#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
622#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
623#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
624#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
625#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
626#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
627#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
628#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
629#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
630#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
631#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
632#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
633#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
634
635/* USB Endpoint FIFO Registers */
636
637#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
638#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
639#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
640#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
641#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
642#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
643#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
644#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
645
646/* USB OTG Control Registers */
647
648#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
649#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
650#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
651
652/* USB Phy Control Registers */
653
654#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
655#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
656#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
657#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
658#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
659
660/* (APHY_CNTRL is for ADI usage only) */
661
662#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
663
664/* (APHY_CALIB is for ADI usage only) */
665
666#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
667#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
668
669/* (PHY_TEST is for ADI usage only) */
670
671#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
672#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
673#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
674
675/* USB Endpoint 0 Control Registers */
676
677#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
678#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
679#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
680#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
681#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
682#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
683#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
684#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
685#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
686
687/* USB Endpoint 1 Control Registers */
688
689#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
690#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
691#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
692#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
693#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
694#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
695#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
696#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
697#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
698#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
699
700/* USB Endpoint 2 Control Registers */
701
702#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
703#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
704#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
705#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
706#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
707#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
708#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
709#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
710#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
711#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
712
713/* USB Endpoint 3 Control Registers */
714
715#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
716#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
717#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
718#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
719#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
720#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
721#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
722#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
723#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
724#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
725
726/* USB Endpoint 4 Control Registers */
727
728#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
729#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
730#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
731#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
732#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
733#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
734#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
735#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
736#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
737#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
738
739/* USB Endpoint 5 Control Registers */
740
741#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
742#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
743#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
744#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
745#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
746#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
747#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
748#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
749#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
750#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
751
752/* USB Endpoint 6 Control Registers */
753
754#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
755#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
756#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
757#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
758#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
759#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
760#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
761#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
762#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
763#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
764
765/* USB Endpoint 7 Control Registers */
766
767#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
768#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
769#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
770#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
771#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
772#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
773#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
774#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
775#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
776#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
777#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
778#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
779
780/* USB Channel 0 Config Registers */
781
782#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
783#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
784#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
785#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
786#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
787
788/* USB Channel 1 Config Registers */
789
790#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
791#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
792#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
793#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
794#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
795
796/* USB Channel 2 Config Registers */
797
798#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
799#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
800#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
801#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
802#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
803
804/* USB Channel 3 Config Registers */
805
806#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
807#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
808#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
809#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
810#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
811
812/* USB Channel 4 Config Registers */
813
814#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
815#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
816#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
817#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
818#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
819
820/* USB Channel 5 Config Registers */
821
822#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
823#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
824#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
825#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
826#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
827
828/* USB Channel 6 Config Registers */
829
830#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
831#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
832#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
833#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
834#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
835
836/* USB Channel 7 Config Registers */
837
838#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
839#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
840#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
841#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
842#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
843
844/* Keypad Registers */
845
846#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
847#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
848#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
849#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
850#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
851#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
852
853/* Pixel Compositor (PIXC) Registers */
854
855#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
856#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
857#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
858#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
859#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
860#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
861#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
862#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
863#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
864#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
865#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
866#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
867#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
868#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
869#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
870#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
871#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
872#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
873#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
874
875/* Handshake MDMA 0 Registers */
876
877#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
878#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
879#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
880#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
881#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
882#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
883#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
884
885/* Handshake MDMA 1 Registers */
886
887#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
888#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
889#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
890#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
891#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
892#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
893#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
894
895
896/* ********************************************************** */
897/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
898/* and MULTI BIT READ MACROS */
899/* ********************************************************** */
900
901/* Bit masks for PIXC_CTL */
902
903#define PIXC_EN 0x1 /* Pixel Compositor Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]904#define OVR_A_EN 0x2 /* Overlay A Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]905#define OVR_B_EN 0x4 /* Overlay B Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]906#define IMG_FORM 0x8 /* Image Data Format */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]907#define OVR_FORM 0x10 /* Overlay Data Format */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]908#define OUT_FORM 0x20 /* Output Data Format */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]909#define UDS_MOD 0x40 /* Resampling Mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]910#define TC_EN 0x80 /* Transparent Color Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]911#define IMG_STAT 0x300 /* Image FIFO Status */
912#define OVR_STAT 0xc00 /* Overlay FIFO Status */
913#define WM_LVL 0x3000 /* FIFO Watermark Level */
914
915/* Bit masks for PIXC_AHSTART */
916
917#define A_HSTART 0xfff /* Horizontal Start Coordinates */
918
919/* Bit masks for PIXC_AHEND */
920
921#define A_HEND 0xfff /* Horizontal End Coordinates */
922
923/* Bit masks for PIXC_AVSTART */
924
925#define A_VSTART 0x3ff /* Vertical Start Coordinates */
926
927/* Bit masks for PIXC_AVEND */
928
929#define A_VEND 0x3ff /* Vertical End Coordinates */
930
931/* Bit masks for PIXC_ATRANSP */
932
933#define A_TRANSP 0xf /* Transparency Value */
934
935/* Bit masks for PIXC_BHSTART */
936
937#define B_HSTART 0xfff /* Horizontal Start Coordinates */
938
939/* Bit masks for PIXC_BHEND */
940
941#define B_HEND 0xfff /* Horizontal End Coordinates */
942
943/* Bit masks for PIXC_BVSTART */
944
945#define B_VSTART 0x3ff /* Vertical Start Coordinates */
946
947/* Bit masks for PIXC_BVEND */
948
949#define B_VEND 0x3ff /* Vertical End Coordinates */
950
951/* Bit masks for PIXC_BTRANSP */
952
953#define B_TRANSP 0xf /* Transparency Value */
954
955/* Bit masks for PIXC_INTRSTAT */
956
957#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]958#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]959#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]960#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]961
962/* Bit masks for PIXC_RYCON */
963
964#define A11 0x3ff /* A11 in the Coefficient Matrix */
965#define A12 0xffc00 /* A12 in the Coefficient Matrix */
966#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
967#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]968
969/* Bit masks for PIXC_GUCON */
970
971#define A21 0x3ff /* A21 in the Coefficient Matrix */
972#define A22 0xffc00 /* A22 in the Coefficient Matrix */
973#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
974#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]975
976/* Bit masks for PIXC_BVCON */
977
978#define A31 0x3ff /* A31 in the Coefficient Matrix */
979#define A32 0xffc00 /* A32 in the Coefficient Matrix */
980#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
981#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]982
983/* Bit masks for PIXC_CCBIAS */
984
985#define A14 0x3ff /* A14 in the Bias Vector */
986#define A24 0xffc00 /* A24 in the Bias Vector */
987#define A34 0x3ff00000 /* A34 in the Bias Vector */
988
989/* Bit masks for PIXC_TC */
990
991#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
992#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
993#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
994
995/* Bit masks for HOST_CONTROL */
996
997#define HOST_EN 0x1 /* Host Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]998#define HOST_END 0x2 /* Host Endianess */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]999#define DATA_SIZE 0x4 /* Data Size */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1000#define HOST_RST 0x8 /* Host Reset */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1001#define HRDY_OVR 0x20 /* Host Ready Override */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1002#define INT_MODE 0x40 /* Interrupt Mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1003#define BT_EN 0x80 /* Bus Timeout Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1004#define EHW 0x100 /* Enable Host Write */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1005#define EHR 0x200 /* Enable Host Read */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1006#define BDR 0x400 /* Burst DMA Requests */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1007
1008/* Bit masks for HOST_STATUS */
1009
Mike Frysingerf26825d2007-11-21 16:17:11 +0800[diff] [blame]1010#define DMA_READY 0x1 /* DMA Ready */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1011#define FIFOFULL 0x2 /* FIFO Full */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1012#define FIFOEMPTY 0x4 /* FIFO Empty */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1013#define COMPLETE 0x8 /* DMA Complete */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1014#define HSHK 0x10 /* Host Handshake */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1015#define TIMEOUT 0x20 /* Host Timeout */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1016#define HIRQ 0x40 /* Host Interrupt Request */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1017#define ALLOW_CNFG 0x80 /* Allow New Configuration */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1018#define DMA_DIR 0x100 /* DMA Direction */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1019#define BTE 0x200 /* Bus Timeout Enabled */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1020
1021/* Bit masks for HOST_TIMEOUT */
1022
1023#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1024
1025/* Bit masks for KPAD_CTL */
1026
1027#define KPAD_EN 0x1 /* Keypad Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1028#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
1029#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
1030#define KPAD_COLEN 0xe000 /* Column Enable Width */
1031
1032/* Bit masks for KPAD_PRESCALE */
1033
1034#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
1035
1036/* Bit masks for KPAD_MSEL */
1037
1038#define DBON_SCALE 0xff /* Debounce Scale Value */
1039#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
1040
1041/* Bit masks for KPAD_ROWCOL */
1042
1043#define KPAD_ROW 0xff /* Rows Pressed */
1044#define KPAD_COL 0xff00 /* Columns Pressed */
1045
1046/* Bit masks for KPAD_STAT */
1047
1048#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1049#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
1050#define KPAD_PRESSED 0x8 /* Key press current status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1051
1052/* Bit masks for KPAD_SOFTEVAL */
1053
1054#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1055
1056/* Bit masks for SDH_COMMAND */
1057
1058#define CMD_IDX 0x3f /* Command Index */
1059#define CMD_RSP 0x40 /* Response */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1060#define CMD_L_RSP 0x80 /* Long Response */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1061#define CMD_INT_E 0x100 /* Command Interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1062#define CMD_PEND_E 0x200 /* Command Pending */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1063#define CMD_E 0x400 /* Command Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1064
1065/* Bit masks for SDH_PWR_CTL */
1066
1067#define PWR_ON 0x3 /* Power On */
1068#if 0
1069#define TBD 0x3c /* TBD */
1070#endif
1071#define SD_CMD_OD 0x40 /* Open Drain Output */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1072#define ROD_CTL 0x80 /* Rod Control */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1073
1074/* Bit masks for SDH_CLK_CTL */
1075
1076#define CLKDIV 0xff /* MC_CLK Divisor */
1077#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1078#define PWR_SV_E 0x200 /* Power Save Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1079#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1080#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1081
1082/* Bit masks for SDH_RESP_CMD */
1083
1084#define RESP_CMD 0x3f /* Response Command */
1085
1086/* Bit masks for SDH_DATA_CTL */
1087
1088#define DTX_E 0x1 /* Data Transfer Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1089#define DTX_DIR 0x2 /* Data Transfer Direction */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1090#define DTX_MODE 0x4 /* Data Transfer Mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1091#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1092#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
1093
1094/* Bit masks for SDH_STATUS */
1095
1096#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1097#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
Cliff Caia5bb85d2007-12-21 21:04:40 +0800[diff] [blame^]1098#define CMD_TIME_OUT 0x4 /* CMD Time Out */
1099#define DAT_TIME_OUT 0x8 /* Data Time Out */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1100#define TX_UNDERRUN 0x10 /* Transmit Underrun */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1101#define RX_OVERRUN 0x20 /* Receive Overrun */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1102#define CMD_RESP_END 0x40 /* CMD Response End */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1103#define CMD_SENT 0x80 /* CMD Sent */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1104#define DAT_END 0x100 /* Data End */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1105#define START_BIT_ERR 0x200 /* Start Bit Error */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1106#define DAT_BLK_END 0x400 /* Data Block End */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1107#define CMD_ACT 0x800 /* CMD Active */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1108#define TX_ACT 0x1000 /* Transmit Active */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1109#define RX_ACT 0x2000 /* Receive Active */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1110#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1111#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1112#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1113#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1114#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1115#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1116#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1117#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1118
1119/* Bit masks for SDH_STATUS_CLR */
1120
1121#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1122#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1123#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1124#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1125#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1126#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1127#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1128#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1129#define DAT_END_STAT 0x100 /* Data End Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1130#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1131#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1132
1133/* Bit masks for SDH_MASK0 */
1134
1135#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1136#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1137#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1138#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1139#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1140#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1141#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1142#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1143#define DAT_END_MASK 0x100 /* Data End Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1144#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1145#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1146#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1147#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1148#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1149#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1150#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1151#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1152#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1153#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1154#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1155#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1156#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1157
1158/* Bit masks for SDH_FIFO_CNT */
1159
1160#define FIFO_COUNT 0x7fff /* FIFO Count */
1161
1162/* Bit masks for SDH_E_STATUS */
1163
1164#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1165#define SD_CARD_DET 0x10 /* SD Card Detect */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1166
1167/* Bit masks for SDH_E_MASK */
1168
1169#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1170#define SCD_MSK 0x40 /* Mask Card Detect */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1171
1172/* Bit masks for SDH_CFG */
1173
1174#define CLKS_EN 0x1 /* Clocks Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1175#define SD4E 0x4 /* SDIO 4-Bit Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1176#define MWE 0x8 /* Moving Window Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1177#define SD_RST 0x10 /* SDMMC Reset */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1178#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1179#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1180#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1181
1182/* Bit masks for SDH_RD_WAIT_EN */
1183
1184#define RWR 0x1 /* Read Wait Request */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1185
1186/* Bit masks for ATAPI_CONTROL */
1187
1188#define PIO_START 0x1 /* Start PIO/Reg Op */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1189#define MULTI_START 0x2 /* Start Multi-DMA Op */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1190#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1191#define XFER_DIR 0x8 /* Transfer Direction */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1192#define IORDY_EN 0x10 /* IORDY Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1193#define FIFO_FLUSH 0x20 /* Flush FIFOs */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1194#define SOFT_RST 0x40 /* Soft Reset */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1195#define DEV_RST 0x80 /* Device Reset */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1196#define TFRCNT_RST 0x100 /* Trans Count Reset */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1197#define END_ON_TERM 0x200 /* End/Terminate Select */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1198#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1199#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
1200
1201/* Bit masks for ATAPI_STATUS */
1202
1203#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1204#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1205#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1206#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
1207
1208/* Bit masks for ATAPI_DEV_ADDR */
1209
1210#define DEV_ADDR 0x1f /* Device Address */
1211
1212/* Bit masks for ATAPI_INT_MASK */
1213
1214#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1215#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1216#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1217#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1218#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1219#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1220#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1221#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1222#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1223
1224/* Bit masks for ATAPI_INT_STATUS */
1225
1226#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1227#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1228#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1229#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1230#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1231#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1232#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1233#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1234#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1235
1236/* Bit masks for ATAPI_LINE_STATUS */
1237
1238#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1239#define ATAPI_DASP 0x2 /* Device dasp to host line status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1240#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1241#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1242#define ATAPI_ADDR 0x70 /* ATAPI address line status */
1243#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1244#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1245#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1246#define ATAPI_DIORN 0x400 /* ATAPI read line status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1247#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1248
1249/* Bit masks for ATAPI_SM_STATE */
1250
1251#define PIO_CSTATE 0xf /* PIO mode state machine current state */
1252#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
1253#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
1254#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
1255
1256/* Bit masks for ATAPI_TERMINATE */
1257
1258#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1259
1260/* Bit masks for ATAPI_REG_TIM_0 */
1261
1262#define T2_REG 0xff /* End of cycle time for register access transfers */
1263#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
1264
1265/* Bit masks for ATAPI_PIO_TIM_0 */
1266
1267#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
1268#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
1269#define T4_REG 0xf000 /* DIOW data hold */
1270
1271/* Bit masks for ATAPI_PIO_TIM_1 */
1272
1273#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
1274
1275/* Bit masks for ATAPI_MULTI_TIM_0 */
1276
1277#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
1278#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
1279
1280/* Bit masks for ATAPI_MULTI_TIM_1 */
1281
1282#define TKW 0xff /* Selects DIOW negated pulsewidth */
1283#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
1284
1285/* Bit masks for ATAPI_MULTI_TIM_2 */
1286
1287#define TH 0xff /* Selects DIOW data hold */
1288#define TEOC 0xff00 /* Selects end of cycle for DMA */
1289
1290/* Bit masks for ATAPI_ULTRA_TIM_0 */
1291
1292#define TACK 0xff /* Selects setup and hold times for TACK */
1293#define TENV 0xff00 /* Selects envelope time */
1294
1295/* Bit masks for ATAPI_ULTRA_TIM_1 */
1296
1297#define TDVS 0xff /* Selects data valid setup time */
1298#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
1299
1300/* Bit masks for ATAPI_ULTRA_TIM_2 */
1301
1302#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
1303#define TMLI 0xff00 /* Selects interlock time */
1304
1305/* Bit masks for ATAPI_ULTRA_TIM_3 */
1306
1307#define TZAH 0xff /* Selects minimum delay required for output */
1308#define READY_PAUSE 0xff00 /* Selects ready to pause */
1309
1310/* Bit masks for TIMER_ENABLE1 */
1311
1312#define TIMEN8 0x1 /* Timer 8 Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1313#define TIMEN9 0x2 /* Timer 9 Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1314#define TIMEN10 0x4 /* Timer 10 Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1315
1316/* Bit masks for TIMER_DISABLE1 */
1317
1318#define TIMDIS8 0x1 /* Timer 8 Disable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1319#define TIMDIS9 0x2 /* Timer 9 Disable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1320#define TIMDIS10 0x4 /* Timer 10 Disable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1321
1322/* Bit masks for TIMER_STATUS1 */
1323
1324#define TIMIL8 0x1 /* Timer 8 Interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1325#define TIMIL9 0x2 /* Timer 9 Interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1326#define TIMIL10 0x4 /* Timer 10 Interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1327#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1328#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1329#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1330#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1331#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1332#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1333
1334/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1335
1336/* Bit masks for USB_FADDR */
1337
1338#define FUNCTION_ADDRESS 0x7f /* Function address */
1339
1340/* Bit masks for USB_POWER */
1341
1342#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1343#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1344#define RESUME_MODE 0x4 /* DMA Mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1345#define RESET 0x8 /* Reset indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1346#define HS_MODE 0x10 /* High Speed mode indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1347#define HS_ENABLE 0x20 /* high Speed Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1348#define SOFT_CONN 0x40 /* Soft connect */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1349#define ISO_UPDATE 0x80 /* Isochronous update */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1350
1351/* Bit masks for USB_INTRTX */
1352
1353#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1354#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1355#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1356#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1357#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1358#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1359#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1360#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1361
1362/* Bit masks for USB_INTRRX */
1363
1364#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1365#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1366#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1367#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1368#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1369#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1370#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1371
1372/* Bit masks for USB_INTRTXE */
1373
1374#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1375#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1376#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1377#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1378#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1379#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1380#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1381#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1382
1383/* Bit masks for USB_INTRRXE */
1384
1385#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1386#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1387#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1388#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1389#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1390#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1391#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1392
1393/* Bit masks for USB_INTRUSB */
1394
1395#define SUSPEND_B 0x1 /* Suspend indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1396#define RESUME_B 0x2 /* Resume indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1397#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1398#define SOF_B 0x8 /* Start of frame */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1399#define CONN_B 0x10 /* Connection indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1400#define DISCON_B 0x20 /* Disconnect indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1401#define SESSION_REQ_B 0x40 /* Session Request */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1402#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1403
1404/* Bit masks for USB_INTRUSBE */
1405
1406#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1407#define RESUME_BE 0x2 /* Resume indicator int enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1408#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1409#define SOF_BE 0x8 /* Start of frame int enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1410#define CONN_BE 0x10 /* Connection indicator int enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1411#define DISCON_BE 0x20 /* Disconnect indicator int enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1412#define SESSION_REQ_BE 0x40 /* Session Request int enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1413#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1414
1415/* Bit masks for USB_FRAME */
1416
1417#define FRAME_NUMBER 0x7ff /* Frame number */
1418
1419/* Bit masks for USB_INDEX */
1420
1421#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1422
1423/* Bit masks for USB_GLOBAL_CTL */
1424
1425#define GLOBAL_ENA 0x1 /* enables USB module */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1426#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1427#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1428#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1429#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1430#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1431#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1432#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1433#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1434#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1435#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1436#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1437#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1438#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1439#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1440
1441/* Bit masks for USB_OTG_DEV_CTL */
1442
1443#define SESSION 0x1 /* session indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1444#define HOST_REQ 0x2 /* Host negotiation request */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1445#define HOST_MODE 0x4 /* indicates USBDRC is a host */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1446#define VBUS0 0x8 /* Vbus level indicator[0] */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1447#define VBUS1 0x10 /* Vbus level indicator[1] */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1448#define LSDEV 0x20 /* Low-speed indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1449#define FSDEV 0x40 /* Full or High-speed indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1450#define B_DEVICE 0x80 /* A' or 'B' device indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1451
1452/* Bit masks for USB_OTG_VBUS_IRQ */
1453
1454#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1455#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1456#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1457#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1458#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1459#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1460
1461/* Bit masks for USB_OTG_VBUS_MASK */
1462
1463#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1464#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1465#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1466#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1467#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1468#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1469
1470/* Bit masks for USB_CSR0 */
1471
1472#define RXPKTRDY 0x1 /* data packet receive indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1473#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1474#define STALL_SENT 0x4 /* STALL handshake sent */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1475#define DATAEND 0x8 /* Data end indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1476#define SETUPEND 0x10 /* Setup end */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1477#define SENDSTALL 0x20 /* Send STALL handshake */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1478#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1479#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1480#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1481#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1482#define SETUPPKT_H 0x8 /* send Setup token host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1483#define ERROR_H 0x10 /* timeout error indicator host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1484#define REQPKT_H 0x20 /* Request an IN transaction host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1485#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1486#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1487
1488/* Bit masks for USB_COUNT0 */
1489
1490#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1491
1492/* Bit masks for USB_NAKLIMIT0 */
1493
1494#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1495
1496/* Bit masks for USB_TX_MAX_PACKET */
1497
1498#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1499
1500/* Bit masks for USB_RX_MAX_PACKET */
1501
1502#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1503
1504/* Bit masks for USB_TXCSR */
1505
1506#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1507#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1508#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1509#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1510#define STALL_SEND_T 0x10 /* issue a Stall handshake */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1511#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1512#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1513#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1514#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1515#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1516#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1517#define ISO_T 0x4000 /* enable Isochronous transfers */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1518#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1519#define ERROR_TH 0x4 /* error condition host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1520#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1521#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1522
1523/* Bit masks for USB_TXCOUNT */
1524
1525#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1526
1527/* Bit masks for USB_RXCSR */
1528
1529#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1530#define FIFO_FULL_R 0x2 /* FIFO not empty */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1531#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1532#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1533#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1534#define STALL_SEND_R 0x20 /* issue a Stall handshake */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1535#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1536#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1537#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1538#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1539#define DISNYET_R 0x1000 /* disable Nyet handshakes */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1540#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1541#define ISO_R 0x4000 /* enable Isochronous transfers */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1542#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1543#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1544#define REQPKT_RH 0x20 /* request an IN transaction host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1545#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1546#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1547#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1548#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1549
1550/* Bit masks for USB_RXCOUNT */
1551
1552#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1553
1554/* Bit masks for USB_TXTYPE */
1555
1556#define TARGET_EP_NO_T 0xf /* EP number */
1557#define PROTOCOL_T 0xc /* transfer type */
1558
1559/* Bit masks for USB_TXINTERVAL */
1560
1561#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1562
1563/* Bit masks for USB_RXTYPE */
1564
1565#define TARGET_EP_NO_R 0xf /* EP number */
1566#define PROTOCOL_R 0xc /* transfer type */
1567
1568/* Bit masks for USB_RXINTERVAL */
1569
1570#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1571
1572/* Bit masks for USB_DMA_INTERRUPT */
1573
1574#define DMA0_INT 0x1 /* DMA0 pending interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1575#define DMA1_INT 0x2 /* DMA1 pending interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1576#define DMA2_INT 0x4 /* DMA2 pending interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1577#define DMA3_INT 0x8 /* DMA3 pending interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1578#define DMA4_INT 0x10 /* DMA4 pending interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1579#define DMA5_INT 0x20 /* DMA5 pending interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1580#define DMA6_INT 0x40 /* DMA6 pending interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1581#define DMA7_INT 0x80 /* DMA7 pending interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1582
1583/* Bit masks for USB_DMAxCONTROL */
1584
1585#define DMA_ENA 0x1 /* DMA enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1586#define DIRECTION 0x2 /* direction of DMA transfer */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1587#define MODE 0x4 /* DMA Bus error */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1588#define INT_ENA 0x8 /* Interrupt enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1589#define EPNUM 0xf0 /* EP number */
1590#define BUSERROR 0x100 /* DMA Bus error */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1591
1592/* Bit masks for USB_DMAxADDRHIGH */
1593
1594#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1595
1596/* Bit masks for USB_DMAxADDRLOW */
1597
1598#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1599
1600/* Bit masks for USB_DMAxCOUNTHIGH */
1601
1602#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1603
1604/* Bit masks for USB_DMAxCOUNTLOW */
1605
1606#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1607
1608/* Bit masks for HMDMAx_CONTROL */
1609
1610#define HMDMAEN 0x1 /* Handshake MDMA Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1611#define REP 0x2 /* Handshake MDMA Request Polarity */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1612#define UTE 0x8 /* Urgency Threshold Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1613#define OIE 0x10 /* Overflow Interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1614#define BDIE 0x20 /* Block Done Interrupt Enable */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1615#define MBDI 0x40 /* Mask Block Done Interrupt */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1616#define DRQ 0x300 /* Handshake MDMA Request Type */
1617#define RBC 0x1000 /* Force Reload of BCOUNT */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1618#define PS 0x2000 /* Pin Status */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1619#define OI 0x4000 /* Overflow Interrupt Generated */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1620#define BDI 0x8000 /* Block Done Interrupt Generated */
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1621
1622/* ******************************************* */
1623/* MULTI BIT MACRO ENUMERATIONS */
1624/* ******************************************* */
1625
1626
1627#endif /* _DEF_BF548_H */